xref: /openwifi/driver/hw_def.h (revision 311b18bf7c5a29112a0ac68c32358ca8512d4269) 
1 // Xianjun jiao. [email protected]; [email protected]
2 
3 const char *sdr_compatible_str = "sdr,sdr";
4 
5 enum openwifi_band {
6 	BAND_900M = 0,
7 	BAND_2_4GHZ,
8 	BAND_3_65GHZ,
9 	BAND_5_0GHZ,
10 	BAND_5_8GHZ,
11 	BAND_5_9GHZ,
12 	BAND_60GHZ,
13 };
14 
15 // ------------------------------------tx interface----------------------------------------
16 const char *tx_intf_compatible_str = "sdr,tx_intf";
17 
18 #define TX_INTF_REG_MULTI_RST_ADDR                 (0*4)
19 #define TX_INTF_REG_MIXER_CFG_ADDR                 (1*4)
20 #define TX_INTF_REG_WIFI_TX_MODE_ADDR              (2*4)
21 #define TX_INTF_REG_IQ_SRC_SEL_ADDR                (3*4)
22 #define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR         (4*4)
23 #define TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR    (5*4)
24 #define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR  (6*4)
25 #define TX_INTF_REG_MISC_SEL_ADDR                  (7*4)
26 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR      (8*4)
27 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR      (9*4)
28 #define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR           (10*4)
29 #define TX_INTF_REG_TX_HOLD_THRESHOLD_ADDR         (12*4)
30 #define TX_INTF_REG_BB_GAIN_ADDR                   (13*4)
31 #define TX_INTF_REG_INTERRUPT_SEL_ADDR             (14*4)
32 #define TX_INTF_REG_ANT_SEL_ADDR                   (16*4)
33 #define TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR    (21*4)
34 #define TX_INTF_REG_PKT_INFO_ADDR                  (22*4)
35 #define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR     (24*4)
36 
37 #define TX_INTF_NUM_ANTENNA                        2
38 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL            (64/8)
39 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS    3
40 
41 enum tx_intf_mode {
42 	TX_INTF_AXIS_LOOP_BACK = 0,
43 	TX_INTF_BYPASS,
44 	TX_INTF_BW_20MHZ_AT_0MHZ_ANT0,
45 	TX_INTF_BW_20MHZ_AT_0MHZ_ANT1,
46 	TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,
47 	TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,
48 	TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,
49 	TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
50 };
51 
52 const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10};
53 
54 struct tx_intf_driver_api {
55 	u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
56 
57 	u32 (*reg_read)(u32 reg);
58 	void (*reg_write)(u32 reg, u32 value);
59 
60 	u32 (*TX_INTF_REG_MULTI_RST_read)(void);
61 	u32 (*TX_INTF_REG_MIXER_CFG_read)(void);
62 	u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void);
63 	u32 (*TX_INTF_REG_IQ_SRC_SEL_read)(void);
64 	u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void);
65 	u32 (*TX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);
66 	u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void);
67 	u32 (*TX_INTF_REG_MISC_SEL_read)(void);
68 	u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
69 	u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
70 	u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
71 	u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void);
72 	u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void);
73 	u32 (*TX_INTF_REG_BB_GAIN_read)(void);
74 	u32 (*TX_INTF_REG_ANT_SEL_read)(void);
75 	u32 (*TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read)(void);
76 	u32 (*TX_INTF_REG_PKT_INFO_read)(void);
77 	u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void);
78 
79 	void (*TX_INTF_REG_MULTI_RST_write)(u32 value);
80 	void (*TX_INTF_REG_MIXER_CFG_write)(u32 value);
81 	void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value);
82 	void (*TX_INTF_REG_IQ_SRC_SEL_write)(u32 value);
83 	void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value);
84 	void (*TX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);
85 	void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value);
86 	void (*TX_INTF_REG_MISC_SEL_write)(u32 value);
87 	void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
88 	void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
89 	void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
90 	void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value);
91 	void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value);
92 	void (*TX_INTF_REG_BB_GAIN_write)(u32 value);
93 	void (*TX_INTF_REG_ANT_SEL_write)(u32 value);
94 	void (*TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write)(u32 value);
95 	void (*TX_INTF_REG_PKT_INFO_write)(u32 value);
96 };
97 
98 // ------------------------------------rx interface----------------------------------------
99 const char *rx_intf_compatible_str = "sdr,rx_intf";
100 
101 #define RX_INTF_REG_MULTI_RST_ADDR                 (0*4)
102 #define RX_INTF_REG_MIXER_CFG_ADDR                 (1*4)
103 #define RX_INTF_REG_INTERRUPT_TEST_ADDR            (2*4)
104 #define RX_INTF_REG_IQ_SRC_SEL_ADDR                (3*4)
105 #define RX_INTF_REG_IQ_CTRL_ADDR                   (4*4)
106 #define RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR    (5*4)
107 #define RX_INTF_REG_START_TRANS_TO_PS_ADDR         (6*4)
108 #define RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR (7*4)
109 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR      (8*4)
110 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR      (9*4)
111 #define RX_INTF_REG_CFG_DATA_TO_ANT_ADDR           (10*4)
112 #define RX_INTF_REG_BB_GAIN_ADDR                   (11*4)
113 #define RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR         (12*4)
114 #define RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR     (13*4)
115 #define RX_INTF_REG_ANT_SEL_ADDR                   (16*4)
116 
117 #define RX_INTF_NUM_ANTENNA                        2
118 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL            (64/8)
119 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS    3
120 
121 enum rx_intf_mode {
122 	RX_INTF_AXIS_LOOP_BACK = 0,
123 	RX_INTF_BYPASS,
124 	RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,
125 	RX_INTF_BW_20MHZ_AT_0MHZ_ANT1,
126 	RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,
127 	RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,
128 	RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,
129 	RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
130 };
131 
132 const int rx_intf_fo_mapping[] = {0,0,0,0,-10,-10,10,10};
133 
134 struct rx_intf_driver_api {
135 	u32 io_start;
136 	u32 base_addr;
137 
138 	u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
139 
140 	u32 (*reg_read)(u32 reg);
141 	void (*reg_write)(u32 reg, u32 value);
142 
143 	u32 (*RX_INTF_REG_MULTI_RST_read)(void);
144 	u32 (*RX_INTF_REG_MIXER_CFG_read)(void);
145 	u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void);
146 	u32 (*RX_INTF_REG_IQ_CTRL_read)(void);
147 	u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);
148 	u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void);
149 	u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void);
150 	u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
151 	u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
152 	u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
153 	u32 (*RX_INTF_REG_ANT_SEL_read)(void);
154 	u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void);
155 	void (*RX_INTF_REG_MULTI_RST_write)(u32 value);
156 	void (*RX_INTF_REG_MIXER_CFG_write)(u32 value);
157 	void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value);
158 	void (*RX_INTF_REG_IQ_CTRL_write)(u32 value);
159 	void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);
160 	void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value);
161 	void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value);
162 	void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
163 	void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
164 	void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
165 	void (*RX_INTF_REG_BB_GAIN_write)(u32 value);
166 	void (*RX_INTF_REG_ANT_SEL_write)(u32 value);
167 	void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value);
168 
169 	void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value);
170 	void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value);
171 	void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value);
172 };
173 
174 // ----------------------------------openofdm rx-------------------------------
175 const char *openofdm_rx_compatible_str = "sdr,openofdm_rx";
176 
177 #define OPENOFDM_RX_REG_MULTI_RST_ADDR     (0*4)
178 #define OPENOFDM_RX_REG_ENABLE_ADDR        (1*4)
179 #define OPENOFDM_RX_REG_POWER_THRES_ADDR   (2*4)
180 #define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR   (3*4)
181 #define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4)
182 
183 enum openofdm_rx_mode {
184 	OPENOFDM_RX_TEST = 0,
185 	OPENOFDM_RX_NORMAL,
186 };
187 
188 struct openofdm_rx_driver_api {
189 	u32 power_thres;
190 	u32 min_plateau;
191 
192 	u32 (*hw_init)(enum openofdm_rx_mode mode);
193 
194 	u32 (*reg_read)(u32 reg);
195 	void (*reg_write)(u32 reg, u32 value);
196 
197 	u32 (*OPENOFDM_RX_REG_STATE_HISTORY_read)(void);
198 
199 	void (*OPENOFDM_RX_REG_MULTI_RST_write)(u32 value);
200 	void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value);
201 	void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value);
202 	void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value);
203 };
204 
205 // ---------------------------------------openofdm tx-------------------------------
206 const char *openofdm_tx_compatible_str = "sdr,openofdm_tx";
207 
208 #define OPENOFDM_TX_REG_MULTI_RST_ADDR                 (0*4)
209 #define OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR          (1*4)
210 #define OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR           (2*4)
211 
212 enum openofdm_tx_mode {
213 	OPENOFDM_TX_TEST = 0,
214 	OPENOFDM_TX_NORMAL,
215 };
216 
217 struct openofdm_tx_driver_api {
218 	u32 (*hw_init)(enum openofdm_tx_mode mode);
219 
220 	u32 (*reg_read)(u32 reg);
221 	void (*reg_write)(u32 reg, u32 value);
222 
223 	void (*OPENOFDM_TX_REG_MULTI_RST_write)(u32 value);
224 	void (*OPENOFDM_TX_REG_INIT_PILOT_STATE_write)(u32 value);
225 	void (*OPENOFDM_TX_REG_INIT_DATA_STATE_write)(u32 value);
226 };
227 
228 // ---------------------------------------xpu low MAC controller-------------------------------
229 
230 // extra filter flag together with enum ieee80211_filter_flags in mac80211.h
231 #define UNICAST_FOR_US     (1<<9)
232 #define BROADCAST_ALL_ONE  (1<<10)
233 #define BROADCAST_ALL_ZERO (1<<11)
234 #define MY_BEACON          (1<<12)
235 #define MONITOR_ALL        (1<<13)
236 
237 const char *xpu_compatible_str = "sdr,xpu";
238 
239 #define XPU_REG_MULTI_RST_ADDR            (0*4)
240 #define XPU_REG_SRC_SEL_ADDR              (1*4)
241 #define XPU_REG_TSF_LOAD_VAL_LOW_ADDR     (2*4)
242 #define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR    (3*4)
243 #define XPU_REG_BAND_CHANNEL_ADDR         (4*4)
244 #define XPU_REG_RSSI_DB_CFG_ADDR          (7*4)
245 #define XPU_REG_LBT_TH_ADDR               (8*4)
246 #define XPU_REG_CSMA_DEBUG_ADDR           (9*4)
247 #define XPU_REG_BB_RF_DELAY_ADDR          (10*4)
248 #define XPU_REG_MAX_NUM_RETRANS_ADDR      (11*4)
249 #define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR  (16*4)
250 #define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR  (17*4)
251 #define XPU_REG_SEND_ACK_WAIT_TOP_ADDR    (18*4)
252 #define XPU_REG_CSMA_CFG_ADDR             (19*4)
253 
254 #define XPU_REG_SLICE_COUNT_TOTAL0_ADDR   (20*4)
255 #define XPU_REG_SLICE_COUNT_START0_ADDR   (21*4)
256 #define XPU_REG_SLICE_COUNT_END0_ADDR     (22*4)
257 #define XPU_REG_SLICE_COUNT_TOTAL1_ADDR   (23*4)
258 #define XPU_REG_SLICE_COUNT_START1_ADDR   (24*4)
259 #define XPU_REG_SLICE_COUNT_END1_ADDR     (25*4)
260 
261 #define XPU_REG_CTS_TO_RTS_CONFIG_ADDR    (26*4)
262 #define XPU_REG_FILTER_FLAG_ADDR          (27*4)
263 #define XPU_REG_BSSID_FILTER_LOW_ADDR     (28*4)
264 #define XPU_REG_BSSID_FILTER_HIGH_ADDR    (29*4)
265 #define XPU_REG_MAC_ADDR_LOW_ADDR         (30*4)
266 #define XPU_REG_MAC_ADDR_HIGH_ADDR        (31*4)
267 
268 #define XPU_REG_FC_DI_ADDR                (34*4)
269 #define XPU_REG_ADDR1_LOW_ADDR            (35*4)
270 #define XPU_REG_ADDR1_HIGH_ADDR           (36*4)
271 #define XPU_REG_ADDR2_LOW_ADDR            (37*4)
272 #define XPU_REG_ADDR2_HIGH_ADDR           (38*4)
273 #define XPU_REG_ADDR3_LOW_ADDR            (39*4)
274 #define XPU_REG_ADDR3_HIGH_ADDR           (40*4)
275 
276 #define XPU_REG_SC_LOW_ADDR               (41*4)
277 #define XPU_REG_ADDR4_HIGH_ADDR           (42*4)
278 #define XPU_REG_ADDR4_LOW_ADDR            (43*4)
279 
280 #define XPU_REG_TRX_STATUS_ADDR           (50*4)
281 #define XPU_REG_TX_RESULT_ADDR            (51*4)
282 
283 #define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR  (58*4)
284 #define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4)
285 
286 #define XPU_REG_RSSI_HALF_DB_ADDR         (60*4)
287 #define XPU_REG_IQ_RSSI_HALF_DB_ADDR      (61*4)
288 
289 enum xpu_mode {
290 	XPU_TEST = 0,
291 	XPU_NORMAL,
292 };
293 
294 struct xpu_driver_api {
295 	u32 (*hw_init)(enum xpu_mode mode);
296 
297 	u32 (*reg_read)(u32 reg);
298 	void (*reg_write)(u32 reg, u32 value);
299 
300 	void (*XPU_REG_MULTI_RST_write)(u32 value);
301 	u32  (*XPU_REG_MULTI_RST_read)(void);
302 
303 	void (*XPU_REG_SRC_SEL_write)(u32 value);
304 	u32  (*XPU_REG_SRC_SEL_read)(void);
305 
306 	void (*XPU_REG_RECV_ACK_COUNT_TOP0_write)(u32 value);
307 	u32  (*XPU_REG_RECV_ACK_COUNT_TOP0_read)(void);
308 
309 	void (*XPU_REG_RECV_ACK_COUNT_TOP1_write)(u32 value);
310 	u32  (*XPU_REG_RECV_ACK_COUNT_TOP1_read)(void);
311 
312 	void (*XPU_REG_SEND_ACK_WAIT_TOP_write)(u32 value);
313 	u32  (*XPU_REG_SEND_ACK_WAIT_TOP_read)(void);
314 
315 	void (*XPU_REG_ACK_FC_FILTER_write)(u32 value);
316 	u32  (*XPU_REG_ACK_FC_FILTER_read)(void);
317 
318 	void (*XPU_REG_CTS_TO_RTS_CONFIG_write)(u32 value);
319 	u32  (*XPU_REG_CTS_TO_RTS_CONFIG_read)(void);
320 
321 	void (*XPU_REG_FILTER_FLAG_write)(u32 value);
322 	u32  (*XPU_REG_FILTER_FLAG_read)(void);
323 
324 	void (*XPU_REG_MAC_ADDR_LOW_write)(u32 value);
325 	u32  (*XPU_REG_MAC_ADDR_LOW_read)(void);
326 
327 	void (*XPU_REG_MAC_ADDR_HIGH_write)(u32 value);
328 	u32  (*XPU_REG_MAC_ADDR_HIGH_read)(void);
329 
330 	void (*XPU_REG_BSSID_FILTER_LOW_write)(u32 value);
331 	u32  (*XPU_REG_BSSID_FILTER_LOW_read)(void);
332 
333 	void (*XPU_REG_BSSID_FILTER_HIGH_write)(u32 value);
334 	u32  (*XPU_REG_BSSID_FILTER_HIGH_read)(void);
335 
336 	void (*XPU_REG_BAND_CHANNEL_write)(u32 value);
337 	u32  (*XPU_REG_BAND_CHANNEL_read)(void);
338 
339 	u32  (*XPU_REG_TRX_STATUS_read)(void);
340 	u32  (*XPU_REG_TX_RESULT_read)(void);
341 
342 	u32  (*XPU_REG_TSF_RUNTIME_VAL_LOW_read)(void);
343 	u32  (*XPU_REG_TSF_RUNTIME_VAL_HIGH_read)(void);
344 
345 	void (*XPU_REG_TSF_LOAD_VAL_LOW_write)(u32 value);
346 	void (*XPU_REG_TSF_LOAD_VAL_HIGH_write)(u32 value);
347 	void (*XPU_REG_TSF_LOAD_VAL_write)(u32 high_value, u32 low_value);
348 
349 	u32  (*XPU_REG_FC_DI_read)(void);
350 	u32  (*XPU_REG_ADDR1_LOW_read)(void);
351 	u32  (*XPU_REG_ADDR1_HIGH_read)(void);
352 	u32  (*XPU_REG_ADDR2_LOW_read)(void);
353 	u32  (*XPU_REG_ADDR2_HIGH_read)(void);
354 
355 	void (*XPU_REG_LBT_TH_write)(u32 value);
356 	u32  (*XPU_REG_LBT_TH_read)(void);
357 
358 	void (*XPU_REG_RSSI_DB_CFG_write)(u32 value);
359 	u32  (*XPU_REG_RSSI_DB_CFG_read)(void);
360 
361 	void (*XPU_REG_CSMA_DEBUG_write)(u32 value);
362 	u32  (*XPU_REG_CSMA_DEBUG_read)(void);
363 
364 	void (*XPU_REG_CSMA_CFG_write)(u32 value);
365 	u32  (*XPU_REG_CSMA_CFG_read)(void);
366 
367 	void (*XPU_REG_SLICE_COUNT_TOTAL0_write)(u32 value);
368 	void (*XPU_REG_SLICE_COUNT_START0_write)(u32 value);
369 	void (*XPU_REG_SLICE_COUNT_END0_write)(u32 value);
370 	void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value);
371 	void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value);
372 	void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value);
373 
374 	u32 (*XPU_REG_SLICE_COUNT_TOTAL0_read)(void);
375 	u32 (*XPU_REG_SLICE_COUNT_START0_read)(void);
376 	u32 (*XPU_REG_SLICE_COUNT_END0_read)(void);
377 	u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void);
378 	u32 (*XPU_REG_SLICE_COUNT_START1_read)(void);
379 	u32 (*XPU_REG_SLICE_COUNT_END1_read)(void);
380 
381 	void (*XPU_REG_BB_RF_DELAY_write)(u32 value);
382 	void (*XPU_REG_MAX_NUM_RETRANS_write)(u32 value);
383 
384 	void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr);
385 };
386