xref: /openwifi/driver/hw_def.h (revision 14124d7306727ee7bbae83655e3d9ecacc4c3bee) 
1 // Xianjun jiao. [email protected]; [email protected]
2 
3 const char *sdr_compatible_str = "sdr,sdr";
4 
5 enum openwifi_band {
6 	BAND_900M = 0,
7 	BAND_2_4GHZ,
8 	BAND_3_65GHZ,
9 	BAND_5_0GHZ,
10 	BAND_5_8GHZ,
11 	BAND_5_9GHZ,
12 	BAND_60GHZ,
13 };
14 
15 // ------------------------------------tx interface----------------------------------------
16 const char *tx_intf_compatible_str = "sdr,tx_intf";
17 
18 #define TX_INTF_REG_MULTI_RST_ADDR                 (0*4)
19 #define TX_INTF_REG_MIXER_CFG_ADDR                 (1*4)
20 #define TX_INTF_REG_WIFI_TX_MODE_ADDR              (2*4)
21 #define TX_INTF_REG_IQ_SRC_SEL_ADDR                (3*4)
22 #define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR         (4*4)
23 #define TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR    (5*4)
24 #define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR  (6*4)
25 #define TX_INTF_REG_MISC_SEL_ADDR                  (7*4)
26 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR      (8*4)
27 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR      (9*4)
28 #define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR           (10*4)
29 #define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL1_ADDR     (12*4)
30 #define TX_INTF_REG_BB_GAIN_ADDR                   (13*4)
31 #define TX_INTF_REG_INTERRUPT_SEL_ADDR             (14*4)
32 #define TX_INTF_REG_ANT_SEL_ADDR                   (16*4)
33 #define TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR    (21*4)
34 #define TX_INTF_REG_PKT_INFO_ADDR                  (22*4)
35 #define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR     (24*4)
36 
37 #define TX_INTF_NUM_ANTENNA                        2
38 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL            (64/8)
39 #define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS    3
40 
41 enum tx_intf_mode {
42 	TX_INTF_AXIS_LOOP_BACK = 0,
43 	TX_INTF_BYPASS,
44 	TX_INTF_BW_20MHZ_AT_0MHZ_ANT0,
45 	TX_INTF_BW_20MHZ_AT_0MHZ_ANT1,
46 	TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,
47 	TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,
48 	TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,
49 	TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
50 };
51 
52 const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10};
53 
54 struct tx_intf_driver_api {
55 	u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
56 
57 	u32 (*reg_read)(u32 reg);
58 	void (*reg_write)(u32 reg, u32 value);
59 
60 	u32 (*TX_INTF_REG_MULTI_RST_read)(void);
61 	u32 (*TX_INTF_REG_MIXER_CFG_read)(void);
62 	u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void);
63 	u32 (*TX_INTF_REG_IQ_SRC_SEL_read)(void);
64 	u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void);
65 	u32 (*TX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);
66 	u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void);
67 	u32 (*TX_INTF_REG_MISC_SEL_read)(void);
68 	u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
69 	u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
70 	u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
71 	u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void);
72 	u32 (*TX_INTF_REG_BB_GAIN_read)(void);
73 	u32 (*TX_INTF_REG_ANT_SEL_read)(void);
74 	u32 (*TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read)(void);
75 	u32 (*TX_INTF_REG_PKT_INFO_read)(void);
76 	u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void);
77 
78 	void (*TX_INTF_REG_MULTI_RST_write)(u32 value);
79 	void (*TX_INTF_REG_MIXER_CFG_write)(u32 value);
80 	void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value);
81 	void (*TX_INTF_REG_IQ_SRC_SEL_write)(u32 value);
82 	void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value);
83 	void (*TX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);
84 	void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value);
85 	void (*TX_INTF_REG_MISC_SEL_write)(u32 value);
86 	void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
87 	void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
88 	void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
89 	void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value);
90 	void (*TX_INTF_REG_BB_GAIN_write)(u32 value);
91 	void (*TX_INTF_REG_ANT_SEL_write)(u32 value);
92 	void (*TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write)(u32 value);
93 	void (*TX_INTF_REG_PKT_INFO_write)(u32 value);
94 };
95 
96 // ------------------------------------rx interface----------------------------------------
97 const char *rx_intf_compatible_str = "sdr,rx_intf";
98 
99 #define RX_INTF_REG_MULTI_RST_ADDR                 (0*4)
100 #define RX_INTF_REG_MIXER_CFG_ADDR                 (1*4)
101 #define RX_INTF_REG_INTERRUPT_TEST_ADDR            (2*4)
102 #define RX_INTF_REG_IQ_SRC_SEL_ADDR                (3*4)
103 #define RX_INTF_REG_IQ_CTRL_ADDR                   (4*4)
104 #define RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR    (5*4)
105 #define RX_INTF_REG_START_TRANS_TO_PS_ADDR         (6*4)
106 #define RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR (7*4)
107 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR      (8*4)
108 #define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR      (9*4)
109 #define RX_INTF_REG_CFG_DATA_TO_ANT_ADDR           (10*4)
110 #define RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR         (12*4)
111 #define RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR     (13*4)
112 #define RX_INTF_REG_ANT_SEL_ADDR                   (16*4)
113 
114 #define RX_INTF_NUM_ANTENNA                        2
115 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL            (64/8)
116 #define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS    3
117 
118 enum rx_intf_mode {
119 	RX_INTF_AXIS_LOOP_BACK = 0,
120 	RX_INTF_BYPASS,
121 	RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,
122 	RX_INTF_BW_20MHZ_AT_0MHZ_ANT1,
123 	RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,
124 	RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,
125 	RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,
126 	RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
127 };
128 
129 const int rx_intf_fo_mapping[] = {0,0,0,0,-10,-10,10,10};
130 
131 struct rx_intf_driver_api {
132 	u32 io_start;
133 	u32 base_addr;
134 
135 	u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
136 
137 	u32 (*reg_read)(u32 reg);
138 	void (*reg_write)(u32 reg, u32 value);
139 
140 	u32 (*RX_INTF_REG_MULTI_RST_read)(void);
141 	u32 (*RX_INTF_REG_MIXER_CFG_read)(void);
142 	u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void);
143 	u32 (*RX_INTF_REG_IQ_CTRL_read)(void);
144 	u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);
145 	u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void);
146 	u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void);
147 	u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
148 	u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
149 	u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
150 	u32 (*RX_INTF_REG_ANT_SEL_read)(void);
151 	u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void);
152 	void (*RX_INTF_REG_MULTI_RST_write)(u32 value);
153 	void (*RX_INTF_REG_MIXER_CFG_write)(u32 value);
154 	void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value);
155 	void (*RX_INTF_REG_IQ_CTRL_write)(u32 value);
156 	void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);
157 	void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value);
158 	void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value);
159 	void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
160 	void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
161 	void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
162 	void (*RX_INTF_REG_ANT_SEL_write)(u32 value);
163 	void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value);
164 
165 	void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value);
166 	void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value);
167 	void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value);
168 };
169 
170 // ----------------------------------openofdm rx-------------------------------
171 const char *openofdm_rx_compatible_str = "sdr,openofdm_rx";
172 
173 #define OPENOFDM_RX_REG_MULTI_RST_ADDR     (0*4)
174 #define OPENOFDM_RX_REG_ENABLE_ADDR        (1*4)
175 #define OPENOFDM_RX_REG_POWER_THRES_ADDR   (2*4)
176 #define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR   (3*4)
177 #define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4)
178 
179 enum openofdm_rx_mode {
180 	OPENOFDM_RX_TEST = 0,
181 	OPENOFDM_RX_NORMAL,
182 };
183 
184 struct openofdm_rx_driver_api {
185 	u32 power_thres;
186 	u32 min_plateau;
187 
188 	u32 (*hw_init)(enum openofdm_rx_mode mode);
189 
190 	u32 (*reg_read)(u32 reg);
191 	void (*reg_write)(u32 reg, u32 value);
192 
193 	u32 (*OPENOFDM_RX_REG_STATE_HISTORY_read)(void);
194 
195 	void (*OPENOFDM_RX_REG_MULTI_RST_write)(u32 value);
196 	void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value);
197 	void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value);
198 	void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value);
199 };
200 
201 // ---------------------------------------openofdm tx-------------------------------
202 const char *openofdm_tx_compatible_str = "sdr,openofdm_tx";
203 
204 #define OPENOFDM_TX_REG_MULTI_RST_ADDR                 (0*4)
205 #define OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR          (1*4)
206 #define OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR           (2*4)
207 
208 enum openofdm_tx_mode {
209 	OPENOFDM_TX_TEST = 0,
210 	OPENOFDM_TX_NORMAL,
211 };
212 
213 struct openofdm_tx_driver_api {
214 	u32 (*hw_init)(enum openofdm_tx_mode mode);
215 
216 	u32 (*reg_read)(u32 reg);
217 	void (*reg_write)(u32 reg, u32 value);
218 
219 	void (*OPENOFDM_TX_REG_MULTI_RST_write)(u32 value);
220 	void (*OPENOFDM_TX_REG_INIT_PILOT_STATE_write)(u32 value);
221 	void (*OPENOFDM_TX_REG_INIT_DATA_STATE_write)(u32 value);
222 };
223 
224 // ---------------------------------------xpu low MAC controller-------------------------------
225 
226 // extra filter flag together with enum ieee80211_filter_flags in mac80211.h
227 #define UNICAST_FOR_US     (1<<9)
228 #define BROADCAST_ALL_ONE  (1<<10)
229 #define BROADCAST_ALL_ZERO (1<<11)
230 #define MY_BEACON          (1<<12)
231 #define MONITOR_ALL        (1<<13)
232 
233 const char *xpu_compatible_str = "sdr,xpu";
234 
235 #define XPU_REG_MULTI_RST_ADDR            (0*4)
236 #define XPU_REG_SRC_SEL_ADDR              (1*4)
237 #define XPU_REG_TSF_LOAD_VAL_LOW_ADDR     (2*4)
238 #define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR    (3*4)
239 #define XPU_REG_BAND_CHANNEL_ADDR         (4*4)
240 #define XPU_REG_RSSI_DB_CFG_ADDR          (7*4)
241 #define XPU_REG_LBT_TH_ADDR               (8*4)
242 #define XPU_REG_CSMA_DEBUG_ADDR           (9*4)
243 #define XPU_REG_BB_RF_DELAY_ADDR          (10*4)
244 #define XPU_REG_MAX_NUM_RETRANS_ADDR      (11*4)
245 #define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR  (16*4)
246 #define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR  (17*4)
247 #define XPU_REG_SEND_ACK_WAIT_TOP_ADDR    (18*4)
248 #define XPU_REG_CSMA_CFG_ADDR             (19*4)
249 
250 #define XPU_REG_SLICE_COUNT_TOTAL0_ADDR   (20*4)
251 #define XPU_REG_SLICE_COUNT_START0_ADDR   (21*4)
252 #define XPU_REG_SLICE_COUNT_END0_ADDR     (22*4)
253 #define XPU_REG_SLICE_COUNT_TOTAL1_ADDR   (23*4)
254 #define XPU_REG_SLICE_COUNT_START1_ADDR   (24*4)
255 #define XPU_REG_SLICE_COUNT_END1_ADDR     (25*4)
256 
257 #define XPU_REG_CTS_TO_RTS_CONFIG_ADDR    (26*4)
258 #define XPU_REG_FILTER_FLAG_ADDR          (27*4)
259 #define XPU_REG_BSSID_FILTER_LOW_ADDR     (28*4)
260 #define XPU_REG_BSSID_FILTER_HIGH_ADDR    (29*4)
261 #define XPU_REG_MAC_ADDR_LOW_ADDR         (30*4)
262 #define XPU_REG_MAC_ADDR_HIGH_ADDR        (31*4)
263 
264 #define XPU_REG_FC_DI_ADDR                (34*4)
265 #define XPU_REG_ADDR1_LOW_ADDR            (35*4)
266 #define XPU_REG_ADDR1_HIGH_ADDR           (36*4)
267 #define XPU_REG_ADDR2_LOW_ADDR            (37*4)
268 #define XPU_REG_ADDR2_HIGH_ADDR           (38*4)
269 #define XPU_REG_ADDR3_LOW_ADDR            (39*4)
270 #define XPU_REG_ADDR3_HIGH_ADDR           (40*4)
271 
272 #define XPU_REG_SC_LOW_ADDR               (41*4)
273 #define XPU_REG_ADDR4_HIGH_ADDR           (42*4)
274 #define XPU_REG_ADDR4_LOW_ADDR            (43*4)
275 
276 #define XPU_REG_TRX_STATUS_ADDR           (50*4)
277 #define XPU_REG_TX_RESULT_ADDR            (51*4)
278 
279 #define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR  (58*4)
280 #define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4)
281 
282 #define XPU_REG_RSSI_HALF_DB_ADDR         (60*4)
283 #define XPU_REG_IQ_RSSI_HALF_DB_ADDR      (61*4)
284 
285 enum xpu_mode {
286 	XPU_TEST = 0,
287 	XPU_NORMAL,
288 };
289 
290 struct xpu_driver_api {
291 	u32 (*hw_init)(enum xpu_mode mode);
292 
293 	u32 (*reg_read)(u32 reg);
294 	void (*reg_write)(u32 reg, u32 value);
295 
296 	void (*XPU_REG_MULTI_RST_write)(u32 value);
297 	u32  (*XPU_REG_MULTI_RST_read)(void);
298 
299 	void (*XPU_REG_SRC_SEL_write)(u32 value);
300 	u32  (*XPU_REG_SRC_SEL_read)(void);
301 
302 	void (*XPU_REG_RECV_ACK_COUNT_TOP0_write)(u32 value);
303 	u32  (*XPU_REG_RECV_ACK_COUNT_TOP0_read)(void);
304 
305 	void (*XPU_REG_RECV_ACK_COUNT_TOP1_write)(u32 value);
306 	u32  (*XPU_REG_RECV_ACK_COUNT_TOP1_read)(void);
307 
308 	void (*XPU_REG_SEND_ACK_WAIT_TOP_write)(u32 value);
309 	u32  (*XPU_REG_SEND_ACK_WAIT_TOP_read)(void);
310 
311 	void (*XPU_REG_ACK_FC_FILTER_write)(u32 value);
312 	u32  (*XPU_REG_ACK_FC_FILTER_read)(void);
313 
314 	void (*XPU_REG_CTS_TO_RTS_CONFIG_write)(u32 value);
315 	u32  (*XPU_REG_CTS_TO_RTS_CONFIG_read)(void);
316 
317 	void (*XPU_REG_FILTER_FLAG_write)(u32 value);
318 	u32  (*XPU_REG_FILTER_FLAG_read)(void);
319 
320 	void (*XPU_REG_MAC_ADDR_LOW_write)(u32 value);
321 	u32  (*XPU_REG_MAC_ADDR_LOW_read)(void);
322 
323 	void (*XPU_REG_MAC_ADDR_HIGH_write)(u32 value);
324 	u32  (*XPU_REG_MAC_ADDR_HIGH_read)(void);
325 
326 	void (*XPU_REG_BSSID_FILTER_LOW_write)(u32 value);
327 	u32  (*XPU_REG_BSSID_FILTER_LOW_read)(void);
328 
329 	void (*XPU_REG_BSSID_FILTER_HIGH_write)(u32 value);
330 	u32  (*XPU_REG_BSSID_FILTER_HIGH_read)(void);
331 
332 	void (*XPU_REG_BAND_CHANNEL_write)(u32 value);
333 	u32  (*XPU_REG_BAND_CHANNEL_read)(void);
334 
335 	u32  (*XPU_REG_TRX_STATUS_read)(void);
336 	u32  (*XPU_REG_TX_RESULT_read)(void);
337 
338 	u32  (*XPU_REG_TSF_RUNTIME_VAL_LOW_read)(void);
339 	u32  (*XPU_REG_TSF_RUNTIME_VAL_HIGH_read)(void);
340 
341 	void (*XPU_REG_TSF_LOAD_VAL_LOW_write)(u32 value);
342 	void (*XPU_REG_TSF_LOAD_VAL_HIGH_write)(u32 value);
343 	void (*XPU_REG_TSF_LOAD_VAL_write)(u32 high_value, u32 low_value);
344 
345 	u32  (*XPU_REG_FC_DI_read)(void);
346 	u32  (*XPU_REG_ADDR1_LOW_read)(void);
347 	u32  (*XPU_REG_ADDR1_HIGH_read)(void);
348 	u32  (*XPU_REG_ADDR2_LOW_read)(void);
349 	u32  (*XPU_REG_ADDR2_HIGH_read)(void);
350 
351 	void (*XPU_REG_LBT_TH_write)(u32 value);
352 	u32  (*XPU_REG_LBT_TH_read)(void);
353 
354 	void (*XPU_REG_RSSI_DB_CFG_write)(u32 value);
355 	u32  (*XPU_REG_RSSI_DB_CFG_read)(void);
356 
357 	void (*XPU_REG_CSMA_DEBUG_write)(u32 value);
358 	u32  (*XPU_REG_CSMA_DEBUG_read)(void);
359 
360 	void (*XPU_REG_CSMA_CFG_write)(u32 value);
361 	u32  (*XPU_REG_CSMA_CFG_read)(void);
362 
363 	void (*XPU_REG_SLICE_COUNT_TOTAL0_write)(u32 value);
364 	void (*XPU_REG_SLICE_COUNT_START0_write)(u32 value);
365 	void (*XPU_REG_SLICE_COUNT_END0_write)(u32 value);
366 	void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value);
367 	void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value);
368 	void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value);
369 
370 	u32 (*XPU_REG_SLICE_COUNT_TOTAL0_read)(void);
371 	u32 (*XPU_REG_SLICE_COUNT_START0_read)(void);
372 	u32 (*XPU_REG_SLICE_COUNT_END0_read)(void);
373 	u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void);
374 	u32 (*XPU_REG_SLICE_COUNT_START1_read)(void);
375 	u32 (*XPU_REG_SLICE_COUNT_END1_read)(void);
376 
377 	void (*XPU_REG_BB_RF_DELAY_write)(u32 value);
378 	void (*XPU_REG_MAX_NUM_RETRANS_write)(u32 value);
379 
380 	void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr);
381 };
382