1 /* 2 * File : sep6200.h 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Change Logs: 21 * Date Author Notes 22 * 2013-7-17 Peng Fan sep6200 implementation 23 */ 24 25 #ifndef __SEP6200_H 26 #define __SEP6200_H 27 28 #include <rtthread.h> 29 30 /*Core definations*/ 31 #define PRIVMODE 0x13 32 #define Mode_USR 0x10 33 #define Mode_REAL 0x11 34 #define Mode_IRQ 0x12 35 #define Mode_PRIV 0x13 36 #define Mode_TRAP 0x17 37 #define Mode_EXT 0x1B 38 #define Mode_SUSR 0x1F 39 40 /* 41 * Address 42 */ 43 44 #define SEP6200_VIC_BASE 0xb0000000 45 #define SEP6200_PMU_BASE 0xb0001000 46 #define SEP6200_RTC_BASE 0xb0002000 47 #define SEP6200_TIMER_BASE 0xb0003000 48 #define SEP6200_PWM_BASE 0xb0004000 49 #define SEP6200_GPIO_BASE 0xb0006000 50 #define SEP6200_TOUCH_ADC 0xb0007000 51 #define SEP6200_SYSCTL_BASE 0xb0008000 52 #define SEP6200_UART0_BASE 0xb1000000 53 #define SEP6200_UART1_BASE 0xb1001000 54 #define SEP6200_UART2_BASE 0xb1002000 55 #define SEP6200_UART3_BASE 0xb1003000 56 #define SEP6200_SSI1_BASE 0xb1004000 57 #define SEP6200_SSI2_BASE 0xb1005000 58 #define SEP6200_SSI3_BASE 0xb1006000 59 #define SEP6200_I2C_BASE 0xb1007000 60 #define SEP6200_I2S_BASE 0xb1008000 61 #define SEP6200_USB_BASE 0xb1010000 62 #define SEP6200_DMAC2_BASE 0xb1011000 63 #define SEP6200_ESRAM_BASE 0xb2000000 64 #define SEP6200_NORREG_BASE0xb2020000 65 #define SEP6200_SDIO1_BASE 0xb2022000 66 #define SEP6200_SDIO2_BASE 0xb2023000 67 #define SEP6200_LCDC_BASE 0xb2025000 68 #define SEP6200_VPU_BASE 0xb2026000 69 #define SEP6200_DMAC1_BASE 0xb2027000 70 #define SEP6200_DDR2_REG 0xb3000000 71 #define SEP6200_DDR_MEM 0x40000000 72 73 #define SEP6200_UART0_DLBL (SEP6200_UART0_BASE+0x00) 74 #define SEP6200_UART0_RXFIFO (SEP6200_UART0_BASE+0x00) 75 #define SEP6200_UART0_TXFIFO (SEP6200_UART0_BASE+0x00) 76 #define SEP6200_UART0_DLBH (SEP6200_UART0_BASE+0x04) 77 #define SEP6200_UART0_IER (SEP6200_UART0_BASE+0x04) 78 #define SEP6200_UART0_IIR (SEP6200_UART0_BASE+0x08) 79 #define SEP6200_UART0_FCR (SEP6200_UART0_BASE+0x08) 80 #define SEP6200_UART0_LCR (SEP6200_UART0_BASE+0x0c) 81 #define SEP6200_UART0_MCR (SEP6200_UART0_BASE+0x10) 82 #define SEP6200_UART0_LSR (SEP6200_UART0_BASE+0x14) 83 #define SEP6200_UART0_MSR (SEP6200_UART0_BASE+0x18) 84 85 86 #define SEP6200_TIMER_T1LCR (SEP6200_TIMER_BASE + 0X000) 87 #define SEP6200_TIMER_T1CCR (SEP6200_TIMER_BASE + 0X004) 88 #define SEP6200_TIMER_T1CR (SEP6200_TIMER_BASE + 0X008) 89 #define SEP6200_TIMER_T1ISCR (SEP6200_TIMER_BASE + 0X00C) 90 #define SEP6200_TIMER_T1IMSR (SEP6200_TIMER_BASE + 0X010) 91 #define SEP6200_TIMER_T2LCR (SEP6200_TIMER_BASE + 0X020) 92 #define SEP6200_TIMER_T2CCR (SEP6200_TIMER_BASE + 0X024) 93 #define SEP6200_TIMER_T2CR (SEP6200_TIMER_BASE + 0X028) 94 #define SEP6200_TIMER_T2ISCR (SEP6200_TIMER_BASE + 0X02C) 95 #define SEP6200_TIMER_T2IMSR (SEP6200_TIMER_BASE + 0X030) 96 #define SEP6200_TIMER_T3LCR (SEP6200_TIMER_BASE + 0X040) 97 #define SEP6200_TIMER_T3CCR (SEP6200_TIMER_BASE + 0X044) 98 #define SEP6200_TIMER_T3CR (SEP6200_TIMER_BASE + 0X048) 99 #define SEP6200_TIMER_T3ISCR (SEP6200_TIMER_BASE + 0X04C) 100 #define SEP6200_TIMER_T3IMSR (SEP6200_TIMER_BASE + 0X050) 101 #define SEP6200_TIMER_T3CAPR (SEP6200_TIMER_BASE + 0X054) 102 #define SEP6200_TIMER_T4LCR (SEP6200_TIMER_BASE + 0X060) 103 #define SEP6200_TIMER_T4CCR (SEP6200_TIMER_BASE + 0X064) 104 #define SEP6200_TIMER_T4CR (SEP6200_TIMER_BASE + 0X068) 105 #define SEP6200_TIMER_T4ISCR (SEP6200_TIMER_BASE + 0X06C) 106 #define SEP6200_TIMER_T4IMSR (SEP6200_TIMER_BASE + 0X070) 107 #define SEP6200_TIMER_T4CAPR (SEP6200_TIMER_BASE + 0X074) 108 #define SEP6200_TIMER_T5LCR (SEP6200_TIMER_BASE + 0X080) 109 #define SEP6200_TIMER_T5CCR (SEP6200_TIMER_BASE + 0X084) 110 #define SEP6200_TIMER_T5CR (SEP6200_TIMER_BASE + 0X088) 111 #define SEP6200_TIMER_T5ISCR (SEP6200_TIMER_BASE + 0X08C) 112 #define SEP6200_TIMER_T5IMSR (SEP6200_TIMER_BASE + 0X090) 113 #define SEP6200_TIMER_T5CAPR (SEP6200_TIMER_BASE + 0X094) 114 #define SEP6200_TIMER_T6LCR (SEP6200_TIMER_BASE + 0X0A0) 115 #define SEP6200_TIMER_T6CCR (SEP6200_TIMER_BASE + 0X0A4) 116 #define SEP6200_TIMER_T6CR (SEP6200_TIMER_BASE + 0X0A8) 117 #define SEP6200_TIMER_T6ISCR (SEP6200_TIMER_BASE + 0X0AC) 118 #define SEP6200_TIMER_T6IMSR (SEP6200_TIMER_BASE + 0X0B0) 119 #define SEP6200_TIMER_T6CAPR (SEP6200_TIMER_BASE + 0X0B4) 120 #define SEP6200_TIMER_T7LCR (SEP6200_TIMER_BASE + 0X0C0) 121 #define SEP6200_TIMER_T7CCR (SEP6200_TIMER_BASE + 0X0C4) 122 #define SEP6200_TIMER_T7CR (SEP6200_TIMER_BASE + 0X0C8) 123 #define SEP6200_TIMER_T7ISCR (SEP6200_TIMER_BASE + 0X0CC) 124 #define SEP6200_TIMER_T7IMSR (SEP6200_TIMER_BASE + 0X0D0) 125 #define SEP6200_TIMER_T8LCR (SEP6200_TIMER_BASE + 0X0E0) 126 #define SEP6200_TIMER_T8CCR (SEP6200_TIMER_BASE + 0X0E4) 127 #define SEP6200_TIMER_T8CR (SEP6200_TIMER_BASE + 0X0E8) 128 #define SEP6200_TIMER_T8ISCR (SEP6200_TIMER_BASE + 0X0EC) 129 #define SEP6200_TIMER_T8IMSR (SEP6200_TIMER_BASE + 0X0F0) 130 #define SEP6200_TIMER_T9LCR (SEP6200_TIMER_BASE + 0X100) 131 #define SEP6200_TIMER_T9CCR (SEP6200_TIMER_BASE + 0X104) 132 #define SEP6200_TIMER_T9CR (SEP6200_TIMER_BASE + 0X108) 133 #define SEP6200_TIMER_T9ISCR (SEP6200_TIMER_BASE + 0X10C) 134 #define SEP6200_TIMER_T9IMSR (SEP6200_TIMER_BASE + 0X110) 135 #define SEP6200_TIMER_T10LCR (SEP6200_TIMER_BASE + 0X120) 136 #define SEP6200_TIMER_T10CCR (SEP6200_TIMER_BASE + 0X124) 137 #define SEP6200_TIMER_T10CR (SEP6200_TIMER_BASE + 0X128) 138 #define SEP6200_TIMER_T10ISCR (SEP6200_TIMER_BASE + 0X12C) 139 #define SEP6200_TIMER_T10IMSR (SEP6200_TIMER_BASE + 0X130) 140 #define SEP6200_TIMER_TIMSR (SEP6200_TIMER_BASE + 0X140) 141 #define SEP6200_TIMER_TISCR (SEP6200_TIMER_BASE + 0X144) 142 #define SEP6200_TIMER_TISR (SEP6200_TIMER_BASE + 0X148) 143 144 #define SEP6200_VIC_INT_SLT_L (SEP6200_VIC_BASE + 0x000) 145 #define SEP6200_VIC_INT_SLT_H (SEP6200_VIC_BASE + 0x004) 146 #define SEP6200_VIC_INT_EN_L (SEP6200_VIC_BASE + 0x008) 147 #define SEP6200_VIC_INT_EN_H (SEP6200_VIC_BASE + 0x00C) 148 #define SEP6200_VIC_INT_EN_CLR_L (SEP6200_VIC_BASE + 0x010) 149 #define SEP6200_VIC_INT_EN_CLR_H (SEP6200_VIC_BASE + 0x014) 150 #define SEP6200_VIC_SFT_INT_L (SEP6200_VIC_BASE + 0x018) 151 #define SEP6200_VIC_SFT_INT_H (SEP6200_VIC_BASE + 0x01C) 152 #define SEP6200_VIC_SFT_INT_CLR_L (SEP6200_VIC_BASE + 0x020) 153 #define SEP6200_VIC_SFT_INT_CLR_H (SEP6200_VIC_BASE + 0x024) 154 #define SEP6200_VIC_INT_MSK_ALL (SEP6200_VIC_BASE + 0x028) 155 #define SEP6200_VIC_RAW_INT_SRC_L (SEP6200_VIC_BASE + 0x030) 156 #define SEP6200_VIC_RAW_INT_SRC_H (SEP6200_VIC_BASE + 0x034) 157 #define SEP6200_VIC_RAW_IRQ_STS_L (SEP6200_VIC_BASE + 0x038) 158 #define SEP6200_VIC_RAW_IRQ_STS_H (SEP6200_VIC_BASE + 0x03C) 159 #define SEP6200_VIC_RAW_FIQ_STS_L (SEP6200_VIC_BASE + 0x040) 160 #define SEP6200_VIC_RAW_FIQ_STS_H (SEP6200_VIC_BASE + 0x044) 161 #define SEP6200_VIC_MSK_IRQ_STS_L (SEP6200_VIC_BASE + 0x048) 162 #define SEP6200_VIC_MSK_IRQ_STS_H (SEP6200_VIC_BASE + 0x04C) 163 #define SEP6200_VIC_MSK_FIQ_STS_L (SEP6200_VIC_BASE + 0x050) 164 #define SEP6200_VIC_MSK_FIQ_STS_H (SEP6200_VIC_BASE + 0x054) 165 #define SEP6200_VIC_IRQ_PENDING_L (SEP6200_VIC_BASE + 0x058) 166 #define SEP6200_VIC_IRQ_PENDING_H (SEP6200_VIC_BASE + 0x05C) 167 #define SEP6200_VIC_FIQ_PENDING_L (SEP6200_VIC_BASE + 0x060) 168 #define SEP6200_VIC_FIQ_PENDING_H (SEP6200_VIC_BASE + 0x064) 169 #define SEP6200_VIC_IRQ_VECTOR_BASE (SEP6200_VIC_BASE + 0x070) 170 #define SEP6200_VIC_FIQ_VECTOR_BASE (SEP6200_VIC_BASE + 0x074) 171 #define SEP6200_VIC_IRQ_VECTOR_NUM (SEP6200_VIC_BASE + 0x078) 172 #define SEP6200_VIC_FIQ_VECTOR_NUM (SEP6200_VIC_BASE + 0x07C) 173 #define SEP6200_VIC_IRQ_VECTOR_ADDR (SEP6200_VIC_BASE + 0x080) 174 #define SEP6200_VIC_FIQ_VECTOR_ADDR (SEP6200_VIC_BASE + 0x084) 175 #define SEP6200_VIC_PROIRTY_MASK (SEP6200_VIC_BASE + 0x090) 176 #define SEP6200_VIC_VECTOR_PROIRTY00 (SEP6200_VIC_BASE + 0x100) 177 #define SEP6200_VIC_VECTOR_PROIRTY01 (SEP6200_VIC_BASE + 0x104) 178 #define SEP6200_VIC_VECTOR_PROIRTY02 (SEP6200_VIC_BASE + 0x108) 179 #define SEP6200_VIC_VECTOR_PROIRTY03 (SEP6200_VIC_BASE + 0x10C) 180 #define SEP6200_VIC_VECTOR_PROIRTY04 (SEP6200_VIC_BASE + 0x110) 181 #define SEP6200_VIC_VECTOR_PROIRTY05 (SEP6200_VIC_BASE + 0x114) 182 #define SEP6200_VIC_VECTOR_PROIRTY06 (SEP6200_VIC_BASE + 0x118) 183 #define SEP6200_VIC_VECTOR_PROIRTY07 (SEP6200_VIC_BASE + 0x11C) 184 #define SEP6200_VIC_VECTOR_PROIRTY08 (SEP6200_VIC_BASE + 0x120) 185 #define SEP6200_VIC_VECTOR_PROIRTY09 (SEP6200_VIC_BASE + 0x124) 186 #define SEP6200_VIC_VECTOR_PROIRTY10 (SEP6200_VIC_BASE + 0x128) 187 #define SEP6200_VIC_VECTOR_PROIRTY11 (SEP6200_VIC_BASE + 0x12C) 188 #define SEP6200_VIC_VECTOR_PROIRTY12 (SEP6200_VIC_BASE + 0x130) 189 #define SEP6200_VIC_VECTOR_PROIRTY13 (SEP6200_VIC_BASE + 0x134) 190 #define SEP6200_VIC_VECTOR_PROIRTY14 (SEP6200_VIC_BASE + 0x138) 191 #define SEP6200_VIC_VECTOR_PROIRTY15 (SEP6200_VIC_BASE + 0x13C) 192 #define SEP6200_VIC_VECTOR_PROIRTY16 (SEP6200_VIC_BASE + 0x140) 193 #define SEP6200_VIC_VECTOR_PROIRTY17 (SEP6200_VIC_BASE + 0x144) 194 #define SEP6200_VIC_VECTOR_PROIRTY18 (SEP6200_VIC_BASE + 0x148) 195 #define SEP6200_VIC_VECTOR_PROIRTY19 (SEP6200_VIC_BASE + 0x14C) 196 #define SEP6200_VIC_VECTOR_PROIRTY20 (SEP6200_VIC_BASE + 0x150) 197 #define SEP6200_VIC_VECTOR_PROIRTY21 (SEP6200_VIC_BASE + 0x154) 198 #define SEP6200_VIC_VECTOR_PROIRTY22 (SEP6200_VIC_BASE + 0x158) 199 #define SEP6200_VIC_VECTOR_PROIRTY23 (SEP6200_VIC_BASE + 0x15C) 200 #define SEP6200_VIC_VECTOR_PROIRTY24 (SEP6200_VIC_BASE + 0x160) 201 #define SEP6200_VIC_VECTOR_PROIRTY25 (SEP6200_VIC_BASE + 0x164) 202 #define SEP6200_VIC_VECTOR_PROIRTY26 (SEP6200_VIC_BASE + 0x168) 203 #define SEP6200_VIC_VECTOR_PROIRTY27 (SEP6200_VIC_BASE + 0x16C) 204 #define SEP6200_VIC_VECTOR_PROIRTY28 (SEP6200_VIC_BASE + 0x170) 205 #define SEP6200_VIC_VECTOR_PROIRTY29 (SEP6200_VIC_BASE + 0x174) 206 #define SEP6200_VIC_VECTOR_PROIRTY30 (SEP6200_VIC_BASE + 0x178) 207 #define SEP6200_VIC_VECTOR_PROIRTY31 (SEP6200_VIC_BASE + 0x17C) 208 #define SEP6200_VIC_VECTOR_PROIRTY32 (SEP6200_VIC_BASE + 0x180) 209 #define SEP6200_VIC_VECTOR_PROIRTY33 (SEP6200_VIC_BASE + 0x184) 210 #define SEP6200_VIC_VECTOR_PROIRTY34 (SEP6200_VIC_BASE + 0x188) 211 #define SEP6200_VIC_VECTOR_PROIRTY35 (SEP6200_VIC_BASE + 0x18C) 212 #define SEP6200_VIC_VECTOR_PROIRTY36 (SEP6200_VIC_BASE + 0x190) 213 #define SEP6200_VIC_VECTOR_PROIRTY37 (SEP6200_VIC_BASE + 0x194) 214 #define SEP6200_VIC_VECTOR_PROIRTY38 (SEP6200_VIC_BASE + 0x198) 215 #define SEP6200_VIC_VECTOR_PROIRTY39 (SEP6200_VIC_BASE + 0x19C) 216 #define SEP6200_VIC_VECTOR_PROIRTY40 (SEP6200_VIC_BASE + 0x1A0) 217 #define SEP6200_VIC_VECTOR_PROIRTY41 (SEP6200_VIC_BASE + 0x1A4) 218 #define SEP6200_VIC_VECTOR_PROIRTY42 (SEP6200_VIC_BASE + 0x1A8) 219 #define SEP6200_VIC_VECTOR_PROIRTY43 (SEP6200_VIC_BASE + 0x1AC) 220 #define SEP6200_VIC_VECTOR_PROIRTY44 (SEP6200_VIC_BASE + 0x1B0) 221 #define SEP6200_VIC_VECTOR_PROIRTY45 (SEP6200_VIC_BASE + 0x1B4) 222 #define SEP6200_VIC_VECTOR_PROIRTY46 (SEP6200_VIC_BASE + 0x1B8) 223 #define SEP6200_VIC_VECTOR_PROIRTY47 (SEP6200_VIC_BASE + 0x1BC) 224 #define SEP6200_VIC_VECTOR_PROIRTY48 (SEP6200_VIC_BASE + 0x1C0) 225 #define SEP6200_VIC_VECTOR_PROIRTY49 (SEP6200_VIC_BASE + 0x1C4) 226 #define SEP6200_VIC_VECTOR_PROIRTY50 (SEP6200_VIC_BASE + 0x1C8) 227 #define SEP6200_VIC_VECTOR_PROIRTY51 (SEP6200_VIC_BASE + 0x1CC) 228 #define SEP6200_VIC_VECTOR_PROIRTY52 (SEP6200_VIC_BASE + 0x1D0) 229 #define SEP6200_VIC_VECTOR_PROIRTY53 (SEP6200_VIC_BASE + 0x1D4) 230 #define SEP6200_VIC_VECTOR_PROIRTY54 (SEP6200_VIC_BASE + 0x1D8) 231 #define SEP6200_VIC_VECTOR_PROIRTY55 (SEP6200_VIC_BASE + 0x1DC) 232 #define SEP6200_VIC_VECTOR_PROIRTY56 (SEP6200_VIC_BASE + 0x1E0) 233 #define SEP6200_VIC_VECTOR_PROIRTY57 (SEP6200_VIC_BASE + 0x1E4) 234 #define SEP6200_VIC_VECTOR_PROIRTY58 (SEP6200_VIC_BASE + 0x1E8) 235 #define SEP6200_VIC_VECTOR_PROIRTY59 (SEP6200_VIC_BASE + 0x1EC) 236 #define SEP6200_VIC_VECTOR_PROIRTY60 (SEP6200_VIC_BASE + 0x1F0) 237 #define SEP6200_VIC_VECTOR_PROIRTY61 (SEP6200_VIC_BASE + 0x1F4) 238 #define SEP6200_VIC_VECTOR_PROIRTY62 (SEP6200_VIC_BASE + 0x1F8) 239 #define SEP6200_VIC_VECTOR_PROIRTY63 (SEP6200_VIC_BASE + 0x1FC) 240 241 #define SEP6200_PMU_PLL_SET (SEP6200_PMU_BASE + 0x000) 242 #define SEP6200_PMU_APLL_CFG (SEP6200_PMU_BASE + 0x004) 243 #define SEP6200_PMU_MPLL_GFG (SEP6200_PMU_BASE + 0x008) 244 #define SEP6200_PMU_DPLL_CFG (SEP6200_PMU_BASE + 0x00C) 245 #define SEP6200_PMU_PMDR (SEP6200_PMU_BASE + 0x010) 246 #define SEP6200_PMU_CLK_GT_CFG1 (SEP6200_PMU_BASE + 0x014) 247 #define SEP6200_PMU_CLK_GT_CFG2 (SEP6200_PMU_BASE + 0x018) 248 #define SEP6200_PMU_PWR_GT_CFG (SEP6200_PMU_BASE + 0x01C) 249 #define SEP6200_PMU_AHB_CLK_CFG (SEP6200_PMU_BASE + 0x020) 250 #define SEP6200_PMU_ARM_CLK_CFG (SEP6200_PMU_BASE + 0x024) 251 #define SEP6200_PMU_DDR_CLK_CFG (SEP6200_PMU_BASE + 0x028) 252 #define SEP6200_PMU_PIX_CLK_CFG (SEP6200_PMU_BASE + 0x02C) 253 #define SEP6200_PMU_GPU_CLK2X_CFG (SEP6200_PMU_BASE + 0x030) 254 #define SEP6200_PMU_DIV_SET (SEP6200_PMU_BASE + 0x034) 255 #define SEP6200_PMU_CRYSTAL_CFG (SEP6200_PMU_BASE + 0x038) 256 #define SEP6200_PMU_MSK_WAKEUP (SEP6200_PMU_BASE + 0x03C) 257 #define SEP6200_PMU_RTCR (SEP6200_PMU_BASE + 0x040) 258 #define SEP6200_PMU_CLR_WAKEUP (SEP6200_PMU_BASE + 0x044) 259 #define SEP6200_PMU_WAKEUP_TIME (SEP6200_PMU_BASE + 0x048) 260 #define SEP6200_PMU_SLEEP_FLAG (SEP6200_PMU_BASE + 0x04C) 261 #define SEP6200_PMU_WAIT_PWR_SWITCH (SEP6200_PMU_BASE + 0x050) 262 #define SEP6200_PMU_PWR_STATE (SEP6200_PMU_BASE + 0x054) 263 #define SEP6200_PMU_INT_POL_SEL (SEP6200_PMU_BASE + 0x058) 264 #define SEP6200_PMU_PLLLD (SEP6200_PMU_BASE + 0x05C) 265 #define SEP6200_PMU_IC_ENABLE (SEP6200_PMU_BASE + 0x060) 266 #define SEP6200_PMU_IC_TAR (SEP6200_PMU_BASE + 0x064) 267 #define SEP6200_PMU_IC_SCL_LCNT (SEP6200_PMU_BASE + 0x068) 268 #define SEP6200_PMU_IC_SCL_HCNT (SEP6200_PMU_BASE + 0x06C) 269 #define SEP6200_PMU_IC_DATA_CMD (SEP6200_PMU_BASE + 0x070) 270 #define SEP6200_PMU_IC_STATE (SEP6200_PMU_BASE + 0x074) 271 #define SEP6200_PMU_IC_SET (SEP6200_PMU_BASE + 0x078) 272 #define SEP6200_PMU_HA_PWR_OFF_DAT (SEP6200_PMU_BASE + 0x07C) 273 #define SEP6200_PMU_HA_PWR_ON_DAT (SEP6200_PMU_BASE + 0x080) 274 #define SEP6200_PMU_HA_PWR_OFF_DAT_CNT (SEP6200_PMU_BASE + 0x084) 275 #define SEP6200_PMU_HA_PWR_ON_DAT_CNT (SEP6200_PMU_BASE + 0x088) 276 #define SEP6200_PMU_PWR_OFF_TIME (SEP6200_PMU_BASE + 0x08C) 277 #define SEP6200_PMU_PWR_ON_TIME (SEP6200_PMU_BASE + 0x090) 278 #define SEP6200_PMU_PWR_ON_POL_SEL (SEP6200_PMU_BASE + 0x094) 279 #define SEP6200_PMU_RETURN_ADDR (SEP6200_PMU_BASE + 0x098) 280 #define SEP6200_PMU_INT (SEP6200_PMU_BASE + 0x09C) 281 282 /* define the interrupt source number */ 283 #define INTSRC_RESERVE2 63 284 #define INTSRC_RESERVE1 62 285 #define INTSRC_LCDC 61 286 #define INTSRC_GPU 60 287 #define INTSRC_VPU 59 288 #define INTSRC_TIMER3 58 289 #define INTSRC_TIMER2 57 290 #define INTSRC_TIMER1 56 291 #define INTSRC_NAND 55 292 #define INTSRC_I2S 54 293 #define INTSRC_I2C3 53 294 #define INTSRC_I2C2 52 295 #define INTSRC_I2C1 51 296 #define INTSRC_SSI3 50 297 #define INTSRC_SSI2 49 298 #define INTSRC_SSI1 48 299 #define INTSRC_SDIO2 47 300 #define INTSRC_SDIO1 46 301 #define INTSRC_UART3 45 302 #define INTSRC_UART2 44 303 #define INTSRC_UART1 43 304 #define INTSRC_UART0 42 305 #define INTSRC_PWM 41 306 #define INTSRC_USB 40 307 #define INTSRC_USBDMA 39 308 #define INTSRC_DMAC2 38 309 #define INTSRC_DMAC1 37 310 #define INTSRC_PMUIRQ_A11 36 311 #define INTSRC_DMAIRQ_A11 35 312 #define INTSRC_GPS 34 313 #define INTSRC_RTC 33 314 #define INTSRC_RESERVED16 32 315 #define INTSRC_PORTE12 31 316 #define INTSRC_PORTE11 30 317 #define INTSRC_PORTE10 29 318 #define INTSRC_PORTE9 28 319 #define INTSRC_PORTE5 27 320 #define INTSRC_PORTE4 26 321 #define INTSRC_PORTD9 25 322 #define INTSRC_PORTD8 24 323 #define INTSRC_PORTD3 23 324 #define INTSRC_PORTD2 22 325 #define INTSRC_PORTD1 21 326 #define INTSRC_PORTD0 20 327 #define INTSRC_PORTC3 19 328 #define INTSRC_PORTC2 18 329 #define INTSRC_PORTC1 17 330 #define INTSRC_PORTC0 16 331 #define INTSRC_EXT15 15 332 #define INTSRC_EXT14 14 333 #define INTSRC_EXT13 13 334 #define INTSRC_EXT12 12 335 #define INTSRC_EXT11 11 336 #define INTSRC_EXT10 10 337 #define INTSRC_EXT9 9 338 #define INTSRC_EXT8 8 339 #define INTSRC_EXT7 7 340 #define INTSRC_EXT6 6 341 #define INTSRC_EXT5 5 342 #define INTSRC_EXT4 4 343 #define INTSRC_AO_EXT3 3 344 #define INTSRC_AO_EXT2 2 345 #define INTSRC_AO_EXT1 1 346 #define INTSRC_AO_EXT0 0 347 348 349 typedef char S8; /* signed 8-bit integer */ 350 typedef short S16; /* signed 16-bit integer */ 351 typedef long S32; /* signed 32-bit integer */ 352 typedef unsigned char U8; /* unsigned 8-bit integer */ 353 typedef unsigned short U16; /* unsigned 16-bit integer */ 354 typedef unsigned long U32; /* unsigned 32-bit integer */ 355 356 typedef volatile U32 * RP; 357 typedef volatile U16 * RP16; 358 typedef volatile U8 * RP8; 359 360 typedef void *VP; /* pointer to an unpredictable data type */ 361 typedef void (*FP)(); /* program start address */ 362 363 #ifndef _BOOL_TYPE_ 364 #define _BOOL_TYPE_ 365 typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ 366 #endif 367 368 typedef int ER; /* Error code. A signed integer. */ 369 370 /** 371 * IO definitions 372 * 373 * define access restrictions to peripheral registers 374 */ 375 376 #define __I volatile const /*!< defines 'read only' permissions */ 377 #define __O volatile /*!< defines 'write only' permissions */ 378 #define __IO volatile /*!< defines 'read / write' permissions */ 379 #define __iomem volatile 380 381 382 /*Macros for debug*/ 383 384 #define EOUT(fmt,...) \ 385 do \ 386 { \ 387 rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ 388 rt_kprintf(fmt,##__VA_ARGS__); \ 389 }while(0) 390 391 #define RT_DEBUG 392 #ifdef RT_DEBUG 393 #define DBOUT(fmt,...) \ 394 do \ 395 { \ 396 rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ 397 rt_kprintf(fmt,##__VA_ARGS__); \ 398 }while(0) 399 #else 400 #define DBOUT(fmt,...) \ 401 do{}while(0) 402 #endif 403 404 #ifdef RT_DEBUG 405 #define ASSERT(arg) \ 406 if((arg) == 0) \ 407 { \ 408 while(1) \ 409 { \ 410 rt_kprintf("have a assert failure\n"); \ 411 } \ 412 } 413 #else 414 #define ASSERT(arg) \ 415 do \ 416 { \ 417 }while(0) 418 #endif 419 420 421 #define write_reg(reg,value) \ 422 do \ 423 { \ 424 *(RP)(reg) = value; \ 425 }while(0) 426 427 #define read_reg(reg) (*(RP)reg) 428 429 430 struct rt_hw_register 431 { 432 rt_uint32_t r0; 433 rt_uint32_t r1; 434 rt_uint32_t r2; 435 rt_uint32_t r3; 436 rt_uint32_t r4; 437 rt_uint32_t r5; 438 rt_uint32_t r6; 439 rt_uint32_t r7; 440 rt_uint32_t r8; 441 rt_uint32_t r9; 442 rt_uint32_t r10; 443 rt_uint32_t r11; 444 rt_uint32_t r12; 445 rt_uint32_t r13; 446 rt_uint32_t r14; 447 rt_uint32_t r15; 448 rt_uint32_t r16; 449 rt_uint32_t r17; 450 rt_uint32_t r18; 451 rt_uint32_t r19; 452 rt_uint32_t r20; 453 rt_uint32_t r21; 454 rt_uint32_t r22; 455 rt_uint32_t r23; 456 rt_uint32_t r24; 457 rt_uint32_t sb; 458 rt_uint32_t sl; 459 rt_uint32_t fp; 460 rt_uint32_t ip; 461 rt_uint32_t sp; 462 rt_uint32_t lr; 463 rt_uint32_t pc; 464 rt_uint32_t asr; 465 rt_uint32_t bsr; 466 rt_uint32_t ORIG_r0; 467 }; 468 469 /*@}*/ 470 471 #endif 472