1 /*----------------------------------------------------------------------------+
2 |
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
9 |
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
13 |
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
17 |
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
21
22 #ifndef __PPC4XX_H__
23 #define __PPC4XX_H__
24
25 /*
26 * Configure which SDRAM/DDR/DDR2 controller is equipped
27 */
28 #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
29
30 #include <asm/ppc405.h>
31 #include <asm/ppc4xx-uic.h>
32
33 /*
34 * Macro for generating register field mnemonics
35 */
36 #define PPC_REG_BITS 32
37 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
38
39 /*
40 * Elide casts when assembling register mnemonics
41 */
42 #ifndef __ASSEMBLY__
43 #define static_cast(type, val) (type)(val)
44 #else
45 #define static_cast(type, val) (val)
46 #endif
47
48 /*
49 * Common stuff for 4xx (405 and 440)
50 */
51
52 #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
53 #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
54
55 #define RESET_VECTOR 0xfffffffc
56 #define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
57 line aligned data. */
58
59 #define CPR0_DCR_BASE 0x0C
60 #define cprcfga (CPR0_DCR_BASE+0x0)
61 #define cprcfgd (CPR0_DCR_BASE+0x1)
62
63 #define SDR_DCR_BASE 0x0E
64 #define sdrcfga (SDR_DCR_BASE+0x0)
65 #define sdrcfgd (SDR_DCR_BASE+0x1)
66
67 #define SDRAM_DCR_BASE 0x10
68 #define memcfga (SDRAM_DCR_BASE+0x0)
69 #define memcfgd (SDRAM_DCR_BASE+0x1)
70
71 #define EBC_DCR_BASE 0x12
72 #define ebccfga (EBC_DCR_BASE+0x0)
73 #define ebccfgd (EBC_DCR_BASE+0x1)
74
75 /*
76 * Macros for indirect DCR access
77 */
78 #define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
79 #define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
80
81 #define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
82 #define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
83
84 #define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
85 #define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
86
87 #define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
88 #define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
89
90 #ifndef __ASSEMBLY__
91
92 typedef struct
93 {
94 unsigned long freqDDR;
95 unsigned long freqEBC;
96 unsigned long freqOPB;
97 unsigned long freqPCI;
98 unsigned long freqPLB;
99 unsigned long freqTmrClk;
100 unsigned long freqUART;
101 unsigned long freqProcessor;
102 unsigned long freqVCOHz;
103 unsigned long freqVCOMhz; /* in MHz */
104 unsigned long pciClkSync; /* PCI clock is synchronous */
105 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
106 unsigned long pllExtBusDiv;
107 unsigned long pllFbkDiv;
108 unsigned long pllFwdDiv;
109 unsigned long pllFwdDivA;
110 unsigned long pllFwdDivB;
111 unsigned long pllOpbDiv;
112 unsigned long pllPciDiv;
113 unsigned long pllPlbDiv;
114 } PPC4xx_SYS_INFO;
115
get_mcsr(void)116 static inline rt_uint32_t get_mcsr(void)
117 {
118 rt_uint32_t val;
119
120 asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
121 return val;
122 }
123
set_mcsr(rt_uint32_t val)124 static inline void set_mcsr(rt_uint32_t val)
125 {
126 asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
127 }
128
129 #endif /* __ASSEMBLY__ */
130
131 /* for multi-cpu support */
132 #define NA_OR_UNKNOWN_CPU -1
133
134 #endif /* __PPC4XX_H__ */
135