1 /*----------------------------------------------------------------------------+ 2 | 3 | This source code has been made available to you by IBM on an AS-IS 4 | basis. Anyone receiving this source is licensed under IBM 5 | copyrights to use it in any way he or she deems fit, including 6 | copying it, modifying it, compiling it, and redistributing it either 7 | with or without modifications. No license under IBM patents or 8 | patent applications is to be implied by the copyright license. 9 | 10 | Any user of this software should understand that IBM cannot provide 11 | technical support for this software and will not be responsible for 12 | any consequences resulting from the use of this software. 13 | 14 | Any person who transfers this source code or any derivative work 15 | must include the IBM copyright notice, this paragraph, and the 16 | preceding two paragraphs in the transferred software. 17 | 18 | COPYRIGHT I B M CORPORATION 1999 19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M 20 +----------------------------------------------------------------------------*/ 21 22 #ifndef __PPC405_H__ 23 #define __PPC405_H__ 24 25 /* Define bits and masks for real-mode storage attribute control registers */ 26 #define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) 27 #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) 28 29 /****************************************************************************** 30 * Special for PPC405GP 31 ******************************************************************************/ 32 33 /****************************************************************************** 34 * DMA 35 ******************************************************************************/ 36 #define DMA_DCR_BASE 0x100 37 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ 38 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ 39 #define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ 40 #define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ 41 #define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ 42 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ 43 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ 44 #define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ 45 #define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ 46 #define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ 47 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ 48 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ 49 #define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ 50 #define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ 51 #define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ 52 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ 53 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ 54 #define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ 55 #define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ 56 #define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ 57 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ 58 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ 59 #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ 60 61 #ifndef CONFIG_405EP 62 /****************************************************************************** 63 * Decompression Controller 64 ******************************************************************************/ 65 #define DECOMP_DCR_BASE 0x14 66 #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ 67 #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ 68 /* values for kiar register - indirect addressing of these regs */ 69 #define kitor0 0x00 /* index table origin register 0 */ 70 #define kitor1 0x01 /* index table origin register 1 */ 71 #define kitor2 0x02 /* index table origin register 2 */ 72 #define kitor3 0x03 /* index table origin register 3 */ 73 #define kaddr0 0x04 /* address decode definition regsiter 0 */ 74 #define kaddr1 0x05 /* address decode definition regsiter 1 */ 75 #define kconf 0x40 /* decompression core config register */ 76 #define kid 0x41 /* decompression core ID register */ 77 #define kver 0x42 /* decompression core version # reg */ 78 #define kpear 0x50 /* bus error addr reg (PLB addr) */ 79 #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ 80 #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ 81 #define kesr0s 0x53 /* bus error status reg 0 (set) */ 82 /* There are 0x400 of the following registers, from krom0 to krom3ff*/ 83 /* Only the first one is given here. */ 84 #define krom0 0x400 /* SRAM/ROM read/write */ 85 #endif 86 87 /****************************************************************************** 88 * Power Management 89 ******************************************************************************/ 90 #ifdef CONFIG_405EX 91 #define POWERMAN_DCR_BASE 0xb0 92 #else 93 #define POWERMAN_DCR_BASE 0xb8 94 #endif 95 #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ 96 #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ 97 #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ 98 99 /****************************************************************************** 100 * Extrnal Bus Controller 101 ******************************************************************************/ 102 /* values for ebccfga register - indirect addressing of these regs */ 103 #define pb0cr 0x00 /* periph bank 0 config reg */ 104 #define pb1cr 0x01 /* periph bank 1 config reg */ 105 #define pb2cr 0x02 /* periph bank 2 config reg */ 106 #define pb3cr 0x03 /* periph bank 3 config reg */ 107 #define pb4cr 0x04 /* periph bank 4 config reg */ 108 #ifndef CONFIG_405EP 109 #define pb5cr 0x05 /* periph bank 5 config reg */ 110 #define pb6cr 0x06 /* periph bank 6 config reg */ 111 #define pb7cr 0x07 /* periph bank 7 config reg */ 112 #endif 113 #define pb0ap 0x10 /* periph bank 0 access parameters */ 114 #define pb1ap 0x11 /* periph bank 1 access parameters */ 115 #define pb2ap 0x12 /* periph bank 2 access parameters */ 116 #define pb3ap 0x13 /* periph bank 3 access parameters */ 117 #define pb4ap 0x14 /* periph bank 4 access parameters */ 118 #ifndef CONFIG_405EP 119 #define pb5ap 0x15 /* periph bank 5 access parameters */ 120 #define pb6ap 0x16 /* periph bank 6 access parameters */ 121 #define pb7ap 0x17 /* periph bank 7 access parameters */ 122 #endif 123 #define pbear 0x20 /* periph bus error addr reg */ 124 #define pbesr0 0x21 /* periph bus error status reg 0 */ 125 #define pbesr1 0x22 /* periph bus error status reg 1 */ 126 #define epcr 0x23 /* external periph control reg */ 127 #define EBC0_CFG 0x23 /* external bus configuration reg */ 128 129 #ifdef CONFIG_405EP 130 /****************************************************************************** 131 * Control 132 ******************************************************************************/ 133 #define CNTRL_DCR_BASE 0x0f0 134 #define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ 135 #define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ 136 #define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ 137 #define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ 138 #define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ 139 #define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ 140 141 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ 142 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ 143 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ 144 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ 145 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ 146 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ 147 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ 148 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ 149 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ 150 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ 151 152 /* Bit definitions */ 153 #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ 154 #define PLLMR0_CPU_DIV_BYPASS 0x00000000 155 #define PLLMR0_CPU_DIV_2 0x00100000 156 #define PLLMR0_CPU_DIV_3 0x00200000 157 #define PLLMR0_CPU_DIV_4 0x00300000 158 159 #define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ 160 #define PLLMR0_CPU_PLB_DIV_1 0x00000000 161 #define PLLMR0_CPU_PLB_DIV_2 0x00010000 162 #define PLLMR0_CPU_PLB_DIV_3 0x00020000 163 #define PLLMR0_CPU_PLB_DIV_4 0x00030000 164 165 #define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ 166 #define PLLMR0_OPB_PLB_DIV_1 0x00000000 167 #define PLLMR0_OPB_PLB_DIV_2 0x00001000 168 #define PLLMR0_OPB_PLB_DIV_3 0x00002000 169 #define PLLMR0_OPB_PLB_DIV_4 0x00003000 170 171 #define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ 172 #define PLLMR0_EXB_PLB_DIV_2 0x00000000 173 #define PLLMR0_EXB_PLB_DIV_3 0x00000100 174 #define PLLMR0_EXB_PLB_DIV_4 0x00000200 175 #define PLLMR0_EXB_PLB_DIV_5 0x00000300 176 177 #define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ 178 #define PLLMR0_MAL_PLB_DIV_1 0x00000000 179 #define PLLMR0_MAL_PLB_DIV_2 0x00000010 180 #define PLLMR0_MAL_PLB_DIV_3 0x00000020 181 #define PLLMR0_MAL_PLB_DIV_4 0x00000030 182 183 #define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ 184 #define PLLMR0_PCI_PLB_DIV_1 0x00000000 185 #define PLLMR0_PCI_PLB_DIV_2 0x00000001 186 #define PLLMR0_PCI_PLB_DIV_3 0x00000002 187 #define PLLMR0_PCI_PLB_DIV_4 0x00000003 188 189 #define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ 190 #define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ 191 #define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ 192 #define PLLMR1_FBMUL_DIV_16 0x00000000 193 #define PLLMR1_FBMUL_DIV_1 0x00100000 194 #define PLLMR1_FBMUL_DIV_2 0x00200000 195 #define PLLMR1_FBMUL_DIV_3 0x00300000 196 #define PLLMR1_FBMUL_DIV_4 0x00400000 197 #define PLLMR1_FBMUL_DIV_5 0x00500000 198 #define PLLMR1_FBMUL_DIV_6 0x00600000 199 #define PLLMR1_FBMUL_DIV_7 0x00700000 200 #define PLLMR1_FBMUL_DIV_8 0x00800000 201 #define PLLMR1_FBMUL_DIV_9 0x00900000 202 #define PLLMR1_FBMUL_DIV_10 0x00A00000 203 #define PLLMR1_FBMUL_DIV_11 0x00B00000 204 #define PLLMR1_FBMUL_DIV_12 0x00C00000 205 #define PLLMR1_FBMUL_DIV_13 0x00D00000 206 #define PLLMR1_FBMUL_DIV_14 0x00E00000 207 #define PLLMR1_FBMUL_DIV_15 0x00F00000 208 209 #define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ 210 #define PLLMR1_FWDVA_DIV_8 0x00000000 211 #define PLLMR1_FWDVA_DIV_7 0x00010000 212 #define PLLMR1_FWDVA_DIV_6 0x00020000 213 #define PLLMR1_FWDVA_DIV_5 0x00030000 214 #define PLLMR1_FWDVA_DIV_4 0x00040000 215 #define PLLMR1_FWDVA_DIV_3 0x00050000 216 #define PLLMR1_FWDVA_DIV_2 0x00060000 217 #define PLLMR1_FWDVA_DIV_1 0x00070000 218 #define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ 219 #define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ 220 221 /* Defines for CPC0_EPRCSR register */ 222 #define CPC0_EPRCSR_E0NFE 0x80000000 223 #define CPC0_EPRCSR_E1NFE 0x40000000 224 #define CPC0_EPRCSR_E1RPP 0x00000080 225 #define CPC0_EPRCSR_E0RPP 0x00000040 226 #define CPC0_EPRCSR_E1ERP 0x00000020 227 #define CPC0_EPRCSR_E0ERP 0x00000010 228 #define CPC0_EPRCSR_E1PCI 0x00000002 229 #define CPC0_EPRCSR_E0PCI 0x00000001 230 231 /* Defines for CPC0_PCI Register */ 232 #define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ 233 #define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ 234 #define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ 235 236 /* Defines for CPC0_BOOR Register */ 237 #define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ 238 239 /* Defines for CPC0_PLLMR1 Register fields */ 240 #define PLL_ACTIVE 0x80000000 241 #define CPC0_PLLMR1_SSCS 0x80000000 242 #define PLL_RESET 0x40000000 243 #define CPC0_PLLMR1_PLLR 0x40000000 244 /* Feedback multiplier */ 245 #define PLL_FBKDIV 0x00F00000 246 #define CPC0_PLLMR1_FBDV 0x00F00000 247 #define PLL_FBKDIV_16 0x00000000 248 #define PLL_FBKDIV_1 0x00100000 249 #define PLL_FBKDIV_2 0x00200000 250 #define PLL_FBKDIV_3 0x00300000 251 #define PLL_FBKDIV_4 0x00400000 252 #define PLL_FBKDIV_5 0x00500000 253 #define PLL_FBKDIV_6 0x00600000 254 #define PLL_FBKDIV_7 0x00700000 255 #define PLL_FBKDIV_8 0x00800000 256 #define PLL_FBKDIV_9 0x00900000 257 #define PLL_FBKDIV_10 0x00A00000 258 #define PLL_FBKDIV_11 0x00B00000 259 #define PLL_FBKDIV_12 0x00C00000 260 #define PLL_FBKDIV_13 0x00D00000 261 #define PLL_FBKDIV_14 0x00E00000 262 #define PLL_FBKDIV_15 0x00F00000 263 /* Forward A divisor */ 264 #define PLL_FWDDIVA 0x00070000 265 #define CPC0_PLLMR1_FWDVA 0x00070000 266 #define PLL_FWDDIVA_8 0x00000000 267 #define PLL_FWDDIVA_7 0x00010000 268 #define PLL_FWDDIVA_6 0x00020000 269 #define PLL_FWDDIVA_5 0x00030000 270 #define PLL_FWDDIVA_4 0x00040000 271 #define PLL_FWDDIVA_3 0x00050000 272 #define PLL_FWDDIVA_2 0x00060000 273 #define PLL_FWDDIVA_1 0x00070000 274 /* Forward B divisor */ 275 #define PLL_FWDDIVB 0x00007000 276 #define CPC0_PLLMR1_FWDVB 0x00007000 277 #define PLL_FWDDIVB_8 0x00000000 278 #define PLL_FWDDIVB_7 0x00001000 279 #define PLL_FWDDIVB_6 0x00002000 280 #define PLL_FWDDIVB_5 0x00003000 281 #define PLL_FWDDIVB_4 0x00004000 282 #define PLL_FWDDIVB_3 0x00005000 283 #define PLL_FWDDIVB_2 0x00006000 284 #define PLL_FWDDIVB_1 0x00007000 285 /* PLL tune bits */ 286 #define PLL_TUNE_MASK 0x000003FF 287 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ 288 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ 289 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ 290 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ 291 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ 292 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ 293 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ 294 295 /* Defines for CPC0_PLLMR0 Register fields */ 296 /* CPU divisor */ 297 #define PLL_CPUDIV 0x00300000 298 #define CPC0_PLLMR0_CCDV 0x00300000 299 #define PLL_CPUDIV_1 0x00000000 300 #define PLL_CPUDIV_2 0x00100000 301 #define PLL_CPUDIV_3 0x00200000 302 #define PLL_CPUDIV_4 0x00300000 303 /* PLB divisor */ 304 #define PLL_PLBDIV 0x00030000 305 #define CPC0_PLLMR0_CBDV 0x00030000 306 #define PLL_PLBDIV_1 0x00000000 307 #define PLL_PLBDIV_2 0x00010000 308 #define PLL_PLBDIV_3 0x00020000 309 #define PLL_PLBDIV_4 0x00030000 310 /* OPB divisor */ 311 #define PLL_OPBDIV 0x00003000 312 #define CPC0_PLLMR0_OPDV 0x00003000 313 #define PLL_OPBDIV_1 0x00000000 314 #define PLL_OPBDIV_2 0x00001000 315 #define PLL_OPBDIV_3 0x00002000 316 #define PLL_OPBDIV_4 0x00003000 317 /* EBC divisor */ 318 #define PLL_EXTBUSDIV 0x00000300 319 #define CPC0_PLLMR0_EPDV 0x00000300 320 #define PLL_EXTBUSDIV_2 0x00000000 321 #define PLL_EXTBUSDIV_3 0x00000100 322 #define PLL_EXTBUSDIV_4 0x00000200 323 #define PLL_EXTBUSDIV_5 0x00000300 324 /* MAL divisor */ 325 #define PLL_MALDIV 0x00000030 326 #define CPC0_PLLMR0_MPDV 0x00000030 327 #define PLL_MALDIV_1 0x00000000 328 #define PLL_MALDIV_2 0x00000010 329 #define PLL_MALDIV_3 0x00000020 330 #define PLL_MALDIV_4 0x00000030 331 /* PCI divisor */ 332 #define PLL_PCIDIV 0x00000003 333 #define CPC0_PLLMR0_PPFD 0x00000003 334 #define PLL_PCIDIV_1 0x00000000 335 #define PLL_PCIDIV_2 0x00000001 336 #define PLL_PCIDIV_3 0x00000002 337 #define PLL_PCIDIV_4 0x00000003 338 339 /* 340 *------------------------------------------------------------------------------- 341 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, 342 * assuming a 33.3MHz input clock to the 405EP. 343 *------------------------------------------------------------------------------- 344 */ 345 #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ 346 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ 347 PLL_MALDIV_1 | PLL_PCIDIV_4) 348 #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ 349 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ 350 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 351 352 #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ 353 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ 354 PLL_MALDIV_1 | PLL_PCIDIV_4) 355 #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ 356 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ 357 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 358 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ 359 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ 360 PLL_MALDIV_1 | PLL_PCIDIV_4) 361 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ 362 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ 363 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 364 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ 365 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ 366 PLL_MALDIV_1 | PLL_PCIDIV_4) 367 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ 368 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ 369 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 370 #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ 371 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ 372 PLL_MALDIV_1 | PLL_PCIDIV_2) 373 #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ 374 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ 375 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) 376 #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ 377 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ 378 PLL_MALDIV_1 | PLL_PCIDIV_3) 379 #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ 380 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ 381 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) 382 #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ 383 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ 384 PLL_MALDIV_1 | PLL_PCIDIV_1) 385 #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ 386 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ 387 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) 388 389 /* 390 * PLL Voltage Controlled Oscillator (VCO) definitions 391 * Maximum and minimum values (in MHz) for correct PLL operation. 392 */ 393 #define VCO_MIN 500 394 #define VCO_MAX 1000 395 #elif defined(CONFIG_405EZ) 396 #define sdrnand0 0x4000 397 #define sdrultra0 0x4040 398 #define sdrultra1 0x4050 399 #define sdricintstat 0x4510 400 401 #define SDR_NAND0_NDEN 0x80000000 402 #define SDR_NAND0_NDBTEN 0x40000000 403 #define SDR_NAND0_NDBADR_MASK 0x30000000 404 #define SDR_NAND0_NDBPG_MASK 0x0f000000 405 #define SDR_NAND0_NDAREN 0x00800000 406 #define SDR_NAND0_NDRBEN 0x00400000 407 408 #define SDR_ULTRA0_NDGPIOBP 0x80000000 409 #define SDR_ULTRA0_CSN_MASK 0x78000000 410 #define SDR_ULTRA0_CSNSEL0 0x40000000 411 #define SDR_ULTRA0_CSNSEL1 0x20000000 412 #define SDR_ULTRA0_CSNSEL2 0x10000000 413 #define SDR_ULTRA0_CSNSEL3 0x08000000 414 #define SDR_ULTRA0_EBCRDYEN 0x04000000 415 #define SDR_ULTRA0_SPISSINEN 0x02000000 416 #define SDR_ULTRA0_NFSRSTEN 0x01000000 417 418 #define SDR_ULTRA1_LEDNENABLE 0x40000000 419 420 #define SDR_ICRX_STAT 0x80000000 421 #define SDR_ICTX0_STAT 0x40000000 422 #define SDR_ICTX1_STAT 0x20000000 423 424 #define SDR_PINSTP 0x40 425 426 /****************************************************************************** 427 * Control 428 ******************************************************************************/ 429 /* CPR Registers */ 430 #define cprclkupd 0x020 /* CPR_CLKUPD */ 431 #define cprpllc 0x040 /* CPR_PLLC */ 432 #define cprplld 0x060 /* CPR_PLLD */ 433 #define cprprimad 0x080 /* CPR_PRIMAD */ 434 #define cprperd0 0x0e0 /* CPR_PERD0 */ 435 #define cprperd1 0x0e1 /* CPR_PERD1 */ 436 #define cprperc0 0x180 /* CPR_PERC0 */ 437 #define cprmisc0 0x181 /* CPR_MISC0 */ 438 #define cprmisc1 0x182 /* CPR_MISC1 */ 439 440 #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ 441 #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ 442 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ 443 444 #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ 445 446 #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ 447 #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ 448 #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ 449 450 #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ 451 #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ 452 #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ 453 #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ 454 455 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ 456 #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ 457 #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ 458 #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ 459 460 #else /* #ifdef CONFIG_405EP */ 461 /****************************************************************************** 462 * Control 463 ******************************************************************************/ 464 #define CNTRL_DCR_BASE 0x0b0 465 #define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ 466 #define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ 467 #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ 468 #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ 469 #define strap (CNTRL_DCR_BASE+0x4) /* strap register */ 470 471 #define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ 472 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ 473 #define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ 474 475 /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ 476 #define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ 477 #define CPC0_ECR (0xaa) /* edge conditioner register */ 478 479 #define ecr (0xaa) /* edge conditioner register (405gpr) */ 480 481 /* Bit definitions */ 482 #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ 483 #define PLLMR_FWD_DIV_BYPASS 0xE0000000 484 #define PLLMR_FWD_DIV_3 0xA0000000 485 #define PLLMR_FWD_DIV_4 0x80000000 486 #define PLLMR_FWD_DIV_6 0x40000000 487 488 #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ 489 #define PLLMR_FB_DIV_1 0x02000000 490 #define PLLMR_FB_DIV_2 0x04000000 491 #define PLLMR_FB_DIV_3 0x06000000 492 #define PLLMR_FB_DIV_4 0x08000000 493 494 #define PLLMR_TUNING_MASK 0x01F80000 495 496 #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ 497 #define PLLMR_CPU_PLB_DIV_1 0x00000000 498 #define PLLMR_CPU_PLB_DIV_2 0x00020000 499 #define PLLMR_CPU_PLB_DIV_3 0x00040000 500 #define PLLMR_CPU_PLB_DIV_4 0x00060000 501 502 #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ 503 #define PLLMR_OPB_PLB_DIV_1 0x00000000 504 #define PLLMR_OPB_PLB_DIV_2 0x00008000 505 #define PLLMR_OPB_PLB_DIV_3 0x00010000 506 #define PLLMR_OPB_PLB_DIV_4 0x00018000 507 508 #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ 509 #define PLLMR_PCI_PLB_DIV_1 0x00000000 510 #define PLLMR_PCI_PLB_DIV_2 0x00002000 511 #define PLLMR_PCI_PLB_DIV_3 0x00004000 512 #define PLLMR_PCI_PLB_DIV_4 0x00006000 513 514 #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ 515 #define PLLMR_EXB_PLB_DIV_2 0x00000000 516 #define PLLMR_EXB_PLB_DIV_3 0x00000800 517 #define PLLMR_EXB_PLB_DIV_4 0x00001000 518 #define PLLMR_EXB_PLB_DIV_5 0x00001800 519 520 /* definitions for PPC405GPr (new mode strapping) */ 521 #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ 522 523 #define PSR_PLL_FWD_MASK 0xC0000000 524 #define PSR_PLL_FDBACK_MASK 0x30000000 525 #define PSR_PLL_TUNING_MASK 0x0E000000 526 #define PSR_PLB_CPU_MASK 0x01800000 527 #define PSR_OPB_PLB_MASK 0x00600000 528 #define PSR_PCI_PLB_MASK 0x00180000 529 #define PSR_EB_PLB_MASK 0x00060000 530 #define PSR_ROM_WIDTH_MASK 0x00018000 531 #define PSR_ROM_LOC 0x00004000 532 #define PSR_PCI_ASYNC_EN 0x00001000 533 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ 534 #define PSR_PCI_ARBIT_EN 0x00000400 535 #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ 536 537 #ifndef CONFIG_IOP480 538 /* 539 * PLL Voltage Controlled Oscillator (VCO) definitions 540 * Maximum and minimum values (in MHz) for correct PLL operation. 541 */ 542 #define VCO_MIN 400 543 #define VCO_MAX 800 544 #endif /* #ifndef CONFIG_IOP480 */ 545 #endif /* #ifdef CONFIG_405EP */ 546 547 /****************************************************************************** 548 * Memory Access Layer 549 ******************************************************************************/ 550 #if defined(CONFIG_405EZ) 551 #define MAL_DCR_BASE 0x380 552 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ 553 #define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ 554 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ 555 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ 556 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ 557 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ 558 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ 559 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ 560 /* 0x08-0x0F Reserved */ 561 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ 562 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ 563 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ 564 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ 565 /* 0x14-0x1F Reserved */ 566 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ 567 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ 568 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ 569 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ 570 #define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ 571 #define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ 572 #define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ 573 #define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ 574 #define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ 575 #define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ 576 #define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ 577 #define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ 578 #define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ 579 #define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ 580 #define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ 581 #define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ 582 #define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ 583 #define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ 584 #define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ 585 #define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ 586 #define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ 587 #define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ 588 #define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ 589 #define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ 590 #define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ 591 #define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ 592 #define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ 593 #define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ 594 #define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ 595 #define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ 596 #define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ 597 #define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ 598 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ 599 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ 600 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ 601 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ 602 #define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ 603 #define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ 604 #define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ 605 #define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ 606 #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ 607 #define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ 608 #define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ 609 #define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ 610 #define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ 611 #define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ 612 #define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ 613 #define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ 614 #define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ 615 #define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ 616 #define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ 617 #define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ 618 #define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ 619 #define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ 620 #define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ 621 #define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ 622 #define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ 623 #define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ 624 #define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ 625 #define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ 626 #define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ 627 #define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ 628 #define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ 629 #define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ 630 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ 631 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ 632 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ 633 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ 634 #define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ 635 #define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ 636 #define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ 637 #define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ 638 #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ 639 #define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ 640 #define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ 641 #define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ 642 #define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ 643 #define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ 644 #define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ 645 #define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ 646 #define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ 647 #define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ 648 #define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ 649 #define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ 650 #define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ 651 #define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ 652 #define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ 653 #define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ 654 #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ 655 #define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ 656 #define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ 657 #define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ 658 #define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ 659 #define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ 660 #define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ 661 #define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ 662 663 #else /* !defined(CONFIG_405EZ) */ 664 665 #define MAL_DCR_BASE 0x180 666 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ 667 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ 668 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ 669 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ 670 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ 671 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ 672 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ 673 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ 674 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ 675 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ 676 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ 677 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ 678 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ 679 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ 680 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ 681 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ 682 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ 683 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ 684 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ 685 #endif /* defined(CONFIG_405EZ) */ 686 687 /*----------------------------------------------------------------------------- 688 | IIC Register Offsets 689 '----------------------------------------------------------------------------*/ 690 #define IICMDBUF 0x00 691 #define IICSDBUF 0x02 692 #define IICLMADR 0x04 693 #define IICHMADR 0x05 694 #define IICCNTL 0x06 695 #define IICMDCNTL 0x07 696 #define IICSTS 0x08 697 #define IICEXTSTS 0x09 698 #define IICLSADR 0x0A 699 #define IICHSADR 0x0B 700 #define IICCLKDIV 0x0C 701 #define IICINTRMSK 0x0D 702 #define IICXFRCNT 0x0E 703 #define IICXTCNTLSS 0x0F 704 #define IICDIRECTCNTL 0x10 705 706 /*----------------------------------------------------------------------------- 707 | UART Register Offsets 708 '----------------------------------------------------------------------------*/ 709 #define DATA_REG 0x00 710 #define DL_LSB 0x00 711 #define DL_MSB 0x01 712 #define INT_ENABLE 0x01 713 #define FIFO_CONTROL 0x02 714 #define LINE_CONTROL 0x03 715 #define MODEM_CONTROL 0x04 716 #define LINE_STATUS 0x05 717 #define MODEM_STATUS 0x06 718 #define SCRATCH 0x07 719 720 /****************************************************************************** 721 * On Chip Memory 722 ******************************************************************************/ 723 #if defined(CONFIG_405EZ) 724 #define OCM_DCR_BASE 0x020 725 #define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ 726 #define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ 727 #define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ 728 #define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ 729 #define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ 730 #define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ 731 #define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ 732 #define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ 733 #define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ 734 #define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ 735 #define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ 736 #define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ 737 #define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ 738 #define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ 739 #define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ 740 #else 741 #define OCM_DCR_BASE 0x018 742 #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ 743 #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ 744 #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ 745 #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ 746 #endif /* CONFIG_405EZ */ 747 748 /****************************************************************************** 749 * GPIO macro register defines 750 ******************************************************************************/ 751 #if defined(CONFIG_405EZ) 752 /* Only the 405EZ has 2 GPIOs */ 753 #define GPIO_BASE 0xEF600700 754 #define GPIO0_OR (GPIO_BASE+0x0) 755 #define GPIO0_TCR (GPIO_BASE+0x4) 756 #define GPIO0_OSRL (GPIO_BASE+0x8) 757 #define GPIO0_OSRH (GPIO_BASE+0xC) 758 #define GPIO0_TSRL (GPIO_BASE+0x10) 759 #define GPIO0_TSRH (GPIO_BASE+0x14) 760 #define GPIO0_ODR (GPIO_BASE+0x18) 761 #define GPIO0_IR (GPIO_BASE+0x1C) 762 #define GPIO0_RR1 (GPIO_BASE+0x20) 763 #define GPIO0_RR2 (GPIO_BASE+0x24) 764 #define GPIO0_RR3 (GPIO_BASE+0x28) 765 #define GPIO0_ISR1L (GPIO_BASE+0x30) 766 #define GPIO0_ISR1H (GPIO_BASE+0x34) 767 #define GPIO0_ISR2L (GPIO_BASE+0x38) 768 #define GPIO0_ISR2H (GPIO_BASE+0x3C) 769 #define GPIO0_ISR3L (GPIO_BASE+0x40) 770 #define GPIO0_ISR3H (GPIO_BASE+0x44) 771 772 #define GPIO1_BASE 0xEF600800 773 #define GPIO1_OR (GPIO1_BASE+0x0) 774 #define GPIO1_TCR (GPIO1_BASE+0x4) 775 #define GPIO1_OSRL (GPIO1_BASE+0x8) 776 #define GPIO1_OSRH (GPIO1_BASE+0xC) 777 #define GPIO1_TSRL (GPIO1_BASE+0x10) 778 #define GPIO1_TSRH (GPIO1_BASE+0x14) 779 #define GPIO1_ODR (GPIO1_BASE+0x18) 780 #define GPIO1_IR (GPIO1_BASE+0x1C) 781 #define GPIO1_RR1 (GPIO1_BASE+0x20) 782 #define GPIO1_RR2 (GPIO1_BASE+0x24) 783 #define GPIO1_RR3 (GPIO1_BASE+0x28) 784 #define GPIO1_ISR1L (GPIO1_BASE+0x30) 785 #define GPIO1_ISR1H (GPIO1_BASE+0x34) 786 #define GPIO1_ISR2L (GPIO1_BASE+0x38) 787 #define GPIO1_ISR2H (GPIO1_BASE+0x3C) 788 #define GPIO1_ISR3L (GPIO1_BASE+0x40) 789 #define GPIO1_ISR3H (GPIO1_BASE+0x44) 790 791 #elif defined(CONFIG_405EX) 792 #define GPIO_BASE 0xEF600800 793 #define GPIO0_OR (GPIO_BASE+0x0) 794 #define GPIO0_TCR (GPIO_BASE+0x4) 795 #define GPIO0_OSRL (GPIO_BASE+0x8) 796 #define GPIO0_OSRH (GPIO_BASE+0xC) 797 #define GPIO0_TSRL (GPIO_BASE+0x10) 798 #define GPIO0_TSRH (GPIO_BASE+0x14) 799 #define GPIO0_ODR (GPIO_BASE+0x18) 800 #define GPIO0_IR (GPIO_BASE+0x1C) 801 #define GPIO0_RR1 (GPIO_BASE+0x20) 802 #define GPIO0_RR2 (GPIO_BASE+0x24) 803 #define GPIO0_ISR1L (GPIO_BASE+0x30) 804 #define GPIO0_ISR1H (GPIO_BASE+0x34) 805 #define GPIO0_ISR2L (GPIO_BASE+0x38) 806 #define GPIO0_ISR2H (GPIO_BASE+0x3C) 807 #define GPIO0_ISR3L (GPIO_BASE+0x40) 808 #define GPIO0_ISR3H (GPIO_BASE+0x44) 809 810 #else /* !405EZ */ 811 812 #define GPIO_BASE 0xEF600700 813 #define GPIO0_OR (GPIO_BASE+0x0) 814 #define GPIO0_TCR (GPIO_BASE+0x4) 815 #define GPIO0_OSRH (GPIO_BASE+0x8) 816 #define GPIO0_OSRL (GPIO_BASE+0xC) 817 #define GPIO0_TSRH (GPIO_BASE+0x10) 818 #define GPIO0_TSRL (GPIO_BASE+0x14) 819 #define GPIO0_ODR (GPIO_BASE+0x18) 820 #define GPIO0_IR (GPIO_BASE+0x1C) 821 #define GPIO0_RR1 (GPIO_BASE+0x20) 822 #define GPIO0_RR2 (GPIO_BASE+0x24) 823 #define GPIO0_ISR1H (GPIO_BASE+0x30) 824 #define GPIO0_ISR1L (GPIO_BASE+0x34) 825 #define GPIO0_ISR2H (GPIO_BASE+0x38) 826 #define GPIO0_ISR2L (GPIO_BASE+0x3C) 827 828 #endif /* CONFIG_405EZ */ 829 830 #define GPIO0_BASE GPIO_BASE 831 832 #if defined(CONFIG_405EX) 833 #define SDR0_SRST 0x0200 834 835 /* 836 * Software Reset Register 837 */ 838 #define SDR0_SRST_BGO PPC_REG_VAL(0, 1) 839 #define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) 840 #define SDR0_SRST_EBC PPC_REG_VAL(2, 1) 841 #define SDR0_SRST_OPB PPC_REG_VAL(3, 1) 842 #define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) 843 #define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) 844 #define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) 845 #define SDR0_SRST_BGI PPC_REG_VAL(7, 1) 846 #define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) 847 #define SDR0_SRST_GPT PPC_REG_VAL(9, 1) 848 #define SDR0_SRST_DMC PPC_REG_VAL(10, 1) 849 #define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) 850 #define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) 851 #define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) 852 #define SDR0_SRST_CPM PPC_REG_VAL(14, 1) 853 #define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) 854 #define SDR0_SRST_UIC PPC_REG_VAL(16, 1) 855 #define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) 856 #define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) 857 #define SDR0_SRST_SCP PPC_REG_VAL(19, 1) 858 #define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) 859 #define SDR0_SRST_DMA PPC_REG_VAL(21, 1) 860 #define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) 861 #define SDR0_SRST_MAL PPC_REG_VAL(23, 1) 862 #define SDR0_SRST_EBM PPC_REG_VAL(24, 1) 863 #define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) 864 #define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) 865 #define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) 866 #define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) 867 #define SDR0_SRST_PKP PPC_REG_VAL(29, 1) 868 #define SDR0_SRST_AHB PPC_REG_VAL(30, 1) 869 #define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) 870 871 #define sdr_uart0 0x0120 /* UART0 Config */ 872 #define sdr_uart1 0x0121 /* UART1 Config */ 873 #define sdr_mfr 0x4300 /* SDR0_MFR reg */ 874 875 /* Defines for CPC0_EPRCSR register */ 876 #define CPC0_EPRCSR_E0NFE 0x80000000 877 #define CPC0_EPRCSR_E1NFE 0x40000000 878 #define CPC0_EPRCSR_E1RPP 0x00000080 879 #define CPC0_EPRCSR_E0RPP 0x00000040 880 #define CPC0_EPRCSR_E1ERP 0x00000020 881 #define CPC0_EPRCSR_E0ERP 0x00000010 882 #define CPC0_EPRCSR_E1PCI 0x00000002 883 #define CPC0_EPRCSR_E0PCI 0x00000001 884 885 #define cpr0_clkupd 0x020 886 #define cpr0_pllc 0x040 887 #define cpr0_plld 0x060 888 #define cpr0_cpud 0x080 889 #define cpr0_plbd 0x0a0 890 #define cpr0_opbd 0x0c0 891 #define cpr0_perd 0x0e0 892 #define cpr0_ahbd 0x100 893 #define cpr0_icfg 0x140 894 895 #define SDR_PINSTP 0x0040 896 #define sdr_sdcs 0x0060 897 898 #define SDR0_SDCS_SDD (0x80000000 >> 31) 899 900 /* CUST0 Customer Configuration Register0 */ 901 #define SDR0_CUST0 0x4000 902 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ 903 #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ 904 #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ 905 #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ 906 907 #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ 908 #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ 909 #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ 910 911 #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ 912 #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ 913 #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ 914 915 #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ 916 #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) 917 #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) 918 919 #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ 920 #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) 921 #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) 922 923 #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ 924 #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ 925 #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ 926 927 #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ 928 #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ 929 #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ 930 931 #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ 932 #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) 933 #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) 934 935 #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ 936 #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ 937 #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ 938 #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ 939 #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ 940 #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ 941 #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ 942 943 #define SDR0_PFC0 0x4100 944 #define SDR0_PFC1 0x4101 945 #define SDR0_PFC1_U1ME 0x02000000 946 #define SDR0_PFC1_U0ME 0x00080000 947 #define SDR0_PFC1_U0IM 0x00040000 948 #define SDR0_PFC1_SIS 0x00020000 949 #define SDR0_PFC1_DMAAEN 0x00010000 950 #define SDR0_PFC1_DMADEN 0x00008000 951 #define SDR0_PFC1_USBEN 0x00004000 952 #define SDR0_PFC1_AHBSWAP 0x00000020 953 #define SDR0_PFC1_USBBIGEN 0x00000010 954 #define SDR0_PFC1_GPT_FREQ 0x0000000f 955 #endif 956 957 /* General Purpose Timer (GPT) Register Offsets */ 958 #define GPT0_TBC 0x00000000 959 #define GPT0_IM 0x00000018 960 #define GPT0_ISS 0x0000001C 961 #define GPT0_ISC 0x00000020 962 #define GPT0_IE 0x00000024 963 #define GPT0_COMP0 0x00000080 964 #define GPT0_COMP1 0x00000084 965 #define GPT0_COMP2 0x00000088 966 #define GPT0_COMP3 0x0000008C 967 #define GPT0_COMP4 0x00000090 968 #define GPT0_COMP5 0x00000094 969 #define GPT0_COMP6 0x00000098 970 #define GPT0_MASK0 0x000000C0 971 #define GPT0_MASK1 0x000000C4 972 #define GPT0_MASK2 0x000000C8 973 #define GPT0_MASK3 0x000000CC 974 #define GPT0_MASK4 0x000000D0 975 #define GPT0_MASK5 0x000000D4 976 #define GPT0_MASK6 0x000000D8 977 #define GPT0_DCT0 0x00000110 978 #define GPT0_DCIS 0x0000011C 979 980 #endif /* __PPC405_H__ */ 981