1 /* 2 * File : x1000.h 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Change Logs: 21 * Date Author Notes 22 * 2015-11-19 Urey the first version 23 */ 24 25 #ifndef X1000_H__ 26 #define X1000_H__ 27 28 #ifndef __ASSEMBLY__ 29 30 // typedef unsigned int size_t; 31 #define u64 unsigned long long 32 #define u32 unsigned int 33 #define u16 unsigned short 34 #define u8 unsigned char 35 36 #define U64 unsigned long long 37 #define U32 unsigned int 38 #define U16 unsigned short 39 #define U8 unsigned char 40 41 #define S64 signed long long 42 #define S32 int 43 #define S16 short int 44 #define S8 signed char 45 46 #define cache_unroll(base,op) \ 47 __asm__ __volatile__(" \ 48 .set noreorder; \ 49 .set mips3; \ 50 cache %1, (%0); \ 51 .set mips0; \ 52 .set reorder" \ 53 : \ 54 : "r" (base), \ 55 "i" (op)); 56 57 /* cpu pipeline flush */ 58 static inline void jz_sync(void) 59 { 60 __asm__ volatile ("sync"); 61 } 62 63 static inline void writeb(u8 value, u32 address) 64 { 65 *((volatile u8 *) address) = value; 66 } 67 static inline void writew( u16 value, u32 address) 68 { 69 *((volatile u16 *) address) = value; 70 } 71 static inline void writel(u32 value, u32 address) 72 { 73 *((volatile u32 *) address) = value; 74 } 75 76 static inline u8 readb(u32 address) 77 { 78 return *((volatile u8 *)address); 79 } 80 81 static inline u16 readw(u32 address) 82 { 83 return *((volatile u16 *)address); 84 } 85 86 static inline u32 readl(u32 address) 87 { 88 return *((volatile u32 *)address); 89 } 90 91 static inline void jz_writeb(u32 address, u8 value) 92 { 93 *((volatile u8 *)address) = value; 94 } 95 96 static inline void jz_writew(u32 address, u16 value) 97 { 98 *((volatile u16 *)address) = value; 99 } 100 101 static inline void jz_writel(u32 address, u32 value) 102 { 103 *((volatile u32 *)address) = value; 104 } 105 106 static inline u8 jz_readb(u32 address) 107 { 108 return *((volatile u8 *)address); 109 } 110 111 static inline u16 jz_readw(u32 address) 112 { 113 return *((volatile u16 *)address); 114 } 115 116 static inline u32 jz_readl(u32 address) 117 { 118 return *((volatile u32 *)address); 119 } 120 121 #define REG8(addr) *((volatile u8 *)(addr)) 122 #define REG16(addr) *((volatile u16 *)(addr)) 123 #define REG32(addr) *((volatile u32 *)(addr)) 124 125 #define BIT(n) (0x01u << (n)) 126 127 #else 128 129 #define REG8(addr) (addr) 130 #define REG16(addr) (addr) 131 #define REG32(addr) (addr) 132 133 #endif /* !ASSEMBLY */ 134 135 136 //---------------------------------------------------------------------- 137 // Register Definitions 138 // 139 /* AHB0 BUS Devices Base */ 140 #define HARB0_BASE 0xB3000000 141 #define EMC_BASE 0xB3010000 142 #define DDRC_BASE 0xB3020000 143 #define MDMAC_BASE 0xB3030000 144 #define LCD_BASE 0xB3050000 145 #define TVE_BASE 0xB3050000 146 #define SLCD_BASE 0xB3050000 147 #define CIM_BASE 0xB3060000 148 #define IPU_BASE 0xB3080000 149 /* AHB1 BUS Devices Base */ 150 #define HARB1_BASE 0xB3200000 151 #define DMAGP0_BASE 0xB3210000 152 #define DMAGP1_BASE 0xB3220000 153 #define DMAGP2_BASE 0xB3230000 154 #define MC_BASE 0xB3250000 155 #define ME_BASE 0xB3260000 156 #define DEBLK_BASE 0xB3270000 157 #define IDCT_BASE 0xB3280000 158 #define CABAC_BASE 0xB3290000 159 #define TCSM0_BASE 0xB32B0000 160 #define TCSM1_BASE 0xB32C0000 161 #define SRAM_BASE 0xB32D0000 162 /* AHB2 BUS Devices Base */ 163 #define HARB2_BASE 0xB3400000 164 #define NEMC_BASE 0xB3410000 165 #define DMAC_BASE 0xB3420000 166 #define UHC_BASE 0xB3430000 167 #define UDC_BASE 0xB3440000 168 #define GPS_BASE 0xB3480000 169 #define ETHC_BASE 0xB34B0000 170 #define BCH_BASE 0xB34D0000 171 #define MSC0_BASE 0xB3450000 172 #define MSC1_BASE 0xB3460000 173 #define MSC2_BASE 0xB3470000 174 175 /* APB BUS Devices Base */ 176 #define CPM_BASE 0xB0000000 177 #define INTC_BASE 0xB0001000 178 #define TCU_BASE 0xB0002000 179 #define WDT_BASE 0xB0002000 180 #define OST_BASE 0xB2000000 /* OS Timer */ 181 #define RTC_BASE 0xB0003000 182 #define GPIO_BASE 0xB0010000 183 #define AIC_BASE 0xB0020000 184 #define DMIC_BASE 0xB0021000 185 #define ICDC_BASE 0xB0020000 186 #define UART0_BASE 0xB0030000 187 #define UART1_BASE 0xB0031000 188 #define UART2_BASE 0xB0032000 189 #define UART3_BASE 0xB0033000 190 #define SCC_BASE 0xB0040000 191 #define SSI0_BASE 0xB0043000 192 #define SSI1_BASE 0xB0044000 193 #define SSI2_BASE 0xB0045000 194 #define I2C0_BASE 0xB0050000 195 #define I2C1_BASE 0xB0051000 196 #define PS2_BASE 0xB0060000 197 #define SADC_BASE 0xB0070000 198 #define OWI_BASE 0xB0072000 199 #define TSSI_BASE 0xB0073000 200 201 /* NAND CHIP Base Address*/ 202 #define NEMC_CS1_IOBASE 0Xbb000000 203 #define NEMC_CS2_IOBASE 0Xba000000 204 #define NEMC_CS3_IOBASE 0Xb9000000 205 #define NEMC_CS4_IOBASE 0Xb8000000 206 #define NEMC_CS5_IOBASE 0Xb7000000 207 #define NEMC_CS6_IOBASE 0Xb6000000 208 209 /********************************************************************************************************* 210 ** WDT 211 *********************************************************************************************************/ 212 #define WDT_TDR (WDT_BASE + 0x00) 213 #define WDT_TCER (WDT_BASE + 0x04) 214 #define WDT_TCNT (WDT_BASE + 0x08) 215 #define WDT_TCSR (WDT_BASE + 0x0C) 216 217 #define REG_WDT_TDR REG16(WDT_TDR) 218 #define REG_WDT_TCER REG8(WDT_TCER) 219 #define REG_WDT_TCNT REG16(WDT_TCNT) 220 #define REG_WDT_TCSR REG16(WDT_TCSR) 221 222 #define WDT_TSCR_WDTSC (1 << 16) 223 224 #define WDT_TCSR_PRESCALE_1 (0 << 3) 225 #define WDT_TCSR_PRESCALE_4 (1 << 3) 226 #define WDT_TCSR_PRESCALE_16 (2 << 3) 227 #define WDT_TCSR_PRESCALE_64 (3 << 3) 228 #define WDT_TCSR_PRESCALE_256 (4 << 3) 229 #define WDT_TCSR_PRESCALE_1024 (5 << 3) 230 231 #define WDT_TCSR_EXT_EN (1 << 2) 232 #define WDT_TCSR_RTC_EN (1 << 1) 233 #define WDT_TCSR_PCK_EN (1 << 0) 234 235 #define WDT_TCER_TCEN (1 << 0) 236 237 /********************************************************************************************************* 238 ** �ж�Դ 239 *********************************************************************************************************/ 240 /* INTC (Interrupt Controller) */ 241 #define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20) 242 #define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20) 243 #define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20) 244 #define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20) 245 #define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20) 246 247 #define REG_INTC_ISR(n) REG32(INTC_ISR((n))) 248 #define REG_INTC_IMR(n) REG32(INTC_IMR((n))) 249 #define REG_INTC_IMSR(n) REG32(INTC_IMSR((n))) 250 #define REG_INTC_IMCR(n) REG32(INTC_IMCR((n))) 251 #define REG_INTC_IPR(n) REG32(INTC_IPR((n))) 252 253 // interrupt controller interrupts 254 #define IRQ_DMIC 0 255 #define IRQ_AIC0 1 256 #define IRQ_RESERVED2 2 257 #define IRQ_RESERVED3 3 258 #define IRQ_RESERVED4 4 259 #define IRQ_RESERVED5 5 260 #define IRQ_RESERVED6 6 261 #define IRQ_SFC 7 262 #define IRQ_SSI0 8 263 #define IRQ_RESERVED9 9 264 #define IRQ_PDMA 10 265 #define IRQ_PDMAD 11 266 #define IRQ_RESERVED12 12 267 #define IRQ_RESERVED13 13 268 #define IRQ_GPIO3 14 269 #define IRQ_GPIO2 15 270 #define IRQ_GPIO1 16 271 #define IRQ_GPIO0 17 272 #define IRQ_RESERVED18 18 273 #define IRQ_RESERVED19 19 274 #define IRQ_RESERVED20 20 275 #define IRQ_OTG 21 276 #define IRQ_RESERVED22 22 277 #define IRQ_AES 23 278 #define IRQ_RESERVED24 24 279 #define IRQ_TCU2 25 280 #define IRQ_TCU1 26 281 #define IRQ_TCU0 27 282 #define IRQ_RESERVED28 28 283 #define IRQ_RESERVED29 29 284 #define IRQ_CIM 30 285 #define IRQ_LCD 31 286 #define IRQ_RTC 32 287 #define IRQ_RESERVED33 33 288 #define IRQ_RESERVED34 34 289 #define IRQ_RESERVED35 35 290 #define IRQ_MSC1 36 291 #define IRQ_MSC0 37 292 #define IRQ_SCC 38 293 #define IRQ_RESERVED39 39 294 #define IRQ_PCM0 40 295 #define IRQ_RESERVED41 41 296 #define IRQ_RESERVED42 42 297 #define IRQ_RESERVED43 43 298 #define IRQ_HARB2 44 299 #define IRQ_RESERVED45 45 300 #define IRQ_HARB0 46 301 #define IRQ_CPM 47 302 #define IRQ_RESERVED48 48 303 #define IRQ_UART2 49 304 #define IRQ_UART1 50 305 #define IRQ_UART0 51 306 #define IRQ_DDR 52 307 #define IRQ_RESERVED53 53 308 #define IRQ_EFUSE 54 309 #define IRQ_MAC 55 310 #define IRQ_RESERVED56 56 311 #define IRQ_RESERVED57 57 312 #define IRQ_I2C2 58 313 #define IRQ_I2C1 59 314 #define IRQ_I2C0 60 315 #define IRQ_PDMAM 61 316 #define IRQ_JPEG 62 317 #define IRQ_RESERVED63 63 318 319 #define IRQ_INTC_MAX 63 320 321 #ifndef __ASSEMBLY__ 322 323 #define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32))) 324 #define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32))) 325 #define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */ 326 327 #endif /* !__ASSEMBLY__ */ 328 329 #endif /* _JZ_M150_H_ */ 330