1*10465441SEvalZero/* 2*10465441SEvalZero * File : mips_excpt_asm.S 3*10465441SEvalZero * This file is part of RT-Thread RTOS 4*10465441SEvalZero * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team 5*10465441SEvalZero * 6*10465441SEvalZero * This program is free software; you can redistribute it and/or modify 7*10465441SEvalZero * it under the terms of the GNU General Public License as published by 8*10465441SEvalZero * the Free Software Foundation; either version 2 of the License, or 9*10465441SEvalZero * (at your option) any later version. 10*10465441SEvalZero * 11*10465441SEvalZero * This program is distributed in the hope that it will be useful, 12*10465441SEvalZero * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*10465441SEvalZero * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*10465441SEvalZero * GNU General Public License for more details. 15*10465441SEvalZero * 16*10465441SEvalZero * You should have received a copy of the GNU General Public License along 17*10465441SEvalZero * with this program; if not, write to the Free Software Foundation, Inc., 18*10465441SEvalZero * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19*10465441SEvalZero * 20*10465441SEvalZero * Change Logs: 21*10465441SEvalZero * Date Author Notes 22*10465441SEvalZero * 2016��9��7�� Urey the first version 23*10465441SEvalZero */ 24*10465441SEvalZero 25*10465441SEvalZero#ifndef __ASSEMBLY__ 26*10465441SEvalZero# define __ASSEMBLY__ 27*10465441SEvalZero#endif 28*10465441SEvalZero 29*10465441SEvalZero#include "../common/mips.h" 30*10465441SEvalZero 31*10465441SEvalZero#define _EXC_STKSIZE 20*1024 32*10465441SEvalZero 33*10465441SEvalZero;/********************************************************************************************************* 34*10465441SEvalZero; PTE BASE ��ض��� 35*10465441SEvalZero;*********************************************************************************************************/ 36*10465441SEvalZero 37*10465441SEvalZero#define PTE_BASE_OFFSET 23 38*10465441SEvalZero#define PTE_BASE_SIZE 9 39*10465441SEvalZero#define MIPS32_BADVPN2_SHIFT 2 40*10465441SEvalZero 41*10465441SEvalZero 42*10465441SEvalZero .section ".text", "ax" 43*10465441SEvalZero .set noreorder 44*10465441SEvalZero 45*10465441SEvalZeroLEAF(mips_tlb_refill_handlerx) 46*10465441SEvalZero .set push 47*10465441SEvalZero .set noat 48*10465441SEvalZero .set noreorder 49*10465441SEvalZero .set volatile 50*10465441SEvalZero 51*10465441SEvalZero ;/* 52*10465441SEvalZero ; * K1 = CP0_CTXT 53*10465441SEvalZero ; * K0 = K1 54*10465441SEvalZero ; */ 55*10465441SEvalZero mfc0 k1 , CP0_CONTEXT ;/* K1 ���� Context �Ĵ��� */ 56*10465441SEvalZero ehb 57*10465441SEvalZero move k0 , k1 ;/* K0 ���� Context �Ĵ��� */ 58*10465441SEvalZero 59*10465441SEvalZero ;/* 60*10465441SEvalZero ; * K1 <<= PTE_BASE_SIZE 61*10465441SEvalZero ; * K1 >>= PTE_BASE_SIZE 62*10465441SEvalZero ; * K1 >>= 4 63*10465441SEvalZero ; * K1 >>= MIPS32_BADVPN2_SHIFT 64*10465441SEvalZero ; * K1 <<= 3 65*10465441SEvalZero ; */ 66*10465441SEvalZero sll k1 , PTE_BASE_SIZE 67*10465441SEvalZero srl k1 , (PTE_BASE_SIZE + 4 + MIPS32_BADVPN2_SHIFT) ;/* K1 Ϊ BAD VPN2 */ 68*10465441SEvalZero sll k1 , (4 - 1) 69*10465441SEvalZero 70*10465441SEvalZero ;/* 71*10465441SEvalZero ; * K0 >>= PTE_BASE_OFFSET 72*10465441SEvalZero ; * K0 <<= PTE_BASE_OFFSET 73*10465441SEvalZero ; */ 74*10465441SEvalZero srl k0 , PTE_BASE_OFFSET 75*10465441SEvalZero sll k0 , PTE_BASE_OFFSET ;/* K0 Ϊ PTE BASE */ 76*10465441SEvalZero 77*10465441SEvalZero ;/* 78*10465441SEvalZero ; * K1 = K1 | K0 79*10465441SEvalZero ; */ 80*10465441SEvalZero or k1 , k1 , k0 ;/* �ϳ� */ 81*10465441SEvalZero 82*10465441SEvalZero ;/* 83*10465441SEvalZero ; * K0 = *K1 84*10465441SEvalZero ; * K1 = *(K1 + 4) 85*10465441SEvalZero ; */ 86*10465441SEvalZero lw k0 , 0(k1) 87*10465441SEvalZero lw k1 , 4(k1) 88*10465441SEvalZero 89*10465441SEvalZero ;/* 90*10465441SEvalZero ; * CP0_TLBLO0 = K0 91*10465441SEvalZero ; * CP0_TLBLO1 = K1 92*10465441SEvalZero ; */ 93*10465441SEvalZero mtc0 k0 , CP0_ENTRYLO0 ;/* EntryLo0 */ 94*10465441SEvalZero mtc0 k1 , CP0_ENTRYLO1 ;/* EntryLo1 */ 95*10465441SEvalZero ehb 96*10465441SEvalZero 97*10465441SEvalZero tlbwr ;/* TLB ����滻 */ 98*10465441SEvalZero 99*10465441SEvalZero eret ;/* �쳣���� */ 100*10465441SEvalZero 101*10465441SEvalZero .set pop 102*10465441SEvalZeroEND(mips_tlb_refill_handlerx) 103