1 /*
2 * Copyright (c) 2006-2018, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2013-07-20 Bernard first version
9 */
10
11 #include <rtthread.h>
12 #include <board.h>
13
14 #include "gic.h"
15 #include "cp15.h"
16
17 struct arm_gic
18 {
19 rt_uint32_t offset;
20
21 rt_uint32_t dist_hw_base;
22 rt_uint32_t cpu_hw_base;
23 };
24 static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
25
26 #define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00)
27 #define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04)
28 #define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08)
29 #define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c)
30 #define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10)
31 #define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14)
32 #define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18)
33
34 #define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000)
35 #define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004)
36 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + (n/32) * 4)
37 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + (n/32) * 4)
38 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + (n/32) * 4)
39 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200)
40 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280)
41 #define GIC_DIST_ACTIVE_BIT(hw_base) __REG32((hw_base) + 0x300)
42 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + (n/4) * 4)
43 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + (n/4) * 4)
44 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + (n/16) * 4)
45 #define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00)
46 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + (n/4) * 4)
47 #define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8)
48
49 static unsigned int _gic_max_irq;
50
arm_gic_get_active_irq(rt_uint32_t index)51 int arm_gic_get_active_irq(rt_uint32_t index)
52 {
53 int irq;
54
55 RT_ASSERT(index < ARM_GIC_MAX_NR);
56
57 irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
58 irq += _gic_table[index].offset;
59 return irq;
60 }
61
arm_gic_ack(rt_uint32_t index,int irq)62 void arm_gic_ack(rt_uint32_t index, int irq)
63 {
64 rt_uint32_t mask = 1 << (irq % 32);
65
66 RT_ASSERT(index < ARM_GIC_MAX_NR);
67
68 irq = irq - _gic_table[index].offset;
69 RT_ASSERT(irq >= 0);
70
71 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
72 GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
73 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
74 }
75
arm_gic_mask(rt_uint32_t index,int irq)76 void arm_gic_mask(rt_uint32_t index, int irq)
77 {
78 rt_uint32_t mask = 1 << (irq % 32);
79
80 RT_ASSERT(index < ARM_GIC_MAX_NR);
81
82 irq = irq - _gic_table[index].offset;
83 RT_ASSERT(irq >= 0);
84
85 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
86 }
87
arm_gic_set_cpu(rt_uint32_t index,int irq,unsigned int cpumask)88 void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
89 {
90 rt_uint32_t old_tgt;
91
92 RT_ASSERT(index < ARM_GIC_MAX_NR);
93
94 irq = irq - _gic_table[index].offset;
95 RT_ASSERT(irq >= 0);
96
97 old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
98
99 old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
100 old_tgt |= cpumask << ((irq % 4)*8);
101
102 GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
103 }
104
arm_gic_umask(rt_uint32_t index,int irq)105 void arm_gic_umask(rt_uint32_t index, int irq)
106 {
107 rt_uint32_t mask = 1 << (irq % 32);
108
109 RT_ASSERT(index < ARM_GIC_MAX_NR);
110
111 irq = irq - _gic_table[index].offset;
112 RT_ASSERT(irq >= 0);
113
114 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
115 }
116
arm_gic_dump_type(rt_uint32_t index)117 void arm_gic_dump_type(rt_uint32_t index)
118 {
119 unsigned int gic_type;
120
121 gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
122 rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
123 (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
124 _gic_table[index].dist_hw_base,
125 _gic_max_irq,
126 gic_type & (1 << 10) ? "has" : "no",
127 gic_type);
128 }
129
arm_gic_dist_init(rt_uint32_t index,rt_uint32_t dist_base,int irq_start)130 int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
131 {
132 unsigned int gic_type, i;
133 rt_uint32_t cpumask = 1 << 0;
134
135 RT_ASSERT(index < ARM_GIC_MAX_NR);
136
137 _gic_table[index].dist_hw_base = dist_base;
138 _gic_table[index].offset = irq_start;
139
140 /* Find out how many interrupts are supported. */
141 gic_type = GIC_DIST_TYPE(dist_base);
142 _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
143
144 /*
145 * The GIC only supports up to 1020 interrupt sources.
146 * Limit this to either the architected maximum, or the
147 * platform maximum.
148 */
149 if (_gic_max_irq > 1020)
150 _gic_max_irq = 1020;
151 if (_gic_max_irq > ARM_GIC_NR_IRQS)
152 _gic_max_irq = ARM_GIC_NR_IRQS;
153
154 cpumask |= cpumask << 8;
155 cpumask |= cpumask << 16;
156
157 GIC_DIST_CTRL(dist_base) = 0x0;
158
159 /* Set all global interrupts to be level triggered, active low. */
160 for (i = 32; i < _gic_max_irq; i += 16)
161 GIC_DIST_CONFIG(dist_base, i) = 0x0;
162
163 /* Set all global interrupts to this CPU only. */
164 for (i = 32; i < _gic_max_irq; i += 4)
165 GIC_DIST_TARGET(dist_base, i) = cpumask;
166
167 /* Set priority on all interrupts. */
168 for (i = 0; i < _gic_max_irq; i += 4)
169 GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
170
171 /* Disable all interrupts. */
172 for (i = 0; i < _gic_max_irq; i += 32)
173 GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
174
175 /* Set the FIQEn bit, signal FIQ for IGROUP0. */
176 GIC_DIST_CTRL(dist_base) = 0x01;
177
178 return 0;
179 }
180
arm_gic_cpu_init(rt_uint32_t index,rt_uint32_t cpu_base)181 int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
182 {
183 RT_ASSERT(index < ARM_GIC_MAX_NR);
184
185 _gic_table[index].cpu_hw_base = cpu_base;
186
187 GIC_CPU_PRIMASK(cpu_base) = 0xf0;
188 /* Enable CPU interrupt */
189 GIC_CPU_CTRL(cpu_base) = 0x01;
190
191 return 0;
192 }
193
arm_gic_set_group(rt_uint32_t index,int vector,int group)194 void arm_gic_set_group(rt_uint32_t index, int vector, int group)
195 {
196 /* As for GICv2, there are only group0 and group1. */
197 RT_ASSERT(group <= 1);
198 RT_ASSERT(vector < _gic_max_irq);
199
200 if (group == 0)
201 {
202 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
203 vector) &= ~(1 << (vector % 32));
204 }
205 else if (group == 1)
206 {
207 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
208 vector) |= (1 << (vector % 32));
209 }
210 }
211
arm_gic_trigger(rt_uint32_t index,int target_cpu,int irq)212 void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq)
213 {
214 unsigned int reg;
215
216 RT_ASSERT(irq <= 15);
217 RT_ASSERT(target_cpu <= 255);
218
219 reg = (target_cpu << 16) | irq;
220 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg;
221 }
222
arm_gic_clear_sgi(rt_uint32_t index,int target_cpu,int irq)223 void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq)
224 {
225 RT_ASSERT(irq <= 15);
226 RT_ASSERT(target_cpu <= 255);
227
228 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4);
229 }
230