1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 */ 9 10 #ifndef __MMU_H__ 11 #define __MMU_H__ 12 13 #include <rtthread.h> 14 15 #define CACHE_LINE_SIZE 32 16 17 /* 18 * Hardware page table definitions. 19 * 20 * + Level 1 descriptor (PGD) 21 * - common 22 */ 23 #define PGD_TYPE_MASK (3 << 0) 24 #define PGD_TYPE_FAULT (0 << 0) 25 #define PGD_TYPE_TABLE (1 << 0) 26 #define PGD_TYPE_SECT (2 << 0) 27 #define PGD_BIT4 (1 << 4) 28 #define PGD_DOMAIN(x) ((x) << 5) 29 #define PGD_PROTECTION (1 << 9) /* ARMv5 */ 30 /* 31 * - section 32 */ 33 #define PGD_SECT_BUFFERABLE (1 << 2) 34 #define PGD_SECT_CACHEABLE (1 << 3) 35 #define PGD_SECT_XN (1 << 4) /* ARMv6 */ 36 #define PGD_SECT_AP0 (1 << 10) 37 #define PGD_SECT_AP1 (1 << 11) 38 #define PGD_SECT_TEX(x) ((x) << 12) /* ARMv5 */ 39 #define PGD_SECT_APX (1 << 15) /* ARMv6 */ 40 #define PGD_SECT_S (1 << 16) /* ARMv6 */ 41 #define PGD_SECT_nG (1 << 17) /* ARMv6 */ 42 #define PGD_SECT_SUPER (1 << 18) /* ARMv6 */ 43 44 #define PGD_SECT_UNCACHED (0) 45 #define PGD_SECT_BUFFERED (PGD_SECT_BUFFERABLE) 46 #define PGD_SECT_WT (PGD_SECT_CACHEABLE) 47 #define PGD_SECT_WB (PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE) 48 #define PGD_SECT_MINICACHE (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE) 49 #define PGD_SECT_WBWA (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE) 50 #define PGD_SECT_NONSHARED_DEV (PGD_SECT_TEX(2)) 51 52 53 /* 54 * + Level 2 descriptor (PTE) 55 * - common 56 */ 57 #define PTE_TYPE_MASK (3 << 0) 58 #define PTE_TYPE_FAULT (0 << 0) 59 #define PTE_TYPE_LARGE (1 << 0) 60 #define PTE_TYPE_SMALL (2 << 0) 61 #define PTE_TYPE_EXT (3 << 0) /* ARMv5 */ 62 #define PTE_BUFFERABLE (1 << 2) 63 #define PTE_CACHEABLE (1 << 3) 64 65 /* 66 * - extended small page/tiny page 67 */ 68 #define PTE_EXT_XN (1 << 0) /* ARMv6 */ 69 #define PTE_EXT_AP_MASK (3 << 4) 70 #define PTE_EXT_AP0 (1 << 4) 71 #define PTE_EXT_AP1 (2 << 4) 72 #define PTE_EXT_AP_UNO_SRO (0 << 4) 73 #define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) 74 #define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) 75 #define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) 76 #define PTE_EXT_TEX(x) ((x) << 6) /* ARMv5 */ 77 #define PTE_EXT_APX (1 << 9) /* ARMv6 */ 78 #define PTE_EXT_SHARED (1 << 10) /* ARMv6 */ 79 #define PTE_EXT_NG (1 << 11) /* ARMv6 */ 80 81 /* 82 * - small page 83 */ 84 #define PTE_SMALL_AP_MASK (0xff << 4) 85 #define PTE_SMALL_AP_UNO_SRO (0x00 << 4) 86 #define PTE_SMALL_AP_UNO_SRW (0x55 << 4) 87 #define PTE_SMALL_AP_URO_SRW (0xaa << 4) 88 #define PTE_SMALL_AP_URW_SRW (0xff << 4) 89 90 /* 91 * sector table properities 92 */ 93 #define SECT_CB (PGD_SECT_CACHEABLE|PGD_SECT_BUFFERABLE) //cache_on, write_back 94 #define SECT_CNB (PGD_SECT_CACHEABLE) //cache_on, write_through 95 #define SECT_NCB (PGD_SECT_BUFFERABLE) //cache_off,WR_BUF on 96 #define SECT_NCNB (0 << 2) //cache_off,WR_BUF off 97 98 #define SECT_AP_RW (PGD_SECT_AP0|PGD_SECT_AP1) //supervisor=RW, user=RW 99 #define SECT_AP_RO ((0 << 10)|(0 << 11)) //supervisor=RO, user=NO Access(SR=10) 100 101 #define SECT_RW_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write back */ 102 #define SECT_RW_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write through */ 103 #define SECT_RW_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */ 104 #define SECT_RW_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */ 105 106 #define SECT_RO_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write back */ 107 #define SECT_RO_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write through */ 108 #define SECT_RO_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */ 109 #define SECT_RO_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */ 110 111 #define SECT_TO_PAGE (PGD_DOMAIN(0)|PGD_TYPE_TABLE|PGD_BIT4) /* Level 2 descriptor (PTE) entry properity */ 112 113 /* 114 * page table properities 115 */ 116 #define PAGE_CB (PTE_BUFFERABLE|PTE_CACHEABLE) //cache_on, write_back 117 #define PAGE_CNB (PTE_CACHEABLE) //cache_on, write_through 118 #define PAGE_NCB (PTE_BUFFERABLE) //cache_off,WR_BUF on 119 #define PAGE_NCNB (0 << 2) //cache_off,WR_BUF off 120 121 #define PAGE_AP_RW PTE_SMALL_AP_URW_SRW //supervisor=RW, user=RW 122 #define PAGE_AP_RO PTE_SMALL_AP_UNO_SRO //supervisor=RO, user=NO Access(SR=10) 123 124 #define PAGE_RW_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL) /* Read/Write, cache, write back */ 125 #define PAGE_RW_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL) /* Read/Write, cache, write through */ 126 #define PAGE_RW_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */ 127 #define PAGE_RW_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */ 128 129 130 #define PAGE_RO_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL) /* Read Only, cache, write back */ 131 #define PAGE_RO_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL) /* Read Only, cache, write through */ 132 #define PAGE_RO_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ 133 #define PAGE_RO_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ 134 135 struct mem_desc { 136 rt_uint32_t vaddr_start; 137 rt_uint32_t vaddr_end; 138 rt_uint32_t paddr_start; 139 rt_uint32_t sect_attr; /* when page mapped */ 140 rt_uint32_t page_attr; /* only sector mapped valid */ 141 rt_uint32_t mapped_mode; 142 #define SECT_MAPPED 0 143 #define PAGE_MAPPED 1 144 }; 145 146 147 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); 148 149 #endif 150 151