1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 */ 9 10 #ifndef __ARMV6_H__ 11 #define __ARMV6_H__ 12 13 14 /*****************************/ 15 /* CPU Mode */ 16 /*****************************/ 17 #define USERMODE 0x10 18 #define FIQMODE 0x11 19 #define IRQMODE 0x12 20 #define SVCMODE 0x13 21 #define ABORTMODE 0x17 22 #define UNDEFMODE 0x1b 23 #define MODEMASK 0x1f 24 #define NOINT 0xc0 25 26 #ifndef __ASSEMBLY__ 27 struct rt_hw_register 28 { 29 rt_uint32_t cpsr; 30 rt_uint32_t r0; 31 rt_uint32_t r1; 32 rt_uint32_t r2; 33 rt_uint32_t r3; 34 rt_uint32_t r4; 35 rt_uint32_t r5; 36 rt_uint32_t r6; 37 rt_uint32_t r7; 38 rt_uint32_t r8; 39 rt_uint32_t r9; 40 rt_uint32_t r10; 41 rt_uint32_t fp; 42 rt_uint32_t ip; 43 rt_uint32_t sp; 44 rt_uint32_t lr; 45 rt_uint32_t pc; 46 }; 47 #if(0) 48 struct rt_hw_register{ 49 rt_uint32_t r0; 50 rt_uint32_t r1; 51 rt_uint32_t r2; 52 rt_uint32_t r3; 53 rt_uint32_t r4; 54 rt_uint32_t r5; 55 rt_uint32_t r6; 56 rt_uint32_t r7; 57 rt_uint32_t r8; 58 rt_uint32_t r9; 59 rt_uint32_t r10; 60 rt_uint32_t fp; 61 rt_uint32_t ip; 62 rt_uint32_t sp; 63 rt_uint32_t lr; 64 rt_uint32_t pc; 65 rt_uint32_t cpsr; 66 rt_uint32_t ORIG_r0; 67 }; 68 #endif 69 #endif 70 71 /* rt_hw_register offset */ 72 #define S_FRAME_SIZE 68 73 74 #define S_PC 64 75 #define S_LR 60 76 #define S_SP 56 77 #define S_IP 52 78 #define S_FP 48 79 #define S_R10 44 80 #define S_R9 40 81 #define S_R8 36 82 #define S_R7 32 83 #define S_R6 28 84 #define S_R5 24 85 #define S_R4 20 86 #define S_R3 16 87 #define S_R2 12 88 #define S_R1 8 89 #define S_R0 4 90 #define S_CPSR 0 91 92 93 #endif 94