xref: /nrf52832-nimble/rt-thread/libcpu/arm/arm926/context_gcc.S (revision 104654410c56c573564690304ae786df310c91fc)
1*10465441SEvalZero;/*
2*10465441SEvalZero; * Copyright (c) 2006-2018, RT-Thread Development Team
3*10465441SEvalZero; *
4*10465441SEvalZero; * SPDX-License-Identifier: Apache-2.0
5*10465441SEvalZero; *
6*10465441SEvalZero; * Change Logs:
7*10465441SEvalZero; * Date           Author       Notes
8*10465441SEvalZero; * 2011-08-14     weety    copy from mini2440
9*10465441SEvalZero; */
10*10465441SEvalZero
11*10465441SEvalZero#define NOINT   0xC0
12*10465441SEvalZero
13*10465441SEvalZero;/*
14*10465441SEvalZero; * rt_base_t rt_hw_interrupt_disable();
15*10465441SEvalZero; */
16*10465441SEvalZero    .globl rt_hw_interrupt_disable
17*10465441SEvalZerort_hw_interrupt_disable:
18*10465441SEvalZero    MRS     R0, CPSR
19*10465441SEvalZero    ORR     R1, R0, #NOINT
20*10465441SEvalZero    MSR     CPSR_c, R1
21*10465441SEvalZero    BX      LR
22*10465441SEvalZero
23*10465441SEvalZero/*
24*10465441SEvalZero * void rt_hw_interrupt_enable(rt_base_t level);
25*10465441SEvalZero */
26*10465441SEvalZero    .globl rt_hw_interrupt_enable
27*10465441SEvalZerort_hw_interrupt_enable:
28*10465441SEvalZero    MSR     CPSR, R0
29*10465441SEvalZero    BX      LR
30*10465441SEvalZero
31*10465441SEvalZero/*
32*10465441SEvalZero * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
33*10465441SEvalZero * r0 --> from
34*10465441SEvalZero * r1 --> to
35*10465441SEvalZero */
36*10465441SEvalZero    .globl rt_hw_context_switch
37*10465441SEvalZerort_hw_context_switch:
38*10465441SEvalZero    STMFD   SP!, {LR}           @; push pc (lr should be pushed in place of pc)
39*10465441SEvalZero    STMFD   SP!, {R0-R12, LR}       @; push lr & register file
40*10465441SEvalZero    MRS     R4, CPSR
41*10465441SEvalZero    STMFD   SP!, {R4}               @; push cpsr
42*10465441SEvalZero    STR     SP, [R0]                @; store sp in preempted tasks tcb
43*10465441SEvalZero    LDR     SP, [R1]                @; get new task stack pointer
44*10465441SEvalZero    LDMFD   SP!, {R4}               @; pop new task spsr
45*10465441SEvalZero    MSR     SPSR_cxsf, R4
46*10465441SEvalZero    LDMFD   SP!, {R0-R12, LR, PC}^  @; pop new task r0-r12, lr & pc
47*10465441SEvalZero
48*10465441SEvalZero/*
49*10465441SEvalZero * void rt_hw_context_switch_to(rt_uint32 to);
50*10465441SEvalZero * r0 --> to
51*10465441SEvalZero */
52*10465441SEvalZero    .globl rt_hw_context_switch_to
53*10465441SEvalZerort_hw_context_switch_to:
54*10465441SEvalZero    LDR     SP, [R0]                @; get new task stack pointer
55*10465441SEvalZero    LDMFD   SP!, {R4}               @; pop new task cpsr
56*10465441SEvalZero    MSR     SPSR_cxsf, R4
57*10465441SEvalZero    LDMFD   SP!, {R0-R12, LR, PC}^  @; pop new task r0-r12, lr & pc
58*10465441SEvalZero
59*10465441SEvalZero/*
60*10465441SEvalZero * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
61*10465441SEvalZero */
62*10465441SEvalZero    .globl rt_thread_switch_interrupt_flag
63*10465441SEvalZero    .globl rt_interrupt_from_thread
64*10465441SEvalZero    .globl rt_interrupt_to_thread
65*10465441SEvalZero    .globl rt_hw_context_switch_interrupt
66*10465441SEvalZerort_hw_context_switch_interrupt:
67*10465441SEvalZero    LDR     R2, =rt_thread_switch_interrupt_flag
68*10465441SEvalZero    LDR     R3, [R2]
69*10465441SEvalZero    CMP     R3, #1
70*10465441SEvalZero    BEQ     _reswitch
71*10465441SEvalZero    MOV     R3, #1                          @; set flag to 1
72*10465441SEvalZero    STR     R3, [R2]
73*10465441SEvalZero    LDR     R2, =rt_interrupt_from_thread   @; set rt_interrupt_from_thread
74*10465441SEvalZero    STR     R0, [R2]
75*10465441SEvalZero_reswitch:
76*10465441SEvalZero    LDR     R2, =rt_interrupt_to_thread     @; set rt_interrupt_to_thread
77*10465441SEvalZero    STR     R1, [R2]
78*10465441SEvalZero    BX      LR
79