1/* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2015-04-06 zchong change to iar compiler from convert from cp15_gcc.S 9 */ 10 11 SECTION .text:CODE:NOROOT(2) 12 13 ARM 14 15 EXPORT rt_cpu_vector_set_base 16rt_cpu_vector_set_base: 17 MCR p15, #0, r0, c12, c0, #0 18 DSB 19 BX lr 20 21 EXPORT rt_cpu_vector_get_base 22rt_cpu_vector_get_base: 23 MRC p15, #0, r0, c12, c0, #0 24 BX lr 25 26 EXPORT rt_cpu_get_sctlr 27rt_cpu_get_sctlr: 28 MRC p15, #0, r0, c1, c0, #0 29 BX lr 30 31 EXPORT rt_cpu_dcache_enable 32rt_cpu_dcache_enable: 33 MRC p15, #0, r0, c1, c0, #0 34 ORR r0, r0, #0x00000004 35 MCR p15, #0, r0, c1, c0, #0 36 BX lr 37 38 EXPORT rt_cpu_icache_enable 39rt_cpu_icache_enable: 40 MRC p15, #0, r0, c1, c0, #0 41 ORR r0, r0, #0x00001000 42 MCR p15, #0, r0, c1, c0, #0 43 BX lr 44 45;_FLD_MAX_WAY DEFINE 0x3ff 46;_FLD_MAX_IDX DEFINE 0x7ff 47 48 49 EXPORT rt_cpu_dcache_clean_flush 50rt_cpu_dcache_clean_flush: 51 PUSH {r4-r11} 52 DMB 53 MRC p15, #1, r0, c0, c0, #1 ; read clid register 54 ANDS r3, r0, #0x7000000 ; get level of coherency 55 MOV r3, r3, lsr #23 56 BEQ finished 57 MOV r10, #0 58loop1: 59 ADD r2, r10, r10, lsr #1 60 MOV r1, r0, lsr r2 61 AND r1, r1, #7 62 CMP r1, #2 63 BLT skip 64 MCR p15, #2, r10, c0, c0, #0 65 ISB 66 MRC p15, #1, r1, c0, c0, #0 67 AND r2, r1, #7 68 ADD r2, r2, #4 69 ;LDR r4, _FLD_MAX_WAY 70 LDR r4, =0x3FF 71 ANDS r4, r4, r1, lsr #3 72 CLZ r5, r4 73 ;LDR r7, _FLD_MAX_IDX 74 LDR r7, =0x7FF 75 ANDS r7, r7, r1, lsr #13 76loop2: 77 MOV r9, r4 78loop3: 79 ORR r11, r10, r9, lsl r5 80 ORR r11, r11, r7, lsl r2 81 MCR p15, #0, r11, c7, c14, #2 82 SUBS r9, r9, #1 83 BGE loop3 84 SUBS r7, r7, #1 85 BGE loop2 86skip: 87 ADD r10, r10, #2 88 CMP r3, r10 89 BGT loop1 90 91finished: 92 DSB 93 ISB 94 POP {r4-r11} 95 BX lr 96 97 98 EXPORT rt_cpu_dcache_disable 99rt_cpu_dcache_disable: 100 PUSH {r4-r11, lr} 101 MRC p15, #0, r0, c1, c0, #0 102 BIC r0, r0, #0x00000004 103 MCR p15, #0, r0, c1, c0, #0 104 BL rt_cpu_dcache_clean_flush 105 POP {r4-r11, lr} 106 BX lr 107 108 109 EXPORT rt_cpu_icache_disable 110rt_cpu_icache_disable: 111 MRC p15, #0, r0, c1, c0, #0 112 BIC r0, r0, #0x00001000 113 MCR p15, #0, r0, c1, c0, #0 114 BX lr 115 116 EXPORT rt_cpu_mmu_disable 117rt_cpu_mmu_disable: 118 MCR p15, #0, r0, c8, c7, #0 ; invalidate tlb 119 MRC p15, #0, r0, c1, c0, #0 120 BIC r0, r0, #1 121 MCR p15, #0, r0, c1, c0, #0 ; clear mmu bit 122 DSB 123 BX lr 124 125 EXPORT rt_cpu_mmu_enable 126rt_cpu_mmu_enable: 127 MRC p15, #0, r0, c1, c0, #0 128 ORR r0, r0, #0x001 129 MCR p15, #0, r0, c1, c0, #0 ; set mmu enable bit 130 DSB 131 BX lr 132 133 EXPORT rt_cpu_tlb_set 134rt_cpu_tlb_set: 135 MCR p15, #0, r0, c2, c0, #0 136 DMB 137 BX lr 138 139 END 140