1 /* 2 * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef NRF_SPIS_H__ 33 #define NRF_SPIS_H__ 34 35 #include <nrfx.h> 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 /** 42 * @defgroup nrf_spis_hal SPIS HAL 43 * @{ 44 * @ingroup nrf_spis 45 * @brief Hardware access layer for managing the SPIS peripheral. 46 */ 47 48 /** 49 * @brief This value can be used as a parameter for the @ref nrf_spis_pins_set 50 * function to specify that a given SPI signal (SCK, MOSI, or MISO) 51 * shall not be connected to a physical pin. 52 */ 53 #define NRF_SPIS_PIN_NOT_CONNECTED 0xFFFFFFFF 54 55 56 /** 57 * @brief SPIS tasks. 58 */ 59 typedef enum 60 { 61 /*lint -save -e30*/ 62 NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore. 63 NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it. 64 /*lint -restore*/ 65 } nrf_spis_task_t; 66 67 /** 68 * @brief SPIS events. 69 */ 70 typedef enum 71 { 72 /*lint -save -e30*/ 73 NRF_SPIS_EVENT_END = offsetof(NRF_SPIS_Type, EVENTS_END), ///< Granted transaction completed. 74 NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired. 75 /*lint -restore*/ 76 } nrf_spis_event_t; 77 78 /** 79 * @brief SPIS shortcuts. 80 */ 81 typedef enum 82 { 83 NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk ///< Shortcut between END event and ACQUIRE task. 84 } nrf_spis_short_mask_t; 85 86 /** 87 * @brief SPIS interrupts. 88 */ 89 typedef enum 90 { 91 NRF_SPIS_INT_END_MASK = SPIS_INTENSET_END_Msk, ///< Interrupt on END event. 92 NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk ///< Interrupt on ACQUIRED event. 93 } nrf_spis_int_mask_t; 94 95 /** 96 * @brief SPI modes. 97 */ 98 typedef enum 99 { 100 NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock. 101 NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock. 102 NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock. 103 NRF_SPIS_MODE_3 ///< SCK active low, sample on trailing edge of clock. 104 } nrf_spis_mode_t; 105 106 /** 107 * @brief SPI bit orders. 108 */ 109 typedef enum 110 { 111 NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. 112 NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. 113 } nrf_spis_bit_order_t; 114 115 /** 116 * @brief SPI semaphore status. 117 */ 118 typedef enum 119 { 120 NRF_SPIS_SEMSTAT_FREE = 0, ///< Semaphore is free. 121 NRF_SPIS_SEMSTAT_CPU = 1, ///< Semaphore is assigned to the CPU. 122 NRF_SPIS_SEMSTAT_SPIS = 2, ///< Semaphore is assigned to the SPI slave. 123 NRF_SPIS_SEMSTAT_CPUPENDING = 3 ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending. 124 } nrf_spis_semstat_t; 125 126 /** 127 * @brief SPIS status. 128 */ 129 typedef enum 130 { 131 NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented. 132 NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk ///< RX buffer overflow detected and prevented. 133 } nrf_spis_status_mask_t; 134 135 /** 136 * @brief Function for activating a specific SPIS task. 137 * 138 * @param[in] p_reg Pointer to the peripheral registers structure. 139 * @param[in] spis_task Task to activate. 140 */ 141 __STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg, 142 nrf_spis_task_t spis_task); 143 144 /** 145 * @brief Function for getting the address of a specific SPIS task register. 146 * 147 * @param[in] p_reg Pointer to the peripheral registers structure. 148 * @param[in] spis_task Requested task. 149 * 150 * @return Address of the specified task register. 151 */ 152 __STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg, 153 nrf_spis_task_t spis_task); 154 155 /** 156 * @brief Function for clearing a specific SPIS event. 157 * 158 * @param[in] p_reg Pointer to the peripheral registers structure. 159 * @param[in] spis_event Event to clear. 160 */ 161 __STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg, 162 nrf_spis_event_t spis_event); 163 164 /** 165 * @brief Function for checking the state of a specific SPIS event. 166 * 167 * @param[in] p_reg Pointer to the peripheral registers structure. 168 * @param[in] spis_event Event to check. 169 * 170 * @retval true If the event is set. 171 * @retval false If the event is not set. 172 */ 173 __STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg, 174 nrf_spis_event_t spis_event); 175 176 /** 177 * @brief Function for getting the address of a specific SPIS event register. 178 * 179 * @param[in] p_reg Pointer to the peripheral registers structure. 180 * @param[in] spis_event Requested event. 181 * 182 * @return Address of the specified event register. 183 */ 184 __STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg, 185 nrf_spis_event_t spis_event); 186 187 /** 188 * @brief Function for enabling specified shortcuts. 189 * 190 * @param[in] p_reg Pointer to the peripheral registers structure. 191 * @param[in] spis_shorts_mask Shortcuts to enable. 192 */ 193 __STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg, 194 uint32_t spis_shorts_mask); 195 196 /** 197 * @brief Function for disabling specified shortcuts. 198 * 199 * @param[in] p_reg Pointer to the peripheral registers structure. 200 * @param[in] spis_shorts_mask Shortcuts to disable. 201 */ 202 __STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg, 203 uint32_t spis_shorts_mask); 204 205 /** 206 * @brief Function for enabling specified interrupts. 207 * 208 * @param[in] p_reg Pointer to the peripheral registers structure. 209 * @param[in] spis_int_mask Interrupts to enable. 210 */ 211 __STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg, 212 uint32_t spis_int_mask); 213 214 /** 215 * @brief Function for disabling specified interrupts. 216 * 217 * @param[in] p_reg Pointer to the peripheral registers structure. 218 * @param[in] spis_int_mask Interrupts to disable. 219 */ 220 __STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg, 221 uint32_t spis_int_mask); 222 223 /** 224 * @brief Function for retrieving the state of a given interrupt. 225 * 226 * @param[in] p_reg Pointer to the peripheral registers structure. 227 * @param[in] spis_int Interrupt to check. 228 * 229 * @retval true If the interrupt is enabled. 230 * @retval false If the interrupt is not enabled. 231 */ 232 __STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg, 233 nrf_spis_int_mask_t spis_int); 234 235 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) 236 /** 237 * @brief Function for setting the subscribe configuration for a given 238 * SPIS task. 239 * 240 * @param[in] p_reg Pointer to the structure of registers of the peripheral. 241 * @param[in] task Task for which to set the configuration. 242 * @param[in] channel Channel through which to subscribe events. 243 */ 244 __STATIC_INLINE void nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg, 245 nrf_spis_task_t task, 246 uint8_t channel); 247 248 /** 249 * @brief Function for clearing the subscribe configuration for a given 250 * SPIS task. 251 * 252 * @param[in] p_reg Pointer to the structure of registers of the peripheral. 253 * @param[in] task Task for which to clear the configuration. 254 */ 255 __STATIC_INLINE void nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg, 256 nrf_spis_task_t task); 257 258 /** 259 * @brief Function for setting the publish configuration for a given 260 * SPIS event. 261 * 262 * @param[in] p_reg Pointer to the structure of registers of the peripheral. 263 * @param[in] event Event for which to set the configuration. 264 * @param[in] channel Channel through which to publish the event. 265 */ 266 __STATIC_INLINE void nrf_spis_publish_set(NRF_SPIS_Type * p_reg, 267 nrf_spis_event_t event, 268 uint8_t channel); 269 270 /** 271 * @brief Function for clearing the publish configuration for a given 272 * SPIS event. 273 * 274 * @param[in] p_reg Pointer to the structure of registers of the peripheral. 275 * @param[in] event Event for which to clear the configuration. 276 */ 277 __STATIC_INLINE void nrf_spis_publish_clear(NRF_SPIS_Type * p_reg, 278 nrf_spis_event_t event); 279 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) 280 281 /** 282 * @brief Function for enabling the SPIS peripheral. 283 * 284 * @param[in] p_reg Pointer to the peripheral registers structure. 285 */ 286 __STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg); 287 288 /** 289 * @brief Function for disabling the SPIS peripheral. 290 * 291 * @param[in] p_reg Pointer to the peripheral registers structure. 292 */ 293 __STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg); 294 295 /** 296 * @brief Function for retrieving the SPIS semaphore status. 297 * 298 * @param[in] p_reg Pointer to the peripheral registers structure. 299 * 300 * @returns Current semaphore status. 301 */ 302 __STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg); 303 304 /** 305 * @brief Function for retrieving the SPIS status. 306 * 307 * @param[in] p_reg Pointer to the peripheral registers structure. 308 * 309 * @returns Current SPIS status. 310 */ 311 __STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg); 312 313 /** 314 * @brief Function for configuring SPIS pins. 315 * 316 * If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED 317 * value instead of its pin number. 318 * 319 * @param[in] p_reg Pointer to the peripheral registers structure. 320 * @param[in] sck_pin SCK pin number. 321 * @param[in] mosi_pin MOSI pin number. 322 * @param[in] miso_pin MISO pin number. 323 * @param[in] csn_pin CSN pin number. 324 */ 325 __STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg, 326 uint32_t sck_pin, 327 uint32_t mosi_pin, 328 uint32_t miso_pin, 329 uint32_t csn_pin); 330 331 /** 332 * @brief Function for setting the transmit buffer. 333 * 334 * @param[in] p_reg Pointer to the peripheral registers structure. 335 * @param[in] p_buffer Pointer to the buffer that contains the data to send. 336 * @param[in] length Maximum number of data bytes to transmit. 337 */ 338 __STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg, 339 uint8_t const * p_buffer, 340 size_t length); 341 342 /** 343 * @brief Function for setting the receive buffer. 344 * 345 * @param[in] p_reg Pointer to the peripheral registers structure. 346 * @param[in] p_buffer Pointer to the buffer for received data. 347 * @param[in] length Maximum number of data bytes to receive. 348 */ 349 __STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg, 350 uint8_t * p_buffer, 351 size_t length); 352 353 /** 354 * @brief Function for getting the number of bytes transmitted 355 * in the last granted transaction. 356 * 357 * @param[in] p_reg Pointer to the peripheral registers structure. 358 * 359 * @returns Number of bytes transmitted. 360 */ 361 __STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg); 362 363 /** 364 * @brief Function for getting the number of bytes received 365 * in the last granted transaction. 366 * 367 * @param[in] p_reg Pointer to the peripheral registers structure. 368 * 369 * @returns Number of bytes received. 370 */ 371 __STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg); 372 373 /** 374 * @brief Function for setting the SPI configuration. 375 * 376 * @param[in] p_reg Pointer to the peripheral registers structure. 377 * @param[in] spi_mode SPI mode. 378 * @param[in] spi_bit_order SPI bit order. 379 */ 380 __STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg, 381 nrf_spis_mode_t spi_mode, 382 nrf_spis_bit_order_t spi_bit_order); 383 384 /** 385 * @brief Function for setting the default character. 386 * 387 * @param[in] p_reg Pointer to the peripheral registers structure. 388 * @param[in] def Default character that is clocked out in case of 389 * an overflow of the RXD buffer. 390 */ 391 __STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg, 392 uint8_t def); 393 394 /** 395 * @brief Function for setting the over-read character. 396 * 397 * @param[in] p_reg Pointer to the peripheral registers structure. 398 * @param[in] orc Over-read character that is clocked out in case of 399 * an over-read of the TXD buffer. 400 */ 401 __STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg, 402 uint8_t orc); 403 404 405 #ifndef SUPPRESS_INLINE_IMPLEMENTATION 406 407 __STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg, 408 nrf_spis_task_t spis_task) 409 { 410 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_task)) = 0x1UL; 411 } 412 413 __STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg, 414 nrf_spis_task_t spis_task) 415 { 416 return (uint32_t)p_reg + (uint32_t)spis_task; 417 } 418 419 __STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg, 420 nrf_spis_event_t spis_event) 421 { 422 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event)) = 0x0UL; 423 #if __CORTEX_M == 0x04 424 volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event)); 425 (void)dummy; 426 #endif 427 } 428 429 __STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg, 430 nrf_spis_event_t spis_event) 431 { 432 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event); 433 } 434 435 __STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg, 436 nrf_spis_event_t spis_event) 437 { 438 return (uint32_t)p_reg + (uint32_t)spis_event; 439 } 440 441 __STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg, 442 uint32_t spis_shorts_mask) 443 { 444 p_reg->SHORTS |= spis_shorts_mask; 445 } 446 447 __STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg, 448 uint32_t spis_shorts_mask) 449 { 450 p_reg->SHORTS &= ~(spis_shorts_mask); 451 } 452 453 __STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg, 454 uint32_t spis_int_mask) 455 { 456 p_reg->INTENSET = spis_int_mask; 457 } 458 459 __STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg, 460 uint32_t spis_int_mask) 461 { 462 p_reg->INTENCLR = spis_int_mask; 463 } 464 465 __STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg, 466 nrf_spis_int_mask_t spis_int) 467 { 468 return (bool)(p_reg->INTENSET & spis_int); 469 } 470 471 #if defined(DPPI_PRESENT) 472 __STATIC_INLINE void nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg, 473 nrf_spis_task_t task, 474 uint8_t channel) 475 { 476 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 477 ((uint32_t)channel | SPIS_SUBSCRIBE_ACQUIRE_EN_Msk); 478 } 479 480 __STATIC_INLINE void nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg, 481 nrf_spis_task_t task) 482 { 483 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0; 484 } 485 486 __STATIC_INLINE void nrf_spis_publish_set(NRF_SPIS_Type * p_reg, 487 nrf_spis_event_t event, 488 uint8_t channel) 489 { 490 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 491 ((uint32_t)channel | SPIS_PUBLISH_END_EN_Msk); 492 } 493 494 __STATIC_INLINE void nrf_spis_publish_clear(NRF_SPIS_Type * p_reg, 495 nrf_spis_event_t event) 496 { 497 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0; 498 } 499 #endif // defined(DPPI_PRESENT) 500 501 __STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg) 502 { 503 p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos); 504 } 505 506 __STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg) 507 { 508 p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos); 509 } 510 511 __STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg) 512 { 513 return (nrf_spis_semstat_t) ((p_reg->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk) 514 >> SPIS_SEMSTAT_SEMSTAT_Pos); 515 } 516 517 __STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg) 518 { 519 return (nrf_spis_status_mask_t) p_reg->STATUS; 520 } 521 522 __STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg, 523 uint32_t sck_pin, 524 uint32_t mosi_pin, 525 uint32_t miso_pin, 526 uint32_t csn_pin) 527 { 528 #if defined (NRF51) 529 p_reg->PSELSCK = sck_pin; 530 p_reg->PSELMOSI = mosi_pin; 531 p_reg->PSELMISO = miso_pin; 532 p_reg->PSELCSN = csn_pin; 533 #else 534 p_reg->PSEL.SCK = sck_pin; 535 p_reg->PSEL.MOSI = mosi_pin; 536 p_reg->PSEL.MISO = miso_pin; 537 p_reg->PSEL.CSN = csn_pin; 538 #endif 539 } 540 541 __STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg, 542 uint8_t const * p_buffer, 543 size_t length) 544 { 545 #if defined (NRF51) 546 p_reg->TXDPTR = (uint32_t)p_buffer; 547 p_reg->MAXTX = length; 548 #else 549 p_reg->TXD.PTR = (uint32_t)p_buffer; 550 p_reg->TXD.MAXCNT = length; 551 #endif 552 } 553 554 __STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg, 555 uint8_t * p_buffer, 556 size_t length) 557 { 558 #if defined (NRF51) 559 p_reg->RXDPTR = (uint32_t)p_buffer; 560 p_reg->MAXRX = length; 561 #else 562 p_reg->RXD.PTR = (uint32_t)p_buffer; 563 p_reg->RXD.MAXCNT = length; 564 #endif 565 } 566 567 __STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg) 568 { 569 #if defined (NRF51) 570 return p_reg->AMOUNTTX; 571 #else 572 return p_reg->TXD.AMOUNT; 573 #endif 574 } 575 576 __STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg) 577 { 578 #if defined (NRF51) 579 return p_reg->AMOUNTRX; 580 #else 581 return p_reg->RXD.AMOUNT; 582 #endif 583 } 584 585 __STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg, 586 nrf_spis_mode_t spi_mode, 587 nrf_spis_bit_order_t spi_bit_order) 588 { 589 uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ? 590 SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst); 591 592 switch (spi_mode) 593 { 594 default: 595 case NRF_SPIS_MODE_0: 596 config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | 597 (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); 598 break; 599 600 case NRF_SPIS_MODE_1: 601 config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | 602 (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); 603 break; 604 605 case NRF_SPIS_MODE_2: 606 config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | 607 (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); 608 break; 609 610 case NRF_SPIS_MODE_3: 611 config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | 612 (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); 613 break; 614 } 615 p_reg->CONFIG = config; 616 } 617 618 __STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg, 619 uint8_t orc) 620 { 621 p_reg->ORC = orc; 622 } 623 624 __STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg, 625 uint8_t def) 626 { 627 p_reg->DEF = def; 628 } 629 630 #endif // SUPPRESS_INLINE_IMPLEMENTATION 631 632 /** @} */ 633 634 #ifdef __cplusplus 635 } 636 #endif 637 638 #endif // NRF_SPIS_H__ 639