1 /* --COPYRIGHT--,BSD 2 * Copyright (c) 2017, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * --/COPYRIGHT--*/ 32 #include <ti/devices/msp432p4xx/driverlib/aes256.h> 33 #include <ti/devices/msp432p4xx/driverlib/interrupt.h> 34 #include <ti/devices/msp432p4xx/driverlib/debug.h> 35 36 bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey, 37 uint_fast16_t keyLength) 38 { 39 uint_fast8_t i; 40 uint16_t sCipherKey; 41 42 AES256_CMSIS(moduleInstance)->CTL0 |= 0; 43 44 switch (keyLength) 45 { 46 case AES256_KEYLENGTH_128BIT: 47 AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT; 48 break; 49 50 case AES256_KEYLENGTH_192BIT: 51 AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT; 52 break; 53 54 case AES256_KEYLENGTH_256BIT: 55 AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT; 56 break; 57 default: 58 return false; 59 } 60 61 keyLength = keyLength / 8; 62 63 for (i = 0; i < keyLength; i = i + 2) 64 { 65 sCipherKey = (uint16_t) (cipherKey[i]); 66 sCipherKey = sCipherKey | ((uint16_t) (cipherKey[i + 1]) << 8); 67 AES256_CMSIS(moduleInstance)->KEY = sCipherKey; 68 } 69 70 // Wait until key is written 71 while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS)) 72 ; 73 74 return true; 75 } 76 77 void AES256_encryptData(uint32_t moduleInstance, const uint8_t * data, 78 uint8_t * encryptedData) 79 { 80 uint_fast8_t i; 81 uint16_t tempData = 0; 82 uint16_t tempVariable = 0; 83 84 // Set module to encrypt mode 85 AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK; 86 87 // Write data to encrypt to module 88 for (i = 0; i < 16; i = i + 2) 89 { 90 tempVariable = (uint16_t) (data[i]); 91 tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8); 92 AES256_CMSIS(moduleInstance)->DIN = tempVariable; 93 } 94 95 // Key that is already written shall be used 96 // Encryption is initialized by setting AES256_STAT_KEYWR to 1 97 BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1; 98 99 // Wait unit finished ~167 MCLK 100 while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS)) 101 ; 102 103 // Write encrypted data back to variable 104 for (i = 0; i < 16; i = i + 2) 105 { 106 tempData = AES256_CMSIS(moduleInstance)->DOUT; 107 *(encryptedData + i) = (uint8_t) tempData; 108 *(encryptedData + i + 1) = (uint8_t) (tempData >> 8); 109 } 110 } 111 112 void AES256_decryptData(uint32_t moduleInstance, const uint8_t * data, 113 uint8_t * decryptedData) 114 { 115 uint_fast8_t i; 116 uint16_t tempData = 0; 117 uint16_t tempVariable = 0; 118 119 // Set module to decrypt mode 120 AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3); 121 122 // Write data to decrypt to module 123 for (i = 0; i < 16; i = i + 2) 124 { 125 tempVariable = (uint16_t) (data[i + 1] << 8); 126 tempVariable = tempVariable | ((uint16_t) (data[i])); 127 AES256_CMSIS(moduleInstance)->DIN = tempVariable; 128 } 129 130 // Key that is already written shall be used 131 // Now decryption starts 132 BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1; 133 134 // Wait unit finished ~167 MCLK 135 while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS)) 136 ; 137 138 // Write encrypted data back to variable 139 for (i = 0; i < 16; i = i + 2) 140 { 141 tempData = AES256_CMSIS(moduleInstance)->DOUT; 142 *(decryptedData + i) = (uint8_t) tempData; 143 *(decryptedData + i + 1) = (uint8_t) (tempData >> 8); 144 } 145 } 146 147 bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey, 148 uint_fast16_t keyLength) 149 { 150 uint8_t i; 151 uint16_t tempVariable = 0; 152 153 // Set module to decrypt mode 154 AES256_CMSIS(moduleInstance)->CTL0 = 155 (AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1; 156 157 switch (keyLength) 158 { 159 case AES256_KEYLENGTH_128BIT: 160 AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT; 161 break; 162 163 case AES256_KEYLENGTH_192BIT: 164 AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT; 165 break; 166 167 case AES256_KEYLENGTH_256BIT: 168 AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT; 169 break; 170 171 default: 172 return false; 173 } 174 175 keyLength = keyLength / 8; 176 177 // Write cipher key to key register 178 for (i = 0; i < keyLength; i = i + 2) 179 { 180 tempVariable = (uint16_t) (cipherKey[i]); 181 tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8); 182 AES256_CMSIS(moduleInstance)->KEY = tempVariable; 183 } 184 185 // Wait until key is processed ~52 MCLK 186 while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS)) 187 ; 188 189 return true; 190 } 191 192 void AES256_clearInterruptFlag(uint32_t moduleInstance) 193 { 194 BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIFG_OFS) = 0; 195 } 196 197 uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance) 198 { 199 return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_RDYIFG_OFS); 200 } 201 202 void AES256_enableInterrupt(uint32_t moduleInstance) 203 { 204 BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 1; 205 } 206 207 void AES256_disableInterrupt(uint32_t moduleInstance) 208 { 209 BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 0; 210 } 211 212 void AES256_reset(uint32_t moduleInstance) 213 { 214 BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_SWRST_OFS) = 1; 215 } 216 217 void AES256_startEncryptData(uint32_t moduleInstance, const uint8_t * data) 218 { 219 uint8_t i; 220 uint16_t tempVariable = 0; 221 222 // Set module to encrypt mode 223 AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK; 224 225 // Write data to encrypt to module 226 for (i = 0; i < 16; i = i + 2) 227 { 228 tempVariable = (uint16_t) (data[i]); 229 tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8); 230 AES256_CMSIS(moduleInstance)->DIN = tempVariable; 231 } 232 233 // Key that is already written shall be used 234 // Encryption is initialized by setting AES256_STAT_KEYWR to 1 235 BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1; 236 } 237 238 void AES256_startDecryptData(uint32_t moduleInstance, const uint8_t * data) 239 { 240 uint_fast8_t i; 241 uint16_t tempVariable = 0; 242 243 // Set module to decrypt mode 244 AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3); 245 246 // Write data to decrypt to module 247 for (i = 0; i < 16; i = i + 2) 248 { 249 tempVariable = (uint16_t) (data[i + 1] << 8); 250 tempVariable = tempVariable | ((uint16_t) (data[i])); 251 AES256_CMSIS(moduleInstance)->DIN = tempVariable; 252 } 253 254 // Key that is already written shall be used 255 // Now decryption starts 256 BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1; 257 } 258 259 bool AES256_startSetDecipherKey(uint32_t moduleInstance, 260 const uint8_t * cipherKey, uint_fast16_t keyLength) 261 { 262 uint_fast8_t i; 263 uint16_t tempVariable = 0; 264 265 AES256_CMSIS(moduleInstance)->CTL0 = 266 (AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1; 267 268 switch (keyLength) 269 { 270 case AES256_KEYLENGTH_128BIT: 271 AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT; 272 break; 273 274 case AES256_KEYLENGTH_192BIT: 275 AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT; 276 break; 277 278 case AES256_KEYLENGTH_256BIT: 279 AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT; 280 break; 281 282 default: 283 return false; 284 } 285 286 keyLength = keyLength / 8; 287 288 // Write cipher key to key register 289 for (i = 0; i < keyLength; i = i + 2) 290 { 291 tempVariable = (uint16_t) (cipherKey[i]); 292 tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8); 293 AES256_CMSIS(moduleInstance)->KEY = tempVariable; 294 } 295 296 return true; 297 } 298 299 bool AES256_getDataOut(uint32_t moduleInstance, uint8_t *outputData) 300 { 301 uint8_t i; 302 uint16_t tempData = 0; 303 304 // If module is busy, exit and return failure 305 if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS)) 306 return false; 307 308 // Write encrypted data back to variable 309 for (i = 0; i < 16; i = i + 2) 310 { 311 tempData = AES256_CMSIS(moduleInstance)->DOUT; 312 *(outputData + i) = (uint8_t) tempData; 313 *(outputData + i + 1) = (uint8_t) (tempData >> 8); 314 } 315 316 return true; 317 } 318 319 bool AES256_isBusy(uint32_t moduleInstance) 320 { 321 return BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS); 322 } 323 324 void AES256_clearErrorFlag(uint32_t moduleInstance) 325 { 326 BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS) = 0; 327 } 328 329 uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance) 330 { 331 return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS); 332 } 333 334 void AES256_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void)) 335 { 336 Interrupt_registerInterrupt(INT_AES256, intHandler); 337 Interrupt_enableInterrupt(INT_AES256); 338 } 339 340 void AES256_unregisterInterrupt(uint32_t moduleInstance) 341 { 342 Interrupt_disableInterrupt(INT_AES256); 343 Interrupt_unregisterInterrupt(INT_AES256); 344 } 345 346 uint32_t AES256_getInterruptStatus(uint32_t moduleInstance) 347 { 348 return AES256_getInterruptFlagStatus(moduleInstance); 349 } 350 351