1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -mcpu=pwr7 -mattr=-vsx| FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s 3*9880d681SAndroid Build Coastguard Workertarget datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" 4*9880d681SAndroid Build Coastguard Workertarget triple = "powerpc64-unknown-linux-gnu" 5*9880d681SAndroid Build Coastguard Worker 6*9880d681SAndroid Build Coastguard Workerdefine void @copy_to_conceal(<8 x i16>* %inp) #0 { 7*9880d681SAndroid Build Coastguard Workerentry: 8*9880d681SAndroid Build Coastguard Worker store <8 x i16> zeroinitializer, <8 x i16>* %inp, align 2 9*9880d681SAndroid Build Coastguard Worker br label %if.end210 10*9880d681SAndroid Build Coastguard Worker 11*9880d681SAndroid Build Coastguard Workerif.end210: ; preds = %entry 12*9880d681SAndroid Build Coastguard Worker ret void 13*9880d681SAndroid Build Coastguard Worker 14*9880d681SAndroid Build Coastguard Worker; This will generate two align-1 i64 stores. Make sure that they are 15*9880d681SAndroid Build Coastguard Worker; indexed stores and not in r+i form (which require the offset to be 16*9880d681SAndroid Build Coastguard Worker; a multiple of 4). 17*9880d681SAndroid Build Coastguard Worker; CHECK: @copy_to_conceal 18*9880d681SAndroid Build Coastguard Worker; CHECK: stdx {{[0-9]+}}, 0, 19*9880d681SAndroid Build Coastguard Worker 20*9880d681SAndroid Build Coastguard Worker; CHECK-VSX: @copy_to_conceal 21*9880d681SAndroid Build Coastguard Worker; CHECK-VSX: stxvw4x {{[0-9]+}}, 0, 22*9880d681SAndroid Build Coastguard Worker} 23*9880d681SAndroid Build Coastguard Worker 24*9880d681SAndroid Build Coastguard Workerattributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 25