1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s 3*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -mtriple=powerpc-apple-darwin | FileCheck %s 4*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -mtriple=powerpc64-apple-darwin | FileCheck %s 5*9880d681SAndroid Build Coastguard Worker 6*9880d681SAndroid Build Coastguard Worker; This test verifies that we choose "assembler variant 1" (which GCC 7*9880d681SAndroid Build Coastguard Worker; uses for "new-style mnemonics" as opposed to POWER mnemonics) when 8*9880d681SAndroid Build Coastguard Worker; processing multi-variant inline asm statements, on all subtargets. 9*9880d681SAndroid Build Coastguard Worker 10*9880d681SAndroid Build Coastguard Worker; CHECK: subfe 11*9880d681SAndroid Build Coastguard Worker; CHECK-NOT: sfe 12*9880d681SAndroid Build Coastguard Worker 13*9880d681SAndroid Build Coastguard Workerdefine i32 @test(i32 %in1, i32 %in2) { 14*9880d681SAndroid Build Coastguard Workerentry: 15*9880d681SAndroid Build Coastguard Worker %0 = tail call i32 asm "$(sfe$|subfe$) $0,$1,$2", "=r,r,r"(i32 %in1, i32 %in2) 16*9880d681SAndroid Build Coastguard Worker ret i32 %0 17*9880d681SAndroid Build Coastguard Worker} 18*9880d681SAndroid Build Coastguard Worker 19