1*67e74705SXin Li // RUN: %clang -target mipsel-unknown-linux -S -o - -emit-llvm %s \
2*67e74705SXin Li // RUN: | FileCheck %s
3*67e74705SXin Li
4*67e74705SXin Li // This checks that the frontend will accept inline asm constraints
5*67e74705SXin Li // c', 'l' and 'x'.
6*67e74705SXin Li
main()7*67e74705SXin Li int main()
8*67e74705SXin Li {
9*67e74705SXin Li // 'c': 16 bit address register for Mips16, GPR for all others
10*67e74705SXin Li // I am using 'c' to constrain both the target and one of the source
11*67e74705SXin Li // registers. We are looking for syntactical correctness.
12*67e74705SXin Li // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "addi $0,$1,$2 \0A\09\09", "=c,c,I,~{$1}"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW:#[0-9]+]], !srcloc !{{[0-9]+}}
13*67e74705SXin Li int __s, __v = 17;
14*67e74705SXin Li int __t;
15*67e74705SXin Li __asm__ __volatile__(
16*67e74705SXin Li "addi %0,%1,%2 \n\t\t"
17*67e74705SXin Li : "=c" (__t)
18*67e74705SXin Li : "c" (__s), "I" (__v));
19*67e74705SXin Li
20*67e74705SXin Li // 'l': lo register
21*67e74705SXin Li // We are making it clear that destination register is lo with the
22*67e74705SXin Li // use of the 'l' constraint ("=l").
23*67e74705SXin Li // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "mtlo $1 \0A\09\09", "=l,r,~{lo},~{$1}"(i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}}
24*67e74705SXin Li int i_temp = 44;
25*67e74705SXin Li int i_result;
26*67e74705SXin Li __asm__ __volatile__(
27*67e74705SXin Li "mtlo %1 \n\t\t"
28*67e74705SXin Li : "=l" (i_result)
29*67e74705SXin Li : "r" (i_temp)
30*67e74705SXin Li : "lo");
31*67e74705SXin Li
32*67e74705SXin Li // 'x': Combined lo/hi registers
33*67e74705SXin Li // We are specifying that destination registers are the hi/lo pair with the
34*67e74705SXin Li // use of the 'x' constraint ("=x").
35*67e74705SXin Li // CHECK: %{{[0-9]+}} = call i64 asm sideeffect "mthi $1 \0A\09\09mtlo $2 \0A\09\09", "=x,r,r,~{$1}"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}}
36*67e74705SXin Li int i_hi = 3;
37*67e74705SXin Li int i_lo = 2;
38*67e74705SXin Li long long ll_result = 0;
39*67e74705SXin Li __asm__ __volatile__(
40*67e74705SXin Li "mthi %1 \n\t\t"
41*67e74705SXin Li "mtlo %2 \n\t\t"
42*67e74705SXin Li : "=x" (ll_result)
43*67e74705SXin Li : "r" (i_hi), "r" (i_lo)
44*67e74705SXin Li : );
45*67e74705SXin Li
46*67e74705SXin Li return 0;
47*67e74705SXin Li }
48*67e74705SXin Li
49*67e74705SXin Li // CHECK: attributes [[NUW]] = { nounwind }
50