1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef STM32MP1_DDR_H 8*54fd6939SJiyong Park #define STM32MP1_DDR_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <stdbool.h> 11*54fd6939SJiyong Park #include <stdint.h> 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park #define DT_DDR_COMPAT "st,stm32mp1-ddr" 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park struct stm32mp1_ddr_size { 16*54fd6939SJiyong Park uint64_t base; 17*54fd6939SJiyong Park uint64_t size; 18*54fd6939SJiyong Park }; 19*54fd6939SJiyong Park 20*54fd6939SJiyong Park /** 21*54fd6939SJiyong Park * struct ddr_info 22*54fd6939SJiyong Park * 23*54fd6939SJiyong Park * @dev: pointer for the device 24*54fd6939SJiyong Park * @info: UCLASS RAM information 25*54fd6939SJiyong Park * @ctl: DDR controleur base address 26*54fd6939SJiyong Park * @phy: DDR PHY base address 27*54fd6939SJiyong Park * @syscfg: syscfg base address 28*54fd6939SJiyong Park */ 29*54fd6939SJiyong Park struct ddr_info { 30*54fd6939SJiyong Park struct stm32mp1_ddr_size info; 31*54fd6939SJiyong Park struct stm32mp1_ddrctl *ctl; 32*54fd6939SJiyong Park struct stm32mp1_ddrphy *phy; 33*54fd6939SJiyong Park uintptr_t pwr; 34*54fd6939SJiyong Park uintptr_t rcc; 35*54fd6939SJiyong Park }; 36*54fd6939SJiyong Park 37*54fd6939SJiyong Park struct stm32mp1_ddrctrl_reg { 38*54fd6939SJiyong Park uint32_t mstr; 39*54fd6939SJiyong Park uint32_t mrctrl0; 40*54fd6939SJiyong Park uint32_t mrctrl1; 41*54fd6939SJiyong Park uint32_t derateen; 42*54fd6939SJiyong Park uint32_t derateint; 43*54fd6939SJiyong Park uint32_t pwrctl; 44*54fd6939SJiyong Park uint32_t pwrtmg; 45*54fd6939SJiyong Park uint32_t hwlpctl; 46*54fd6939SJiyong Park uint32_t rfshctl0; 47*54fd6939SJiyong Park uint32_t rfshctl3; 48*54fd6939SJiyong Park uint32_t crcparctl0; 49*54fd6939SJiyong Park uint32_t zqctl0; 50*54fd6939SJiyong Park uint32_t dfitmg0; 51*54fd6939SJiyong Park uint32_t dfitmg1; 52*54fd6939SJiyong Park uint32_t dfilpcfg0; 53*54fd6939SJiyong Park uint32_t dfiupd0; 54*54fd6939SJiyong Park uint32_t dfiupd1; 55*54fd6939SJiyong Park uint32_t dfiupd2; 56*54fd6939SJiyong Park uint32_t dfiphymstr; 57*54fd6939SJiyong Park uint32_t odtmap; 58*54fd6939SJiyong Park uint32_t dbg0; 59*54fd6939SJiyong Park uint32_t dbg1; 60*54fd6939SJiyong Park uint32_t dbgcmd; 61*54fd6939SJiyong Park uint32_t poisoncfg; 62*54fd6939SJiyong Park uint32_t pccfg; 63*54fd6939SJiyong Park }; 64*54fd6939SJiyong Park 65*54fd6939SJiyong Park struct stm32mp1_ddrctrl_timing { 66*54fd6939SJiyong Park uint32_t rfshtmg; 67*54fd6939SJiyong Park uint32_t dramtmg0; 68*54fd6939SJiyong Park uint32_t dramtmg1; 69*54fd6939SJiyong Park uint32_t dramtmg2; 70*54fd6939SJiyong Park uint32_t dramtmg3; 71*54fd6939SJiyong Park uint32_t dramtmg4; 72*54fd6939SJiyong Park uint32_t dramtmg5; 73*54fd6939SJiyong Park uint32_t dramtmg6; 74*54fd6939SJiyong Park uint32_t dramtmg7; 75*54fd6939SJiyong Park uint32_t dramtmg8; 76*54fd6939SJiyong Park uint32_t dramtmg14; 77*54fd6939SJiyong Park uint32_t odtcfg; 78*54fd6939SJiyong Park }; 79*54fd6939SJiyong Park 80*54fd6939SJiyong Park struct stm32mp1_ddrctrl_map { 81*54fd6939SJiyong Park uint32_t addrmap1; 82*54fd6939SJiyong Park uint32_t addrmap2; 83*54fd6939SJiyong Park uint32_t addrmap3; 84*54fd6939SJiyong Park uint32_t addrmap4; 85*54fd6939SJiyong Park uint32_t addrmap5; 86*54fd6939SJiyong Park uint32_t addrmap6; 87*54fd6939SJiyong Park uint32_t addrmap9; 88*54fd6939SJiyong Park uint32_t addrmap10; 89*54fd6939SJiyong Park uint32_t addrmap11; 90*54fd6939SJiyong Park }; 91*54fd6939SJiyong Park 92*54fd6939SJiyong Park struct stm32mp1_ddrctrl_perf { 93*54fd6939SJiyong Park uint32_t sched; 94*54fd6939SJiyong Park uint32_t sched1; 95*54fd6939SJiyong Park uint32_t perfhpr1; 96*54fd6939SJiyong Park uint32_t perflpr1; 97*54fd6939SJiyong Park uint32_t perfwr1; 98*54fd6939SJiyong Park uint32_t pcfgr_0; 99*54fd6939SJiyong Park uint32_t pcfgw_0; 100*54fd6939SJiyong Park uint32_t pcfgqos0_0; 101*54fd6939SJiyong Park uint32_t pcfgqos1_0; 102*54fd6939SJiyong Park uint32_t pcfgwqos0_0; 103*54fd6939SJiyong Park uint32_t pcfgwqos1_0; 104*54fd6939SJiyong Park uint32_t pcfgr_1; 105*54fd6939SJiyong Park uint32_t pcfgw_1; 106*54fd6939SJiyong Park uint32_t pcfgqos0_1; 107*54fd6939SJiyong Park uint32_t pcfgqos1_1; 108*54fd6939SJiyong Park uint32_t pcfgwqos0_1; 109*54fd6939SJiyong Park uint32_t pcfgwqos1_1; 110*54fd6939SJiyong Park }; 111*54fd6939SJiyong Park 112*54fd6939SJiyong Park struct stm32mp1_ddrphy_reg { 113*54fd6939SJiyong Park uint32_t pgcr; 114*54fd6939SJiyong Park uint32_t aciocr; 115*54fd6939SJiyong Park uint32_t dxccr; 116*54fd6939SJiyong Park uint32_t dsgcr; 117*54fd6939SJiyong Park uint32_t dcr; 118*54fd6939SJiyong Park uint32_t odtcr; 119*54fd6939SJiyong Park uint32_t zq0cr1; 120*54fd6939SJiyong Park uint32_t dx0gcr; 121*54fd6939SJiyong Park uint32_t dx1gcr; 122*54fd6939SJiyong Park uint32_t dx2gcr; 123*54fd6939SJiyong Park uint32_t dx3gcr; 124*54fd6939SJiyong Park }; 125*54fd6939SJiyong Park 126*54fd6939SJiyong Park struct stm32mp1_ddrphy_timing { 127*54fd6939SJiyong Park uint32_t ptr0; 128*54fd6939SJiyong Park uint32_t ptr1; 129*54fd6939SJiyong Park uint32_t ptr2; 130*54fd6939SJiyong Park uint32_t dtpr0; 131*54fd6939SJiyong Park uint32_t dtpr1; 132*54fd6939SJiyong Park uint32_t dtpr2; 133*54fd6939SJiyong Park uint32_t mr0; 134*54fd6939SJiyong Park uint32_t mr1; 135*54fd6939SJiyong Park uint32_t mr2; 136*54fd6939SJiyong Park uint32_t mr3; 137*54fd6939SJiyong Park }; 138*54fd6939SJiyong Park 139*54fd6939SJiyong Park struct stm32mp1_ddrphy_cal { 140*54fd6939SJiyong Park uint32_t dx0dllcr; 141*54fd6939SJiyong Park uint32_t dx0dqtr; 142*54fd6939SJiyong Park uint32_t dx0dqstr; 143*54fd6939SJiyong Park uint32_t dx1dllcr; 144*54fd6939SJiyong Park uint32_t dx1dqtr; 145*54fd6939SJiyong Park uint32_t dx1dqstr; 146*54fd6939SJiyong Park uint32_t dx2dllcr; 147*54fd6939SJiyong Park uint32_t dx2dqtr; 148*54fd6939SJiyong Park uint32_t dx2dqstr; 149*54fd6939SJiyong Park uint32_t dx3dllcr; 150*54fd6939SJiyong Park uint32_t dx3dqtr; 151*54fd6939SJiyong Park uint32_t dx3dqstr; 152*54fd6939SJiyong Park }; 153*54fd6939SJiyong Park 154*54fd6939SJiyong Park struct stm32mp1_ddr_info { 155*54fd6939SJiyong Park const char *name; 156*54fd6939SJiyong Park uint32_t speed; /* in kHZ */ 157*54fd6939SJiyong Park uint32_t size; /* Memory size in byte = col * row * width */ 158*54fd6939SJiyong Park }; 159*54fd6939SJiyong Park 160*54fd6939SJiyong Park struct stm32mp1_ddr_config { 161*54fd6939SJiyong Park struct stm32mp1_ddr_info info; 162*54fd6939SJiyong Park struct stm32mp1_ddrctrl_reg c_reg; 163*54fd6939SJiyong Park struct stm32mp1_ddrctrl_timing c_timing; 164*54fd6939SJiyong Park struct stm32mp1_ddrctrl_map c_map; 165*54fd6939SJiyong Park struct stm32mp1_ddrctrl_perf c_perf; 166*54fd6939SJiyong Park struct stm32mp1_ddrphy_reg p_reg; 167*54fd6939SJiyong Park struct stm32mp1_ddrphy_timing p_timing; 168*54fd6939SJiyong Park struct stm32mp1_ddrphy_cal p_cal; 169*54fd6939SJiyong Park }; 170*54fd6939SJiyong Park 171*54fd6939SJiyong Park int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed); 172*54fd6939SJiyong Park void stm32mp1_ddr_init(struct ddr_info *priv, 173*54fd6939SJiyong Park struct stm32mp1_ddr_config *config); 174*54fd6939SJiyong Park #endif /* STM32MP1_DDR_H */ 175