1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park * Copyright 2021 NXP
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park #include <errno.h>
8*54fd6939SJiyong Park #include <inttypes.h>
9*54fd6939SJiyong Park #include <stdint.h>
10*54fd6939SJiyong Park #include <stdio.h>
11*54fd6939SJiyong Park #include <stdlib.h>
12*54fd6939SJiyong Park #include <string.h>
13*54fd6939SJiyong Park
14*54fd6939SJiyong Park #include <common/debug.h>
15*54fd6939SJiyong Park #include <ddr.h>
16*54fd6939SJiyong Park #ifndef CONFIG_DDR_NODIMM
17*54fd6939SJiyong Park #include <i2c.h>
18*54fd6939SJiyong Park #endif
19*54fd6939SJiyong Park #include <nxp_timer.h>
20*54fd6939SJiyong Park
21*54fd6939SJiyong Park struct dynamic_odt {
22*54fd6939SJiyong Park unsigned int odt_rd_cfg;
23*54fd6939SJiyong Park unsigned int odt_wr_cfg;
24*54fd6939SJiyong Park unsigned int odt_rtt_norm;
25*54fd6939SJiyong Park unsigned int odt_rtt_wr;
26*54fd6939SJiyong Park };
27*54fd6939SJiyong Park
28*54fd6939SJiyong Park #ifndef CONFIG_STATIC_DDR
29*54fd6939SJiyong Park #if defined(PHY_GEN2_FW_IMAGE_BUFFER) && !defined(NXP_DDR_PHY_GEN2)
30*54fd6939SJiyong Park #error Missing NXP_DDR_PHY_GEN2
31*54fd6939SJiyong Park #endif
32*54fd6939SJiyong Park #ifdef NXP_DDR_PHY_GEN2
33*54fd6939SJiyong Park static const struct dynamic_odt single_D[4] = {
34*54fd6939SJiyong Park { /* cs0 */
35*54fd6939SJiyong Park DDR_ODT_NEVER,
36*54fd6939SJiyong Park DDR_ODT_ALL,
37*54fd6939SJiyong Park DDR4_RTT_80_OHM,
38*54fd6939SJiyong Park DDR4_RTT_WR_OFF
39*54fd6939SJiyong Park },
40*54fd6939SJiyong Park { /* cs1 */
41*54fd6939SJiyong Park DDR_ODT_NEVER,
42*54fd6939SJiyong Park DDR_ODT_NEVER,
43*54fd6939SJiyong Park DDR4_RTT_OFF,
44*54fd6939SJiyong Park DDR4_RTT_WR_OFF
45*54fd6939SJiyong Park },
46*54fd6939SJiyong Park {},
47*54fd6939SJiyong Park {}
48*54fd6939SJiyong Park };
49*54fd6939SJiyong Park
50*54fd6939SJiyong Park static const struct dynamic_odt single_S[4] = {
51*54fd6939SJiyong Park { /* cs0 */
52*54fd6939SJiyong Park DDR_ODT_NEVER,
53*54fd6939SJiyong Park DDR_ODT_ALL,
54*54fd6939SJiyong Park DDR4_RTT_80_OHM,
55*54fd6939SJiyong Park DDR4_RTT_WR_OFF
56*54fd6939SJiyong Park },
57*54fd6939SJiyong Park {},
58*54fd6939SJiyong Park {},
59*54fd6939SJiyong Park {},
60*54fd6939SJiyong Park };
61*54fd6939SJiyong Park
62*54fd6939SJiyong Park static const struct dynamic_odt dual_DD[4] = {
63*54fd6939SJiyong Park { /* cs0 */
64*54fd6939SJiyong Park DDR_ODT_OTHER_DIMM,
65*54fd6939SJiyong Park DDR_ODT_ALL,
66*54fd6939SJiyong Park DDR4_RTT_60_OHM,
67*54fd6939SJiyong Park DDR4_RTT_WR_240_OHM
68*54fd6939SJiyong Park },
69*54fd6939SJiyong Park { /* cs1 */
70*54fd6939SJiyong Park DDR_ODT_OTHER_DIMM,
71*54fd6939SJiyong Park DDR_ODT_ALL,
72*54fd6939SJiyong Park DDR4_RTT_60_OHM,
73*54fd6939SJiyong Park DDR4_RTT_WR_240_OHM
74*54fd6939SJiyong Park },
75*54fd6939SJiyong Park { /* cs2 */
76*54fd6939SJiyong Park DDR_ODT_OTHER_DIMM,
77*54fd6939SJiyong Park DDR_ODT_ALL,
78*54fd6939SJiyong Park DDR4_RTT_60_OHM,
79*54fd6939SJiyong Park DDR4_RTT_WR_240_OHM
80*54fd6939SJiyong Park },
81*54fd6939SJiyong Park { /* cs3 */
82*54fd6939SJiyong Park DDR_ODT_OTHER_DIMM,
83*54fd6939SJiyong Park DDR_ODT_ALL,
84*54fd6939SJiyong Park DDR4_RTT_60_OHM,
85*54fd6939SJiyong Park DDR4_RTT_WR_240_OHM
86*54fd6939SJiyong Park }
87*54fd6939SJiyong Park };
88*54fd6939SJiyong Park
89*54fd6939SJiyong Park static const struct dynamic_odt dual_SS[4] = {
90*54fd6939SJiyong Park { /* cs0 */
91*54fd6939SJiyong Park DDR_ODT_NEVER,
92*54fd6939SJiyong Park DDR_ODT_ALL,
93*54fd6939SJiyong Park DDR4_RTT_80_OHM,
94*54fd6939SJiyong Park DDR4_RTT_WR_OFF
95*54fd6939SJiyong Park },
96*54fd6939SJiyong Park {},
97*54fd6939SJiyong Park { /* cs2 */
98*54fd6939SJiyong Park DDR_ODT_NEVER,
99*54fd6939SJiyong Park DDR_ODT_ALL,
100*54fd6939SJiyong Park DDR4_RTT_80_OHM,
101*54fd6939SJiyong Park DDR4_RTT_WR_OFF
102*54fd6939SJiyong Park },
103*54fd6939SJiyong Park {}
104*54fd6939SJiyong Park };
105*54fd6939SJiyong Park
106*54fd6939SJiyong Park static const struct dynamic_odt dual_D0[4] = {
107*54fd6939SJiyong Park { /* cs0 */
108*54fd6939SJiyong Park DDR_ODT_NEVER,
109*54fd6939SJiyong Park DDR_ODT_SAME_DIMM,
110*54fd6939SJiyong Park DDR4_RTT_80_OHM,
111*54fd6939SJiyong Park DDR4_RTT_WR_OFF
112*54fd6939SJiyong Park },
113*54fd6939SJiyong Park { /* cs1 */
114*54fd6939SJiyong Park DDR_ODT_NEVER,
115*54fd6939SJiyong Park DDR_ODT_NEVER,
116*54fd6939SJiyong Park DDR4_RTT_80_OHM,
117*54fd6939SJiyong Park DDR4_RTT_WR_OFF
118*54fd6939SJiyong Park },
119*54fd6939SJiyong Park {},
120*54fd6939SJiyong Park {}
121*54fd6939SJiyong Park };
122*54fd6939SJiyong Park
123*54fd6939SJiyong Park static const struct dynamic_odt dual_S0[4] = {
124*54fd6939SJiyong Park { /* cs0 */
125*54fd6939SJiyong Park DDR_ODT_NEVER,
126*54fd6939SJiyong Park DDR_ODT_CS,
127*54fd6939SJiyong Park DDR4_RTT_80_OHM,
128*54fd6939SJiyong Park DDR4_RTT_WR_OFF
129*54fd6939SJiyong Park },
130*54fd6939SJiyong Park {},
131*54fd6939SJiyong Park {},
132*54fd6939SJiyong Park {}
133*54fd6939SJiyong Park };
134*54fd6939SJiyong Park #else
135*54fd6939SJiyong Park static const struct dynamic_odt single_D[4] = {
136*54fd6939SJiyong Park { /* cs0 */
137*54fd6939SJiyong Park DDR_ODT_NEVER,
138*54fd6939SJiyong Park DDR_ODT_ALL,
139*54fd6939SJiyong Park DDR4_RTT_40_OHM,
140*54fd6939SJiyong Park DDR4_RTT_WR_OFF
141*54fd6939SJiyong Park },
142*54fd6939SJiyong Park { /* cs1 */
143*54fd6939SJiyong Park DDR_ODT_NEVER,
144*54fd6939SJiyong Park DDR_ODT_NEVER,
145*54fd6939SJiyong Park DDR4_RTT_OFF,
146*54fd6939SJiyong Park DDR4_RTT_WR_OFF
147*54fd6939SJiyong Park },
148*54fd6939SJiyong Park {},
149*54fd6939SJiyong Park {}
150*54fd6939SJiyong Park };
151*54fd6939SJiyong Park
152*54fd6939SJiyong Park static const struct dynamic_odt single_S[4] = {
153*54fd6939SJiyong Park { /* cs0 */
154*54fd6939SJiyong Park DDR_ODT_NEVER,
155*54fd6939SJiyong Park DDR_ODT_ALL,
156*54fd6939SJiyong Park DDR4_RTT_40_OHM,
157*54fd6939SJiyong Park DDR4_RTT_WR_OFF
158*54fd6939SJiyong Park },
159*54fd6939SJiyong Park {},
160*54fd6939SJiyong Park {},
161*54fd6939SJiyong Park {},
162*54fd6939SJiyong Park };
163*54fd6939SJiyong Park
164*54fd6939SJiyong Park static const struct dynamic_odt dual_DD[4] = {
165*54fd6939SJiyong Park { /* cs0 */
166*54fd6939SJiyong Park DDR_ODT_NEVER,
167*54fd6939SJiyong Park DDR_ODT_SAME_DIMM,
168*54fd6939SJiyong Park DDR4_RTT_120_OHM,
169*54fd6939SJiyong Park DDR4_RTT_WR_OFF
170*54fd6939SJiyong Park },
171*54fd6939SJiyong Park { /* cs1 */
172*54fd6939SJiyong Park DDR_ODT_OTHER_DIMM,
173*54fd6939SJiyong Park DDR_ODT_OTHER_DIMM,
174*54fd6939SJiyong Park DDR4_RTT_34_OHM,
175*54fd6939SJiyong Park DDR4_RTT_WR_OFF
176*54fd6939SJiyong Park },
177*54fd6939SJiyong Park { /* cs2 */
178*54fd6939SJiyong Park DDR_ODT_NEVER,
179*54fd6939SJiyong Park DDR_ODT_SAME_DIMM,
180*54fd6939SJiyong Park DDR4_RTT_120_OHM,
181*54fd6939SJiyong Park DDR4_RTT_WR_OFF
182*54fd6939SJiyong Park },
183*54fd6939SJiyong Park { /* cs3 */
184*54fd6939SJiyong Park DDR_ODT_OTHER_DIMM,
185*54fd6939SJiyong Park DDR_ODT_OTHER_DIMM,
186*54fd6939SJiyong Park DDR4_RTT_34_OHM,
187*54fd6939SJiyong Park DDR4_RTT_WR_OFF
188*54fd6939SJiyong Park }
189*54fd6939SJiyong Park };
190*54fd6939SJiyong Park
191*54fd6939SJiyong Park static const struct dynamic_odt dual_SS[4] = {
192*54fd6939SJiyong Park { /* cs0 */
193*54fd6939SJiyong Park DDR_ODT_OTHER_DIMM,
194*54fd6939SJiyong Park DDR_ODT_ALL,
195*54fd6939SJiyong Park DDR4_RTT_34_OHM,
196*54fd6939SJiyong Park DDR4_RTT_WR_120_OHM
197*54fd6939SJiyong Park },
198*54fd6939SJiyong Park {},
199*54fd6939SJiyong Park { /* cs2 */
200*54fd6939SJiyong Park DDR_ODT_OTHER_DIMM,
201*54fd6939SJiyong Park DDR_ODT_ALL,
202*54fd6939SJiyong Park DDR4_RTT_34_OHM,
203*54fd6939SJiyong Park DDR4_RTT_WR_120_OHM
204*54fd6939SJiyong Park },
205*54fd6939SJiyong Park {}
206*54fd6939SJiyong Park };
207*54fd6939SJiyong Park
208*54fd6939SJiyong Park static const struct dynamic_odt dual_D0[4] = {
209*54fd6939SJiyong Park { /* cs0 */
210*54fd6939SJiyong Park DDR_ODT_NEVER,
211*54fd6939SJiyong Park DDR_ODT_SAME_DIMM,
212*54fd6939SJiyong Park DDR4_RTT_40_OHM,
213*54fd6939SJiyong Park DDR4_RTT_WR_OFF
214*54fd6939SJiyong Park },
215*54fd6939SJiyong Park { /* cs1 */
216*54fd6939SJiyong Park DDR_ODT_NEVER,
217*54fd6939SJiyong Park DDR_ODT_NEVER,
218*54fd6939SJiyong Park DDR4_RTT_OFF,
219*54fd6939SJiyong Park DDR4_RTT_WR_OFF
220*54fd6939SJiyong Park },
221*54fd6939SJiyong Park {},
222*54fd6939SJiyong Park {}
223*54fd6939SJiyong Park };
224*54fd6939SJiyong Park
225*54fd6939SJiyong Park static const struct dynamic_odt dual_S0[4] = {
226*54fd6939SJiyong Park { /* cs0 */
227*54fd6939SJiyong Park DDR_ODT_NEVER,
228*54fd6939SJiyong Park DDR_ODT_CS,
229*54fd6939SJiyong Park DDR4_RTT_40_OHM,
230*54fd6939SJiyong Park DDR4_RTT_WR_OFF
231*54fd6939SJiyong Park },
232*54fd6939SJiyong Park {},
233*54fd6939SJiyong Park {},
234*54fd6939SJiyong Park {}
235*54fd6939SJiyong Park };
236*54fd6939SJiyong Park #endif /* NXP_DDR_PHY_GEN2 */
237*54fd6939SJiyong Park
238*54fd6939SJiyong Park /*
239*54fd6939SJiyong Park * Automatically select bank interleaving mode based on DIMMs
240*54fd6939SJiyong Park * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
241*54fd6939SJiyong Park * This function only deal with one or two slots per controller.
242*54fd6939SJiyong Park */
auto_bank_intlv(const int cs_in_use,const struct dimm_params * pdimm)243*54fd6939SJiyong Park static inline unsigned int auto_bank_intlv(const int cs_in_use,
244*54fd6939SJiyong Park const struct dimm_params *pdimm)
245*54fd6939SJiyong Park {
246*54fd6939SJiyong Park switch (cs_in_use) {
247*54fd6939SJiyong Park case 0xf:
248*54fd6939SJiyong Park return DDR_BA_INTLV_CS0123;
249*54fd6939SJiyong Park case 0x3:
250*54fd6939SJiyong Park return DDR_BA_INTLV_CS01;
251*54fd6939SJiyong Park case 0x1:
252*54fd6939SJiyong Park return DDR_BA_NONE;
253*54fd6939SJiyong Park case 0x5:
254*54fd6939SJiyong Park return DDR_BA_NONE;
255*54fd6939SJiyong Park default:
256*54fd6939SJiyong Park break;
257*54fd6939SJiyong Park }
258*54fd6939SJiyong Park
259*54fd6939SJiyong Park return 0U;
260*54fd6939SJiyong Park }
261*54fd6939SJiyong Park
cal_odt(const unsigned int clk,struct memctl_opt * popts,struct ddr_conf * conf,struct dimm_params * pdimm,const int dimm_slot_per_ctrl)262*54fd6939SJiyong Park static int cal_odt(const unsigned int clk,
263*54fd6939SJiyong Park struct memctl_opt *popts,
264*54fd6939SJiyong Park struct ddr_conf *conf,
265*54fd6939SJiyong Park struct dimm_params *pdimm,
266*54fd6939SJiyong Park const int dimm_slot_per_ctrl)
267*54fd6939SJiyong Park
268*54fd6939SJiyong Park {
269*54fd6939SJiyong Park unsigned int i;
270*54fd6939SJiyong Park const struct dynamic_odt *pdodt = NULL;
271*54fd6939SJiyong Park
272*54fd6939SJiyong Park const static struct dynamic_odt *table[2][5] = {
273*54fd6939SJiyong Park {single_S, single_D, NULL, NULL},
274*54fd6939SJiyong Park {dual_SS, dual_DD, NULL, NULL},
275*54fd6939SJiyong Park };
276*54fd6939SJiyong Park
277*54fd6939SJiyong Park if (dimm_slot_per_ctrl != 1 && dimm_slot_per_ctrl != 2) {
278*54fd6939SJiyong Park ERROR("Unsupported number of DIMMs\n");
279*54fd6939SJiyong Park return -EINVAL;
280*54fd6939SJiyong Park }
281*54fd6939SJiyong Park
282*54fd6939SJiyong Park pdodt = table[dimm_slot_per_ctrl - 1][pdimm->n_ranks - 1];
283*54fd6939SJiyong Park if (pdodt == dual_SS) {
284*54fd6939SJiyong Park pdodt = (conf->cs_in_use == 0x5) ? dual_SS :
285*54fd6939SJiyong Park ((conf->cs_in_use == 0x1) ? dual_S0 : NULL);
286*54fd6939SJiyong Park } else if (pdodt == dual_DD) {
287*54fd6939SJiyong Park pdodt = (conf->cs_in_use == 0xf) ? dual_DD :
288*54fd6939SJiyong Park ((conf->cs_in_use == 0x3) ? dual_D0 : NULL);
289*54fd6939SJiyong Park }
290*54fd6939SJiyong Park if (pdodt == dual_DD && pdimm->package_3ds) {
291*54fd6939SJiyong Park ERROR("Too many 3DS DIMMs.\n");
292*54fd6939SJiyong Park return -EINVAL;
293*54fd6939SJiyong Park }
294*54fd6939SJiyong Park
295*54fd6939SJiyong Park if (pdodt == NULL) {
296*54fd6939SJiyong Park ERROR("Error determing ODT.\n");
297*54fd6939SJiyong Park return -EINVAL;
298*54fd6939SJiyong Park }
299*54fd6939SJiyong Park
300*54fd6939SJiyong Park /* Pick chip-select local options. */
301*54fd6939SJiyong Park for (i = 0U; i < DDRC_NUM_CS; i++) {
302*54fd6939SJiyong Park debug("cs %d\n", i);
303*54fd6939SJiyong Park popts->cs_odt[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
304*54fd6939SJiyong Park debug(" odt_rd_cfg 0x%x\n",
305*54fd6939SJiyong Park popts->cs_odt[i].odt_rd_cfg);
306*54fd6939SJiyong Park popts->cs_odt[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
307*54fd6939SJiyong Park debug(" odt_wr_cfg 0x%x\n",
308*54fd6939SJiyong Park popts->cs_odt[i].odt_wr_cfg);
309*54fd6939SJiyong Park popts->cs_odt[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
310*54fd6939SJiyong Park debug(" odt_rtt_norm 0x%x\n",
311*54fd6939SJiyong Park popts->cs_odt[i].odt_rtt_norm);
312*54fd6939SJiyong Park popts->cs_odt[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
313*54fd6939SJiyong Park debug(" odt_rtt_wr 0x%x\n",
314*54fd6939SJiyong Park popts->cs_odt[i].odt_rtt_wr);
315*54fd6939SJiyong Park popts->cs_odt[i].auto_precharge = 0;
316*54fd6939SJiyong Park debug(" auto_precharge %d\n",
317*54fd6939SJiyong Park popts->cs_odt[i].auto_precharge);
318*54fd6939SJiyong Park }
319*54fd6939SJiyong Park
320*54fd6939SJiyong Park return 0;
321*54fd6939SJiyong Park }
322*54fd6939SJiyong Park
cal_opts(const unsigned int clk,struct memctl_opt * popts,struct ddr_conf * conf,struct dimm_params * pdimm,const int dimm_slot_per_ctrl,const unsigned int ip_rev)323*54fd6939SJiyong Park static int cal_opts(const unsigned int clk,
324*54fd6939SJiyong Park struct memctl_opt *popts,
325*54fd6939SJiyong Park struct ddr_conf *conf,
326*54fd6939SJiyong Park struct dimm_params *pdimm,
327*54fd6939SJiyong Park const int dimm_slot_per_ctrl,
328*54fd6939SJiyong Park const unsigned int ip_rev)
329*54fd6939SJiyong Park {
330*54fd6939SJiyong Park popts->rdimm = pdimm->rdimm;
331*54fd6939SJiyong Park popts->mirrored_dimm = pdimm->mirrored_dimm;
332*54fd6939SJiyong Park #ifdef CONFIG_DDR_ECC_EN
333*54fd6939SJiyong Park popts->ecc_mode = pdimm->edc_config == 0x02 ? 1 : 0;
334*54fd6939SJiyong Park #endif
335*54fd6939SJiyong Park popts->ctlr_init_ecc = popts->ecc_mode;
336*54fd6939SJiyong Park debug("ctlr_init_ecc %d\n", popts->ctlr_init_ecc);
337*54fd6939SJiyong Park popts->self_refresh_in_sleep = 1;
338*54fd6939SJiyong Park popts->dynamic_power = 0;
339*54fd6939SJiyong Park
340*54fd6939SJiyong Park /*
341*54fd6939SJiyong Park * check sdram width, allow platform override
342*54fd6939SJiyong Park * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
343*54fd6939SJiyong Park */
344*54fd6939SJiyong Park if (pdimm->primary_sdram_width == 64) {
345*54fd6939SJiyong Park popts->data_bus_dimm = DDR_DBUS_64;
346*54fd6939SJiyong Park popts->otf_burst_chop_en = 1;
347*54fd6939SJiyong Park } else if (pdimm->primary_sdram_width == 32) {
348*54fd6939SJiyong Park popts->data_bus_dimm = DDR_DBUS_32;
349*54fd6939SJiyong Park popts->otf_burst_chop_en = 0;
350*54fd6939SJiyong Park } else if (pdimm->primary_sdram_width == 16) {
351*54fd6939SJiyong Park popts->data_bus_dimm = DDR_DBUS_16;
352*54fd6939SJiyong Park popts->otf_burst_chop_en = 0;
353*54fd6939SJiyong Park } else {
354*54fd6939SJiyong Park ERROR("primary sdram width invalid!\n");
355*54fd6939SJiyong Park return -EINVAL;
356*54fd6939SJiyong Park }
357*54fd6939SJiyong Park popts->data_bus_used = popts->data_bus_dimm;
358*54fd6939SJiyong Park popts->x4_en = (pdimm->device_width == 4) ? 1 : 0;
359*54fd6939SJiyong Park debug("x4_en %d\n", popts->x4_en);
360*54fd6939SJiyong Park
361*54fd6939SJiyong Park /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
362*54fd6939SJiyong Park if (popts->rdimm != 0) {
363*54fd6939SJiyong Park popts->ap_en = 1; /* 0 = disable, 1 = enable */
364*54fd6939SJiyong Park } else {
365*54fd6939SJiyong Park popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
366*54fd6939SJiyong Park }
367*54fd6939SJiyong Park
368*54fd6939SJiyong Park if (ip_rev == 0x50500) {
369*54fd6939SJiyong Park popts->ap_en = 0;
370*54fd6939SJiyong Park }
371*54fd6939SJiyong Park
372*54fd6939SJiyong Park debug("ap_en %d\n", popts->ap_en);
373*54fd6939SJiyong Park
374*54fd6939SJiyong Park /* BSTTOPRE precharge interval uses 1/4 of refint value. */
375*54fd6939SJiyong Park popts->bstopre = picos_to_mclk(clk, pdimm->refresh_rate_ps) >> 2;
376*54fd6939SJiyong Park popts->tfaw_ps = pdimm->tfaw_ps;
377*54fd6939SJiyong Park
378*54fd6939SJiyong Park return 0;
379*54fd6939SJiyong Park }
380*54fd6939SJiyong Park
cal_intlv(const int num_ctlrs,struct memctl_opt * popts,struct ddr_conf * conf,struct dimm_params * pdimm)381*54fd6939SJiyong Park static void cal_intlv(const int num_ctlrs,
382*54fd6939SJiyong Park struct memctl_opt *popts,
383*54fd6939SJiyong Park struct ddr_conf *conf,
384*54fd6939SJiyong Park struct dimm_params *pdimm)
385*54fd6939SJiyong Park {
386*54fd6939SJiyong Park #ifdef NXP_DDR_INTLV_256B
387*54fd6939SJiyong Park if (num_ctlrs == 2) {
388*54fd6939SJiyong Park popts->ctlr_intlv = 1;
389*54fd6939SJiyong Park popts->ctlr_intlv_mode = DDR_256B_INTLV;
390*54fd6939SJiyong Park }
391*54fd6939SJiyong Park #endif
392*54fd6939SJiyong Park debug("ctlr_intlv %d\n", popts->ctlr_intlv);
393*54fd6939SJiyong Park debug("ctlr_intlv_mode %d\n", popts->ctlr_intlv_mode);
394*54fd6939SJiyong Park
395*54fd6939SJiyong Park popts->ba_intlv = auto_bank_intlv(conf->cs_in_use, pdimm);
396*54fd6939SJiyong Park debug("ba_intlv 0x%x\n", popts->ba_intlv);
397*54fd6939SJiyong Park }
398*54fd6939SJiyong Park
update_burst_length(struct memctl_opt * popts)399*54fd6939SJiyong Park static int update_burst_length(struct memctl_opt *popts)
400*54fd6939SJiyong Park {
401*54fd6939SJiyong Park /* Choose burst length. */
402*54fd6939SJiyong Park if ((popts->data_bus_used == DDR_DBUS_32) ||
403*54fd6939SJiyong Park (popts->data_bus_used == DDR_DBUS_16)) {
404*54fd6939SJiyong Park /* 32-bit or 16-bit bus */
405*54fd6939SJiyong Park popts->otf_burst_chop_en = 0;
406*54fd6939SJiyong Park popts->burst_length = DDR_BL8;
407*54fd6939SJiyong Park } else if (popts->otf_burst_chop_en != 0) { /* on-the-fly burst chop */
408*54fd6939SJiyong Park popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
409*54fd6939SJiyong Park } else {
410*54fd6939SJiyong Park popts->burst_length = DDR_BL8;
411*54fd6939SJiyong Park }
412*54fd6939SJiyong Park debug("data_bus_used %d\n", popts->data_bus_used);
413*54fd6939SJiyong Park debug("otf_burst_chop_en %d\n", popts->otf_burst_chop_en);
414*54fd6939SJiyong Park debug("burst_length 0x%x\n", popts->burst_length);
415*54fd6939SJiyong Park /*
416*54fd6939SJiyong Park * If a reduced data width is requested, but the SPD
417*54fd6939SJiyong Park * specifies a physically wider device, adjust the
418*54fd6939SJiyong Park * computed dimm capacities accordingly before
419*54fd6939SJiyong Park * assigning addresses.
420*54fd6939SJiyong Park * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
421*54fd6939SJiyong Park */
422*54fd6939SJiyong Park if (popts->data_bus_dimm > popts->data_bus_used) {
423*54fd6939SJiyong Park ERROR("Data bus configuration error\n");
424*54fd6939SJiyong Park return -EINVAL;
425*54fd6939SJiyong Park }
426*54fd6939SJiyong Park popts->dbw_cap_shift = popts->data_bus_used - popts->data_bus_dimm;
427*54fd6939SJiyong Park debug("dbw_cap_shift %d\n", popts->dbw_cap_shift);
428*54fd6939SJiyong Park
429*54fd6939SJiyong Park return 0;
430*54fd6939SJiyong Park }
431*54fd6939SJiyong Park
cal_board_params(struct ddr_info * priv,const struct board_timing * dimm,int len)432*54fd6939SJiyong Park int cal_board_params(struct ddr_info *priv,
433*54fd6939SJiyong Park const struct board_timing *dimm,
434*54fd6939SJiyong Park int len)
435*54fd6939SJiyong Park {
436*54fd6939SJiyong Park const unsigned long speed = priv->clk / 1000000;
437*54fd6939SJiyong Park const struct dimm_params *pdimm = &priv->dimm;
438*54fd6939SJiyong Park struct memctl_opt *popts = &priv->opt;
439*54fd6939SJiyong Park struct rc_timing const *prt = NULL;
440*54fd6939SJiyong Park struct rc_timing const *chosen = NULL;
441*54fd6939SJiyong Park int i;
442*54fd6939SJiyong Park
443*54fd6939SJiyong Park for (i = 0; i < len; i++) {
444*54fd6939SJiyong Park if (pdimm->rc == dimm[i].rc) {
445*54fd6939SJiyong Park prt = dimm[i].p;
446*54fd6939SJiyong Park break;
447*54fd6939SJiyong Park }
448*54fd6939SJiyong Park }
449*54fd6939SJiyong Park if (prt == NULL) {
450*54fd6939SJiyong Park ERROR("Board parameters no match.\n");
451*54fd6939SJiyong Park return -EINVAL;
452*54fd6939SJiyong Park }
453*54fd6939SJiyong Park while (prt->speed_bin != 0) {
454*54fd6939SJiyong Park if (speed <= prt->speed_bin) {
455*54fd6939SJiyong Park chosen = prt;
456*54fd6939SJiyong Park break;
457*54fd6939SJiyong Park }
458*54fd6939SJiyong Park prt++;
459*54fd6939SJiyong Park }
460*54fd6939SJiyong Park if (chosen == NULL) {
461*54fd6939SJiyong Park ERROR("timing no match for speed %lu\n", speed);
462*54fd6939SJiyong Park return -EINVAL;
463*54fd6939SJiyong Park }
464*54fd6939SJiyong Park popts->clk_adj = prt->clk_adj;
465*54fd6939SJiyong Park popts->wrlvl_start = prt->wrlvl;
466*54fd6939SJiyong Park popts->wrlvl_ctl_2 = (prt->wrlvl * 0x01010101 + dimm[i].add1) &
467*54fd6939SJiyong Park 0xFFFFFFFF;
468*54fd6939SJiyong Park popts->wrlvl_ctl_3 = (prt->wrlvl * 0x01010101 + dimm[i].add2) &
469*54fd6939SJiyong Park 0xFFFFFFFF;
470*54fd6939SJiyong Park
471*54fd6939SJiyong Park return 0;
472*54fd6939SJiyong Park }
473*54fd6939SJiyong Park
synthesize_ctlr(struct ddr_info * priv)474*54fd6939SJiyong Park static int synthesize_ctlr(struct ddr_info *priv)
475*54fd6939SJiyong Park {
476*54fd6939SJiyong Park int ret;
477*54fd6939SJiyong Park
478*54fd6939SJiyong Park ret = cal_odt(priv->clk,
479*54fd6939SJiyong Park &priv->opt,
480*54fd6939SJiyong Park &priv->conf,
481*54fd6939SJiyong Park &priv->dimm,
482*54fd6939SJiyong Park priv->dimm_on_ctlr);
483*54fd6939SJiyong Park if (ret != 0) {
484*54fd6939SJiyong Park return ret;
485*54fd6939SJiyong Park }
486*54fd6939SJiyong Park
487*54fd6939SJiyong Park ret = cal_opts(priv->clk,
488*54fd6939SJiyong Park &priv->opt,
489*54fd6939SJiyong Park &priv->conf,
490*54fd6939SJiyong Park &priv->dimm,
491*54fd6939SJiyong Park priv->dimm_on_ctlr,
492*54fd6939SJiyong Park priv->ip_rev);
493*54fd6939SJiyong Park
494*54fd6939SJiyong Park if (ret != 0) {
495*54fd6939SJiyong Park return ret;
496*54fd6939SJiyong Park }
497*54fd6939SJiyong Park
498*54fd6939SJiyong Park cal_intlv(priv->num_ctlrs, &priv->opt, &priv->conf, &priv->dimm);
499*54fd6939SJiyong Park ret = ddr_board_options(priv);
500*54fd6939SJiyong Park if (ret != 0) {
501*54fd6939SJiyong Park ERROR("Failed matching board timing.\n");
502*54fd6939SJiyong Park }
503*54fd6939SJiyong Park
504*54fd6939SJiyong Park ret = update_burst_length(&priv->opt);
505*54fd6939SJiyong Park
506*54fd6939SJiyong Park return ret;
507*54fd6939SJiyong Park }
508*54fd6939SJiyong Park
509*54fd6939SJiyong Park /* Return the bit mask of valid DIMMs found */
parse_spd(struct ddr_info * priv)510*54fd6939SJiyong Park static int parse_spd(struct ddr_info *priv)
511*54fd6939SJiyong Park {
512*54fd6939SJiyong Park struct ddr_conf *conf = &priv->conf;
513*54fd6939SJiyong Park struct dimm_params *dimm = &priv->dimm;
514*54fd6939SJiyong Park int j, valid_mask = 0;
515*54fd6939SJiyong Park
516*54fd6939SJiyong Park #ifdef CONFIG_DDR_NODIMM
517*54fd6939SJiyong Park valid_mask = ddr_get_ddr_params(dimm, conf);
518*54fd6939SJiyong Park if (valid_mask < 0) {
519*54fd6939SJiyong Park ERROR("DDR params error\n");
520*54fd6939SJiyong Park return valid_mask;
521*54fd6939SJiyong Park }
522*54fd6939SJiyong Park #else
523*54fd6939SJiyong Park const int *spd_addr = priv->spd_addr;
524*54fd6939SJiyong Park const int num_ctlrs = priv->num_ctlrs;
525*54fd6939SJiyong Park const int num_dimm = priv->dimm_on_ctlr;
526*54fd6939SJiyong Park struct ddr4_spd spd[2];
527*54fd6939SJiyong Park unsigned int spd_checksum[2];
528*54fd6939SJiyong Park int addr_idx = 0;
529*54fd6939SJiyong Park int spd_idx = 0;
530*54fd6939SJiyong Park int ret, addr, i;
531*54fd6939SJiyong Park
532*54fd6939SJiyong Park /* Scan all DIMMs */
533*54fd6939SJiyong Park for (i = 0; i < num_ctlrs; i++) {
534*54fd6939SJiyong Park debug("Controller %d\n", i);
535*54fd6939SJiyong Park for (j = 0; j < num_dimm; j++, addr_idx++) {
536*54fd6939SJiyong Park debug("DIMM %d\n", j);
537*54fd6939SJiyong Park addr = spd_addr[addr_idx];
538*54fd6939SJiyong Park if (addr == 0) {
539*54fd6939SJiyong Park if (j == 0) {
540*54fd6939SJiyong Park ERROR("First SPD addr wrong.\n");
541*54fd6939SJiyong Park return -EINVAL;
542*54fd6939SJiyong Park }
543*54fd6939SJiyong Park continue;
544*54fd6939SJiyong Park }
545*54fd6939SJiyong Park debug("addr 0x%x\n", addr);
546*54fd6939SJiyong Park ret = read_spd(addr, &spd[spd_idx],
547*54fd6939SJiyong Park sizeof(struct ddr4_spd));
548*54fd6939SJiyong Park if (ret != 0) { /* invalid */
549*54fd6939SJiyong Park debug("Invalid SPD at address 0x%x\n", addr);
550*54fd6939SJiyong Park continue;
551*54fd6939SJiyong Park }
552*54fd6939SJiyong Park
553*54fd6939SJiyong Park spd_checksum[spd_idx] =
554*54fd6939SJiyong Park (spd[spd_idx].crc[1] << 24) |
555*54fd6939SJiyong Park (spd[spd_idx].crc[0] << 16) |
556*54fd6939SJiyong Park (spd[spd_idx].mod_section.uc[127] << 8) |
557*54fd6939SJiyong Park (spd[spd_idx].mod_section.uc[126] << 0);
558*54fd6939SJiyong Park debug("checksum 0x%x\n", spd_checksum[spd_idx]);
559*54fd6939SJiyong Park if (spd_checksum[spd_idx] == 0) {
560*54fd6939SJiyong Park debug("Bad checksum, ignored.\n");
561*54fd6939SJiyong Park continue;
562*54fd6939SJiyong Park }
563*54fd6939SJiyong Park if (spd_idx == 0) {
564*54fd6939SJiyong Park /* first valid SPD */
565*54fd6939SJiyong Park ret = cal_dimm_params(&spd[0], dimm);
566*54fd6939SJiyong Park if (ret != 0) {
567*54fd6939SJiyong Park ERROR("SPD calculation error\n");
568*54fd6939SJiyong Park return -EINVAL;
569*54fd6939SJiyong Park }
570*54fd6939SJiyong Park }
571*54fd6939SJiyong Park
572*54fd6939SJiyong Park if (spd_idx != 0 && spd_checksum[0] !=
573*54fd6939SJiyong Park spd_checksum[spd_idx]) {
574*54fd6939SJiyong Park ERROR("Not identical DIMMs.\n");
575*54fd6939SJiyong Park return -EINVAL;
576*54fd6939SJiyong Park }
577*54fd6939SJiyong Park conf->dimm_in_use[j] = 1;
578*54fd6939SJiyong Park valid_mask |= 1 << addr_idx;
579*54fd6939SJiyong Park spd_idx = 1;
580*54fd6939SJiyong Park }
581*54fd6939SJiyong Park debug("done with controller %d\n", i);
582*54fd6939SJiyong Park }
583*54fd6939SJiyong Park switch (num_ctlrs) {
584*54fd6939SJiyong Park case 1:
585*54fd6939SJiyong Park if ((valid_mask & 0x1) == 0) {
586*54fd6939SJiyong Park ERROR("First slot cannot be empty.\n");
587*54fd6939SJiyong Park return -EINVAL;
588*54fd6939SJiyong Park }
589*54fd6939SJiyong Park break;
590*54fd6939SJiyong Park case 2:
591*54fd6939SJiyong Park switch (num_dimm) {
592*54fd6939SJiyong Park case 1:
593*54fd6939SJiyong Park if (valid_mask == 0) {
594*54fd6939SJiyong Park ERROR("Both slot empty\n");
595*54fd6939SJiyong Park return -EINVAL;
596*54fd6939SJiyong Park }
597*54fd6939SJiyong Park break;
598*54fd6939SJiyong Park case 2:
599*54fd6939SJiyong Park if (valid_mask != 0x5 &&
600*54fd6939SJiyong Park valid_mask != 0xf &&
601*54fd6939SJiyong Park (valid_mask & 0x7) != 0x4 &&
602*54fd6939SJiyong Park (valid_mask & 0xd) != 0x1) {
603*54fd6939SJiyong Park ERROR("Invalid DIMM combination.\n");
604*54fd6939SJiyong Park return -EINVAL;
605*54fd6939SJiyong Park }
606*54fd6939SJiyong Park break;
607*54fd6939SJiyong Park default:
608*54fd6939SJiyong Park ERROR("Invalid number of DIMMs.\n");
609*54fd6939SJiyong Park return -EINVAL;
610*54fd6939SJiyong Park }
611*54fd6939SJiyong Park break;
612*54fd6939SJiyong Park default:
613*54fd6939SJiyong Park ERROR("Invalid number of controllers.\n");
614*54fd6939SJiyong Park return -EINVAL;
615*54fd6939SJiyong Park }
616*54fd6939SJiyong Park /* now we have valid and identical DIMMs on controllers */
617*54fd6939SJiyong Park #endif /* CONFIG_DDR_NODIMM */
618*54fd6939SJiyong Park
619*54fd6939SJiyong Park debug("cal cs\n");
620*54fd6939SJiyong Park conf->cs_in_use = 0;
621*54fd6939SJiyong Park for (j = 0; j < DDRC_NUM_DIMM; j++) {
622*54fd6939SJiyong Park if (conf->dimm_in_use[j] == 0) {
623*54fd6939SJiyong Park continue;
624*54fd6939SJiyong Park }
625*54fd6939SJiyong Park switch (dimm->n_ranks) {
626*54fd6939SJiyong Park case 4:
627*54fd6939SJiyong Park ERROR("Quad-rank DIMM not supported\n");
628*54fd6939SJiyong Park return -EINVAL;
629*54fd6939SJiyong Park case 2:
630*54fd6939SJiyong Park conf->cs_on_dimm[j] = 0x3 << (j * CONFIG_CS_PER_SLOT);
631*54fd6939SJiyong Park conf->cs_in_use |= conf->cs_on_dimm[j];
632*54fd6939SJiyong Park break;
633*54fd6939SJiyong Park case 1:
634*54fd6939SJiyong Park conf->cs_on_dimm[j] = 0x1 << (j * CONFIG_CS_PER_SLOT);
635*54fd6939SJiyong Park conf->cs_in_use |= conf->cs_on_dimm[j];
636*54fd6939SJiyong Park break;
637*54fd6939SJiyong Park default:
638*54fd6939SJiyong Park ERROR("SPD error with n_ranks\n");
639*54fd6939SJiyong Park return -EINVAL;
640*54fd6939SJiyong Park }
641*54fd6939SJiyong Park debug("cs_in_use = %x\n", conf->cs_in_use);
642*54fd6939SJiyong Park debug("cs_on_dimm[%d] = %x\n", j, conf->cs_on_dimm[j]);
643*54fd6939SJiyong Park }
644*54fd6939SJiyong Park #ifndef CONFIG_DDR_NODIMM
645*54fd6939SJiyong Park if (priv->dimm.rdimm != 0) {
646*54fd6939SJiyong Park NOTICE("RDIMM %s\n", priv->dimm.mpart);
647*54fd6939SJiyong Park } else {
648*54fd6939SJiyong Park NOTICE("UDIMM %s\n", priv->dimm.mpart);
649*54fd6939SJiyong Park }
650*54fd6939SJiyong Park #else
651*54fd6939SJiyong Park NOTICE("%s\n", priv->dimm.mpart);
652*54fd6939SJiyong Park #endif
653*54fd6939SJiyong Park
654*54fd6939SJiyong Park return valid_mask;
655*54fd6939SJiyong Park }
656*54fd6939SJiyong Park
assign_intlv_addr(const struct dimm_params * pdimm,const struct memctl_opt * opt,struct ddr_conf * conf,const unsigned long long current_mem_base)657*54fd6939SJiyong Park static unsigned long long assign_intlv_addr(
658*54fd6939SJiyong Park const struct dimm_params *pdimm,
659*54fd6939SJiyong Park const struct memctl_opt *opt,
660*54fd6939SJiyong Park struct ddr_conf *conf,
661*54fd6939SJiyong Park const unsigned long long current_mem_base)
662*54fd6939SJiyong Park {
663*54fd6939SJiyong Park int i;
664*54fd6939SJiyong Park int ctlr_density_mul = 0;
665*54fd6939SJiyong Park const unsigned long long rank_density = pdimm->rank_density >>
666*54fd6939SJiyong Park opt->dbw_cap_shift;
667*54fd6939SJiyong Park unsigned long long total_ctlr_mem;
668*54fd6939SJiyong Park
669*54fd6939SJiyong Park debug("rank density 0x%llx\n", rank_density);
670*54fd6939SJiyong Park switch (opt->ba_intlv & DDR_BA_INTLV_CS0123) {
671*54fd6939SJiyong Park case DDR_BA_INTLV_CS0123:
672*54fd6939SJiyong Park ctlr_density_mul = 4;
673*54fd6939SJiyong Park break;
674*54fd6939SJiyong Park case DDR_BA_INTLV_CS01:
675*54fd6939SJiyong Park ctlr_density_mul = 2;
676*54fd6939SJiyong Park break;
677*54fd6939SJiyong Park default:
678*54fd6939SJiyong Park ctlr_density_mul = 1;
679*54fd6939SJiyong Park break;
680*54fd6939SJiyong Park }
681*54fd6939SJiyong Park debug("ctlr density mul %d\n", ctlr_density_mul);
682*54fd6939SJiyong Park switch (opt->ctlr_intlv_mode) {
683*54fd6939SJiyong Park case DDR_256B_INTLV:
684*54fd6939SJiyong Park total_ctlr_mem = 2 * ctlr_density_mul * rank_density;
685*54fd6939SJiyong Park break;
686*54fd6939SJiyong Park default:
687*54fd6939SJiyong Park ERROR("Unknown interleaving mode");
688*54fd6939SJiyong Park return 0;
689*54fd6939SJiyong Park }
690*54fd6939SJiyong Park conf->base_addr = current_mem_base;
691*54fd6939SJiyong Park conf->total_mem = total_ctlr_mem;
692*54fd6939SJiyong Park
693*54fd6939SJiyong Park /* overwrite cs_in_use bitmask with controller interleaving */
694*54fd6939SJiyong Park conf->cs_in_use = (1 << ctlr_density_mul) - 1;
695*54fd6939SJiyong Park debug("Overwrite cs_in_use as %x\n", conf->cs_in_use);
696*54fd6939SJiyong Park
697*54fd6939SJiyong Park /* Fill addr with each cs in use */
698*54fd6939SJiyong Park for (i = 0; i < ctlr_density_mul; i++) {
699*54fd6939SJiyong Park conf->cs_base_addr[i] = current_mem_base;
700*54fd6939SJiyong Park conf->cs_size[i] = total_ctlr_mem;
701*54fd6939SJiyong Park debug("CS %d\n", i);
702*54fd6939SJiyong Park debug(" base_addr 0x%llx\n", conf->cs_base_addr[i]);
703*54fd6939SJiyong Park debug(" size 0x%llx\n", conf->cs_size[i]);
704*54fd6939SJiyong Park }
705*54fd6939SJiyong Park
706*54fd6939SJiyong Park return total_ctlr_mem;
707*54fd6939SJiyong Park }
708*54fd6939SJiyong Park
assign_non_intlv_addr(const struct dimm_params * pdimm,const struct memctl_opt * opt,struct ddr_conf * conf,unsigned long long current_mem_base)709*54fd6939SJiyong Park static unsigned long long assign_non_intlv_addr(
710*54fd6939SJiyong Park const struct dimm_params *pdimm,
711*54fd6939SJiyong Park const struct memctl_opt *opt,
712*54fd6939SJiyong Park struct ddr_conf *conf,
713*54fd6939SJiyong Park unsigned long long current_mem_base)
714*54fd6939SJiyong Park {
715*54fd6939SJiyong Park int i;
716*54fd6939SJiyong Park const unsigned long long rank_density = pdimm->rank_density >>
717*54fd6939SJiyong Park opt->dbw_cap_shift;
718*54fd6939SJiyong Park unsigned long long total_ctlr_mem = 0ULL;
719*54fd6939SJiyong Park
720*54fd6939SJiyong Park debug("rank density 0x%llx\n", rank_density);
721*54fd6939SJiyong Park conf->base_addr = current_mem_base;
722*54fd6939SJiyong Park
723*54fd6939SJiyong Park /* assign each cs */
724*54fd6939SJiyong Park switch (opt->ba_intlv & DDR_BA_INTLV_CS0123) {
725*54fd6939SJiyong Park case DDR_BA_INTLV_CS0123:
726*54fd6939SJiyong Park for (i = 0; i < DDRC_NUM_CS; i++) {
727*54fd6939SJiyong Park conf->cs_base_addr[i] = current_mem_base;
728*54fd6939SJiyong Park conf->cs_size[i] = rank_density << 2;
729*54fd6939SJiyong Park total_ctlr_mem += rank_density;
730*54fd6939SJiyong Park }
731*54fd6939SJiyong Park break;
732*54fd6939SJiyong Park case DDR_BA_INTLV_CS01:
733*54fd6939SJiyong Park for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) && i < 2; i++) {
734*54fd6939SJiyong Park conf->cs_base_addr[i] = current_mem_base;
735*54fd6939SJiyong Park conf->cs_size[i] = rank_density << 1;
736*54fd6939SJiyong Park total_ctlr_mem += rank_density;
737*54fd6939SJiyong Park }
738*54fd6939SJiyong Park current_mem_base += total_ctlr_mem;
739*54fd6939SJiyong Park for (; ((conf->cs_in_use & (1 << i)) != 0) && i < DDRC_NUM_CS;
740*54fd6939SJiyong Park i++) {
741*54fd6939SJiyong Park conf->cs_base_addr[i] = current_mem_base;
742*54fd6939SJiyong Park conf->cs_size[i] = rank_density;
743*54fd6939SJiyong Park total_ctlr_mem += rank_density;
744*54fd6939SJiyong Park current_mem_base += rank_density;
745*54fd6939SJiyong Park }
746*54fd6939SJiyong Park break;
747*54fd6939SJiyong Park case DDR_BA_NONE:
748*54fd6939SJiyong Park for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) &&
749*54fd6939SJiyong Park (i < DDRC_NUM_CS); i++) {
750*54fd6939SJiyong Park conf->cs_base_addr[i] = current_mem_base;
751*54fd6939SJiyong Park conf->cs_size[i] = rank_density;
752*54fd6939SJiyong Park current_mem_base += rank_density;
753*54fd6939SJiyong Park total_ctlr_mem += rank_density;
754*54fd6939SJiyong Park }
755*54fd6939SJiyong Park break;
756*54fd6939SJiyong Park default:
757*54fd6939SJiyong Park ERROR("Unsupported bank interleaving\n");
758*54fd6939SJiyong Park return 0;
759*54fd6939SJiyong Park }
760*54fd6939SJiyong Park for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) &&
761*54fd6939SJiyong Park (i < DDRC_NUM_CS); i++) {
762*54fd6939SJiyong Park debug("CS %d\n", i);
763*54fd6939SJiyong Park debug(" base_addr 0x%llx\n", conf->cs_base_addr[i]);
764*54fd6939SJiyong Park debug(" size 0x%llx\n", conf->cs_size[i]);
765*54fd6939SJiyong Park }
766*54fd6939SJiyong Park
767*54fd6939SJiyong Park return total_ctlr_mem;
768*54fd6939SJiyong Park }
769*54fd6939SJiyong Park
770*54fd6939SJiyong Park unsigned long long assign_addresses(struct ddr_info *priv)
771*54fd6939SJiyong Park __attribute__ ((weak));
772*54fd6939SJiyong Park
assign_addresses(struct ddr_info * priv)773*54fd6939SJiyong Park unsigned long long assign_addresses(struct ddr_info *priv)
774*54fd6939SJiyong Park {
775*54fd6939SJiyong Park struct memctl_opt *opt = &priv->opt;
776*54fd6939SJiyong Park const struct dimm_params *dimm = &priv->dimm;
777*54fd6939SJiyong Park struct ddr_conf *conf = &priv->conf;
778*54fd6939SJiyong Park unsigned long long current_mem_base = priv->mem_base;
779*54fd6939SJiyong Park unsigned long long total_mem;
780*54fd6939SJiyong Park
781*54fd6939SJiyong Park total_mem = 0ULL;
782*54fd6939SJiyong Park debug("ctlr_intlv %d\n", opt->ctlr_intlv);
783*54fd6939SJiyong Park if (opt->ctlr_intlv != 0) {
784*54fd6939SJiyong Park total_mem = assign_intlv_addr(dimm, opt, conf,
785*54fd6939SJiyong Park current_mem_base);
786*54fd6939SJiyong Park } else {
787*54fd6939SJiyong Park /*
788*54fd6939SJiyong Park * Simple linear assignment if memory controllers are not
789*54fd6939SJiyong Park * interleaved. This is only valid for SoCs with single DDRC.
790*54fd6939SJiyong Park */
791*54fd6939SJiyong Park total_mem = assign_non_intlv_addr(dimm, opt, conf,
792*54fd6939SJiyong Park current_mem_base);
793*54fd6939SJiyong Park }
794*54fd6939SJiyong Park conf->total_mem = total_mem;
795*54fd6939SJiyong Park debug("base 0x%llx\n", current_mem_base);
796*54fd6939SJiyong Park debug("Total mem by assignment is 0x%llx\n", total_mem);
797*54fd6939SJiyong Park
798*54fd6939SJiyong Park return total_mem;
799*54fd6939SJiyong Park }
800*54fd6939SJiyong Park
cal_ddrc_regs(struct ddr_info * priv)801*54fd6939SJiyong Park static int cal_ddrc_regs(struct ddr_info *priv)
802*54fd6939SJiyong Park {
803*54fd6939SJiyong Park int ret;
804*54fd6939SJiyong Park
805*54fd6939SJiyong Park ret = compute_ddrc(priv->clk,
806*54fd6939SJiyong Park &priv->opt,
807*54fd6939SJiyong Park &priv->conf,
808*54fd6939SJiyong Park &priv->ddr_reg,
809*54fd6939SJiyong Park &priv->dimm,
810*54fd6939SJiyong Park priv->ip_rev);
811*54fd6939SJiyong Park if (ret != 0) {
812*54fd6939SJiyong Park ERROR("Calculating DDR registers failed\n");
813*54fd6939SJiyong Park }
814*54fd6939SJiyong Park
815*54fd6939SJiyong Park return ret;
816*54fd6939SJiyong Park }
817*54fd6939SJiyong Park
818*54fd6939SJiyong Park #endif /* CONFIG_STATIC_DDR */
819*54fd6939SJiyong Park
write_ddrc_regs(struct ddr_info * priv)820*54fd6939SJiyong Park static int write_ddrc_regs(struct ddr_info *priv)
821*54fd6939SJiyong Park {
822*54fd6939SJiyong Park int i;
823*54fd6939SJiyong Park int ret;
824*54fd6939SJiyong Park
825*54fd6939SJiyong Park for (i = 0; i < priv->num_ctlrs; i++) {
826*54fd6939SJiyong Park ret = ddrc_set_regs(priv->clk, &priv->ddr_reg, priv->ddr[i], 0);
827*54fd6939SJiyong Park if (ret != 0) {
828*54fd6939SJiyong Park ERROR("Writing DDR register(s) failed\n");
829*54fd6939SJiyong Park return ret;
830*54fd6939SJiyong Park }
831*54fd6939SJiyong Park }
832*54fd6939SJiyong Park
833*54fd6939SJiyong Park return 0;
834*54fd6939SJiyong Park }
835*54fd6939SJiyong Park
dram_init(struct ddr_info * priv,uintptr_t nxp_ccn_hn_f0_addr)836*54fd6939SJiyong Park long long dram_init(struct ddr_info *priv
837*54fd6939SJiyong Park #if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
838*54fd6939SJiyong Park , uintptr_t nxp_ccn_hn_f0_addr
839*54fd6939SJiyong Park #endif
840*54fd6939SJiyong Park )
841*54fd6939SJiyong Park {
842*54fd6939SJiyong Park uint64_t time __unused;
843*54fd6939SJiyong Park long long dram_size;
844*54fd6939SJiyong Park int ret;
845*54fd6939SJiyong Park const uint64_t time_base = get_timer_val(0);
846*54fd6939SJiyong Park unsigned int ip_rev = get_ddrc_version(priv->ddr[0]);
847*54fd6939SJiyong Park
848*54fd6939SJiyong Park int valid_spd_mask __unused;
849*54fd6939SJiyong Park int scratch = 0x0;
850*54fd6939SJiyong Park
851*54fd6939SJiyong Park priv->ip_rev = ip_rev;
852*54fd6939SJiyong Park
853*54fd6939SJiyong Park #ifndef CONFIG_STATIC_DDR
854*54fd6939SJiyong Park INFO("time base %" PRIu64 " ms\n", time_base);
855*54fd6939SJiyong Park debug("Parse DIMM SPD(s)\n");
856*54fd6939SJiyong Park valid_spd_mask = parse_spd(priv);
857*54fd6939SJiyong Park
858*54fd6939SJiyong Park if (valid_spd_mask < 0) {
859*54fd6939SJiyong Park ERROR("Parsing DIMM Error\n");
860*54fd6939SJiyong Park return valid_spd_mask;
861*54fd6939SJiyong Park }
862*54fd6939SJiyong Park
863*54fd6939SJiyong Park #if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
864*54fd6939SJiyong Park if (priv->num_ctlrs == 2 || priv->num_ctlrs == 1) {
865*54fd6939SJiyong Park ret = disable_unused_ddrc(priv, valid_spd_mask,
866*54fd6939SJiyong Park nxp_ccn_hn_f0_addr);
867*54fd6939SJiyong Park if (ret != 0) {
868*54fd6939SJiyong Park return ret;
869*54fd6939SJiyong Park }
870*54fd6939SJiyong Park }
871*54fd6939SJiyong Park #endif
872*54fd6939SJiyong Park
873*54fd6939SJiyong Park time = get_timer_val(time_base);
874*54fd6939SJiyong Park INFO("Time after parsing SPD %" PRIu64 " ms\n", time);
875*54fd6939SJiyong Park debug("Synthesize configurations\n");
876*54fd6939SJiyong Park ret = synthesize_ctlr(priv);
877*54fd6939SJiyong Park if (ret != 0) {
878*54fd6939SJiyong Park ERROR("Synthesize config error\n");
879*54fd6939SJiyong Park return ret;
880*54fd6939SJiyong Park }
881*54fd6939SJiyong Park
882*54fd6939SJiyong Park debug("Assign binding addresses\n");
883*54fd6939SJiyong Park dram_size = assign_addresses(priv);
884*54fd6939SJiyong Park if (dram_size == 0) {
885*54fd6939SJiyong Park ERROR("Assigning address error\n");
886*54fd6939SJiyong Park return -EINVAL;
887*54fd6939SJiyong Park }
888*54fd6939SJiyong Park
889*54fd6939SJiyong Park debug("Calculate controller registers\n");
890*54fd6939SJiyong Park ret = cal_ddrc_regs(priv);
891*54fd6939SJiyong Park if (ret != 0) {
892*54fd6939SJiyong Park ERROR("Calculate register error\n");
893*54fd6939SJiyong Park return ret;
894*54fd6939SJiyong Park }
895*54fd6939SJiyong Park
896*54fd6939SJiyong Park ret = compute_ddr_phy(priv);
897*54fd6939SJiyong Park if (ret != 0)
898*54fd6939SJiyong Park ERROR("Calculating DDR PHY registers failed.\n");
899*54fd6939SJiyong Park
900*54fd6939SJiyong Park #else
901*54fd6939SJiyong Park dram_size = board_static_ddr(priv);
902*54fd6939SJiyong Park if (dram_size == 0) {
903*54fd6939SJiyong Park ERROR("Error getting static DDR settings.\n");
904*54fd6939SJiyong Park return -EINVAL;
905*54fd6939SJiyong Park }
906*54fd6939SJiyong Park #endif
907*54fd6939SJiyong Park
908*54fd6939SJiyong Park if (priv->warm_boot_flag == DDR_WARM_BOOT) {
909*54fd6939SJiyong Park scratch = (priv->ddr_reg).sdram_cfg[1];
910*54fd6939SJiyong Park scratch = scratch & ~(SDRAM_CFG2_D_INIT);
911*54fd6939SJiyong Park priv->ddr_reg.sdram_cfg[1] = scratch;
912*54fd6939SJiyong Park }
913*54fd6939SJiyong Park
914*54fd6939SJiyong Park time = get_timer_val(time_base);
915*54fd6939SJiyong Park INFO("Time before programming controller %" PRIu64 " ms\n", time);
916*54fd6939SJiyong Park debug("Program controller registers\n");
917*54fd6939SJiyong Park ret = write_ddrc_regs(priv);
918*54fd6939SJiyong Park if (ret != 0) {
919*54fd6939SJiyong Park ERROR("Programing DDRC error\n");
920*54fd6939SJiyong Park return ret;
921*54fd6939SJiyong Park }
922*54fd6939SJiyong Park
923*54fd6939SJiyong Park puts("");
924*54fd6939SJiyong Park NOTICE("%lld GB ", dram_size >> 30);
925*54fd6939SJiyong Park print_ddr_info(priv->ddr[0]);
926*54fd6939SJiyong Park
927*54fd6939SJiyong Park time = get_timer_val(time_base);
928*54fd6939SJiyong Park INFO("Time used by DDR driver %" PRIu64 " ms\n", time);
929*54fd6939SJiyong Park
930*54fd6939SJiyong Park return dram_size;
931*54fd6939SJiyong Park }
932