1 /*
2 * Copyright (C) 2023 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "context_riscv64.h"
18
19 #include <stdint.h>
20
21 #include "base/bit_utils.h"
22 #include "base/bit_utils_iterator.h"
23 #include "quick/quick_method_frame_info.h"
24 #include "thread-current-inl.h"
25
26 extern "C" __attribute__((weak)) void __hwasan_handle_longjmp(const void* sp_dst);
27
28 namespace art HIDDEN {
29 namespace riscv64 {
30
31 static constexpr uint64_t gZero = 0;
32
Reset()33 void Riscv64Context::Reset() {
34 std::fill_n(gprs_, arraysize(gprs_), nullptr);
35 std::fill_n(fprs_, arraysize(fprs_), nullptr);
36 gprs_[SP] = &sp_;
37 gprs_[kPC] = &pc_;
38 gprs_[A0] = &arg0_;
39 // Initialize registers with easy to spot debug values.
40 sp_ = kBadGprBase + SP;
41 pc_ = kBadGprBase + kPC;
42 arg0_ = 0;
43 }
44
FillCalleeSaves(uint8_t * frame,const QuickMethodFrameInfo & frame_info)45 void Riscv64Context::FillCalleeSaves(uint8_t* frame, const QuickMethodFrameInfo& frame_info) {
46 // RA is at top of the frame
47 DCHECK_NE(frame_info.CoreSpillMask() & (1u << RA), 0u);
48 const size_t frame_size = frame_info.FrameSizeInBytes();
49 gprs_[RA] = CalleeSaveAddress<InstructionSet::kRiscv64>(frame, 0, frame_size);
50
51 // Core registers come first, from the highest down to the lowest, with the exception of RA/X1.
52 int spill_pos = 1;
53 for (uint32_t core_reg : HighToLowBits(frame_info.CoreSpillMask() & ~(1u << RA))) {
54 gprs_[core_reg] = CalleeSaveAddress<InstructionSet::kRiscv64>(frame, spill_pos, frame_size);
55 ++spill_pos;
56 }
57 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()));
58
59 // FP registers come second, from the highest down to the lowest.
60 for (uint32_t fp_reg : HighToLowBits(frame_info.FpSpillMask())) {
61 fprs_[fp_reg] = CalleeSaveAddress<InstructionSet::kRiscv64>(frame, spill_pos, frame_size);
62 ++spill_pos;
63 }
64 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) + POPCOUNT(frame_info.FpSpillMask()));
65 }
66
SetGPR(uint32_t reg,uintptr_t value)67 void Riscv64Context::SetGPR(uint32_t reg, uintptr_t value) {
68 DCHECK_LT(reg, arraysize(gprs_));
69 DCHECK_NE(reg, static_cast<uint32_t>(Zero)); // Zero/X0 is immutable (hard-wired zero)
70 DCHECK(IsAccessibleGPR(reg));
71 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
72 *gprs_[reg] = value;
73 }
74
SetFPR(uint32_t reg,uintptr_t value)75 void Riscv64Context::SetFPR(uint32_t reg, uintptr_t value) {
76 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfFRegisters));
77 DCHECK(IsAccessibleFPR(reg));
78 DCHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
79 *fprs_[reg] = value;
80 }
81
SmashCallerSaves()82 void Riscv64Context::SmashCallerSaves() {
83 // Temporary registers T0 - T6 and argument registers A0 - A7 are caller-saved.
84 gprs_[Zero] = const_cast<uint64_t*>(&gZero); // hard-wired zero
85 gprs_[T0] = nullptr;
86 gprs_[T1] = nullptr;
87 gprs_[T2] = nullptr;
88 gprs_[T3] = nullptr;
89 gprs_[T4] = nullptr;
90 gprs_[T5] = nullptr;
91 gprs_[T6] = nullptr;
92 gprs_[A0] = const_cast<uint64_t*>(&gZero); // must be 0 because we want a null/zero return value
93 gprs_[A1] = nullptr;
94 gprs_[A2] = nullptr;
95 gprs_[A3] = nullptr;
96 gprs_[A4] = nullptr;
97 gprs_[A5] = nullptr;
98 gprs_[A6] = nullptr;
99 gprs_[A7] = nullptr;
100
101 // Temporary registers FT0 - FT11 and argument registers FA0 - FA7 are caller-saved.
102 fprs_[FT0] = nullptr;
103 fprs_[FT1] = nullptr;
104 fprs_[FT2] = nullptr;
105 fprs_[FT3] = nullptr;
106 fprs_[FT4] = nullptr;
107 fprs_[FT5] = nullptr;
108 fprs_[FT6] = nullptr;
109 fprs_[FT7] = nullptr;
110 fprs_[FT8] = nullptr;
111 fprs_[FT9] = nullptr;
112 fprs_[FT10] = nullptr;
113 fprs_[FT11] = nullptr;
114 fprs_[FA0] = nullptr;
115 fprs_[FA1] = nullptr;
116 fprs_[FA2] = nullptr;
117 fprs_[FA3] = nullptr;
118 fprs_[FA4] = nullptr;
119 fprs_[FA5] = nullptr;
120 fprs_[FA6] = nullptr;
121 fprs_[FA7] = nullptr;
122 }
123
CopyContextTo(uintptr_t * gprs,uintptr_t * fprs)124 void Riscv64Context::CopyContextTo(uintptr_t* gprs, uintptr_t* fprs) {
125 // The long jump routine called below expects to find the value for SP at index 2.
126 DCHECK_EQ(SP, 2);
127
128 for (size_t i = 0; i < arraysize(gprs_); ++i) {
129 gprs[i] = gprs_[i] != nullptr ? *gprs_[i] : kBadGprBase + i;
130 }
131 for (size_t i = 0; i < kNumberOfFRegisters; ++i) {
132 fprs[i] = fprs_[i] != nullptr ? *fprs_[i] : kBadFprBase + i;
133 }
134
135 // Fill in TR (the ART Thread Register) with the address of the current thread.
136 gprs[TR] = reinterpret_cast<uintptr_t>(Thread::Current());
137
138 // Tell HWASan about the new stack top.
139 if (__hwasan_handle_longjmp != nullptr) {
140 __hwasan_handle_longjmp(reinterpret_cast<void*>(gprs[SP]));
141 }
142 }
143
144 } // namespace riscv64
145 } // namespace art
146