1package xiangshan 2 3import chisel3._ 4import chisel3.stage._ 5import chiseltest._ 6import chiseltest.ChiselScalatestTester 7import chiseltest.VerilatorBackendAnnotation 8import chiseltest.simulator.{VerilatorFlags, VerilatorCFlags} 9import freechips.rocketchip.util.{ElaborationArtefacts, HasRocketChipStageUtils} 10import org.scalatest.flatspec.AnyFlatSpec 11import org.scalatest.matchers.must.Matchers 12import firrtl.stage.RunFirrtlTransformAnnotation 13import xstransforms.PrintModuleName 14 15import firrtl.options.TargetDirAnnotation 16 17import top.ArgParser 18import xiangshan.backend.decode.DecodeUnit 19 20object DecodeMain extends App with HasRocketChipStageUtils { 21 override def main(args: Array[String]): Unit = { 22 val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args) 23 // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config) 24 // If Complex Params are needed, wrap it with a Top Module to do dirty works, 25 // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params" 26 val defaultConfig = config.alterPartial({ 27 // Get XSCoreParams and pass it to the "small module" 28 case XSCoreParamsKey => config(XSTileKey).head.copy( 29 // Example of how to change params 30 IssQueSize = 12 31 ) 32 }) 33 (new ChiselStage).execute(args, Seq( 34 ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig) 35 ))) 36// // Generate files when compiling. Used by ChiselDB. 37// ElaborationArtefacts.files.foreach{ case (extension, contents) => 38// writeOutputFile("./build", s"DecodeUnit.${extension}", contents()) 39// } 40 } 41} 42 43class DecodeUnitTest extends XSTester { 44 behavior of "DecodeUnit" 45 it should "pass" in { 46 test(new DecodeUnit()(config)).withAnnotations(Seq( 47 VerilatorBackendAnnotation, 48 VerilatorFlags(Seq()), 49 WriteVcdAnnotation, 50 TargetDirAnnotation("./build"), 51 RunFirrtlTransformAnnotation(new PrintModuleName) 52 )){ dut => 53 dut.clock.step(10) 54 } 55 } 56}