1package xiangshan 2 3import chisel3._ 4import chisel3.stage._ 5import chiseltest._ 6import chiseltest.ChiselScalatestTester 7import chiseltest.VerilatorBackendAnnotation 8import chiseltest.simulator.{VerilatorFlags, VerilatorCFlags} 9import org.scalatest.flatspec.AnyFlatSpec 10import org.scalatest.matchers.must.Matchers 11import firrtl.stage.RunFirrtlTransformAnnotation 12import xstransforms.PrintModuleName 13import firrtl.options.TargetDirAnnotation 14import top.ArgParser 15import utility.FileRegisters 16import xiangshan.backend.decode.DecodeUnit 17 18object DecodeMain extends App { 19 val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args) 20 // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config) 21 // If Complex Params are needed, wrap it with a Top Module to do dirty works, 22 // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params" 23 val defaultConfig = config.alterPartial({ 24 // Get XSCoreParams and pass it to the "small module" 25 case XSCoreParamsKey => config(XSTileKey).head.copy( 26 // Example of how to change params 27 IssQueSize = 12 28 ) 29 }) 30 (new ChiselStage).execute(args, Seq( 31 ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig) 32 ))) 33// // Generate files when compiling. Used by ChiselDB. 34// FileRegisters.write("./build") 35} 36 37class DecodeUnitTest extends XSTester { 38 behavior of "DecodeUnit" 39 it should "pass" in { 40 test(new DecodeUnit()(config)).withAnnotations(Seq( 41 VerilatorBackendAnnotation, 42 VerilatorFlags(Seq()), 43 WriteVcdAnnotation, 44 TargetDirAnnotation("./build"), 45 RunFirrtlTransformAnnotation(new PrintModuleName) 46 )){ dut => 47 dut.clock.step(10) 48 } 49 } 50}