1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19 20import chipsalliance.rocketchip.config.Parameters 21import freechips.rocketchip.tile.XLen 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25 26package object xiangshan { 27 object SrcType { 28 def reg = "b00".U 29 def pc = "b01".U 30 def imm = "b01".U 31 def fp = "b10".U 32 33 def DC = imm // Don't Care 34 35 def isReg(srcType: UInt) = srcType===reg 36 def isPc(srcType: UInt) = srcType===pc 37 def isImm(srcType: UInt) = srcType===imm 38 def isFp(srcType: UInt) = srcType===fp 39 def isPcImm(srcType: UInt) = srcType(0) 40 def isRegFp(srcType: UInt) = !srcType(0) 41 42 def apply() = UInt(2.W) 43 } 44 45 object SrcState { 46 def busy = "b0".U 47 def rdy = "b1".U 48 // def specRdy = "b10".U // speculative ready, for future use 49 def apply() = UInt(1.W) 50 } 51 52 object FuType { 53 def jmp = "b0000".U 54 def i2f = "b0001".U 55 def csr = "b0010".U 56 def alu = "b0110".U 57 def mul = "b0100".U 58 def div = "b0101".U 59 def fence = "b0011".U 60 61 def fmac = "b1000".U 62 def fmisc = "b1011".U 63 def fDivSqrt = "b1010".U 64 65 def ldu = "b1100".U 66 def stu = "b1101".U 67 def mou = "b1111".U // for amo, lr, sc, fence 68 69 def num = 13 70 71 def apply() = UInt(log2Up(num).W) 72 73 def isIntExu(fuType: UInt) = !fuType(3) 74 def isJumpExu(fuType: UInt) = fuType === jmp 75 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 76 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 77 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 78 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 79 def isAMO(fuType: UInt) = fuType(1) 80 81 def jmpCanAccept(fuType: UInt) = !fuType(2) 82 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) 83 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) 84 85 def fmacCanAccept(fuType: UInt) = !fuType(1) 86 def fmiscCanAccept(fuType: UInt) = fuType(1) 87 88 def loadCanAccept(fuType: UInt) = !fuType(0) 89 def storeCanAccept(fuType: UInt) = fuType(0) 90 91 def storeIsAMO(fuType: UInt) = fuType(1) 92 93 val functionNameMap = Map( 94 jmp.litValue() -> "jmp", 95 i2f.litValue() -> "int to float", 96 csr.litValue() -> "csr", 97 alu.litValue() -> "alu", 98 mul.litValue() -> "mul", 99 div.litValue() -> "div", 100 fence.litValue() -> "fence", 101 fmac.litValue() -> "fmac", 102 fmisc.litValue() -> "fmisc", 103 fDivSqrt.litValue() -> "fdiv/fsqrt", 104 ldu.litValue() -> "load", 105 stu.litValue() -> "store" 106 ) 107 108 } 109 110 object FuOpType { 111 def apply() = UInt(6.W) 112 } 113 114 object CommitType { 115 def NORMAL = "b00".U // int/fp 116 def BRANCH = "b01".U // branch 117 def LOAD = "b10".U // load 118 def STORE = "b11".U // store 119 120 def apply() = UInt(2.W) 121 def isLoadStore(commitType: UInt) = commitType(1) 122 def lsInstIsStore(commitType: UInt) = commitType(0) 123 def isStore(commitType: UInt) = isLoadStore(commitType) && lsInstIsStore(commitType) 124 def isBranch(commitType: UInt) = commitType(0) && !commitType(1) 125 } 126 127 object RedirectLevel { 128 def flushAfter = "b0".U 129 def flush = "b1".U 130 131 def apply() = UInt(1.W) 132 // def isUnconditional(level: UInt) = level(1) 133 def flushItself(level: UInt) = level(0) 134 // def isException(level: UInt) = level(1) && level(0) 135 } 136 137 object ExceptionVec { 138 def apply() = Vec(16, Bool()) 139 } 140 141 object PMAMode { 142 def R = "b1".U << 0 //readable 143 def W = "b1".U << 1 //writeable 144 def X = "b1".U << 2 //executable 145 def I = "b1".U << 3 //cacheable: icache 146 def D = "b1".U << 4 //cacheable: dcache 147 def S = "b1".U << 5 //enable speculative access 148 def A = "b1".U << 6 //enable atomic operation, A imply R & W 149 def C = "b1".U << 7 //if it is cacheable is configable 150 def Reserved = "b0".U 151 152 def apply() = UInt(7.W) 153 154 def read(mode: UInt) = mode(0) 155 def write(mode: UInt) = mode(1) 156 def execute(mode: UInt) = mode(2) 157 def icache(mode: UInt) = mode(3) 158 def dcache(mode: UInt) = mode(4) 159 def speculate(mode: UInt) = mode(5) 160 def atomic(mode: UInt) = mode(6) 161 def configable_cache(mode: UInt) = mode(7) 162 163 def strToMode(s: String) = { 164 var result = 0.U(8.W) 165 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 166 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 167 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 168 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 169 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 170 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 171 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 172 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 173 result 174 } 175 } 176 177 178 object CSROpType { 179 def jmp = "b000".U 180 def wrt = "b001".U 181 def set = "b010".U 182 def clr = "b011".U 183 def wrti = "b101".U 184 def seti = "b110".U 185 def clri = "b111".U 186 } 187 188 // jump 189 object JumpOpType { 190 def jal = "b00".U 191 def jalr = "b01".U 192 def auipc = "b10".U 193// def call = "b11_011".U 194// def ret = "b11_100".U 195 def jumpOpisJalr(op: UInt) = op(0) 196 def jumpOpisAuipc(op: UInt) = op(1) 197 } 198 199 object FenceOpType { 200 def fence = "b10000".U 201 def sfence = "b10001".U 202 def fencei = "b10010".U 203 } 204 205 object ALUOpType { 206 def add = "b000000".U 207 def sll = "b000001".U 208 def slt = "b000010".U 209 def sltu = "b000011".U 210 def xor = "b000100".U 211 def srl = "b000101".U 212 def or = "b000110".U 213 def and = "b000111".U 214 def sub = "b001000".U 215 def sra = "b001101".U 216 217 def addw = "b100000".U 218 def subw = "b101000".U 219 def sllw = "b100001".U 220 def srlw = "b100101".U 221 def sraw = "b101101".U 222 223 def isAddSub(func: UInt) = { 224 func === add || func === sub || func === addw || func === subw 225 } 226 227 def isWordOp(func: UInt) = func(5) 228 229 def beq = "b010000".U 230 def bne = "b010001".U 231 def blt = "b010100".U 232 def bge = "b010101".U 233 def bltu = "b010110".U 234 def bgeu = "b010111".U 235 236 def isBranch(func: UInt) = func(4) 237 def getBranchType(func: UInt) = func(2, 1) 238 def isBranchInvert(func: UInt) = func(0) 239 } 240 241 object MDUOpType { 242 // mul 243 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 244 def mul = "b00000".U 245 def mulh = "b00001".U 246 def mulhsu = "b00010".U 247 def mulhu = "b00011".U 248 def mulw = "b00100".U 249 250 // div 251 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 252 def div = "b01000".U 253 def divu = "b01010".U 254 def rem = "b01001".U 255 def remu = "b01011".U 256 257 def divw = "b01100".U 258 def divuw = "b01110".U 259 def remw = "b01101".U 260 def remuw = "b01111".U 261 262 // fence 263 // bit encoding: | type (2bit) | padding(1bit)(zero) | opcode(2bit) | 264 def fence = "b10000".U 265 def sfence = "b10001".U 266 def fencei = "b10010".U 267 268 // the highest bits are for instruction types 269 def typeMSB = 4 270 def typeLSB = 3 271 272 def MulType = "b00".U 273 def DivType = "b01".U 274 def FenceType = "b10".U 275 276 def isMul(op: UInt) = op(typeMSB, typeLSB) === MulType 277 def isDiv(op: UInt) = op(typeMSB, typeLSB) === DivType 278 def isFence(op: UInt) = op(typeMSB, typeLSB) === FenceType 279 280 def isDivSign(op: UInt) = isDiv(op) && !op(1) 281 def isW(op: UInt) = op(2) 282 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1,0)=/=0.U) 283 def getMulOp(op: UInt) = op(1,0) 284 } 285 286 object LSUOpType { 287 // normal load/store 288 // bit(1, 0) are size 289 def lb = "b000000".U 290 def lh = "b000001".U 291 def lw = "b000010".U 292 def ld = "b000011".U 293 def lbu = "b000100".U 294 def lhu = "b000101".U 295 def lwu = "b000110".U 296 def sb = "b001000".U 297 def sh = "b001001".U 298 def sw = "b001010".U 299 def sd = "b001011".U 300 301 def isLoad(op: UInt): Bool = !op(3) 302 def isStore(op: UInt): Bool = op(3) 303 304 // atomics 305 // bit(1, 0) are size 306 // since atomics use a different fu type 307 // so we can safely reuse other load/store's encodings 308 def lr_w = "b000010".U 309 def sc_w = "b000110".U 310 def amoswap_w = "b001010".U 311 def amoadd_w = "b001110".U 312 def amoxor_w = "b010010".U 313 def amoand_w = "b010110".U 314 def amoor_w = "b011010".U 315 def amomin_w = "b011110".U 316 def amomax_w = "b100010".U 317 def amominu_w = "b100110".U 318 def amomaxu_w = "b101010".U 319 320 def lr_d = "b000011".U 321 def sc_d = "b000111".U 322 def amoswap_d = "b001011".U 323 def amoadd_d = "b001111".U 324 def amoxor_d = "b010011".U 325 def amoand_d = "b010111".U 326 def amoor_d = "b011011".U 327 def amomin_d = "b011111".U 328 def amomax_d = "b100011".U 329 def amominu_d = "b100111".U 330 def amomaxu_d = "b101011".U 331 } 332 333 object BTBtype { 334 def B = "b00".U // branch 335 def J = "b01".U // jump 336 def I = "b10".U // indirect 337 def R = "b11".U // return 338 339 def apply() = UInt(2.W) 340 } 341 342 object SelImm { 343 def IMM_X = "b111".U 344 def IMM_S = "b000".U 345 def IMM_SB = "b001".U 346 def IMM_U = "b010".U 347 def IMM_UJ = "b011".U 348 def IMM_I = "b100".U 349 def IMM_Z = "b101".U 350 def INVALID_INSTR = "b110".U 351 352 def apply() = UInt(3.W) 353 } 354 355 def dividerGen(p: Parameters) = new SRT4Divider(p(XLen))(p) 356 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1, Seq(0, 2))(p) 357 def aluGen(p: Parameters) = new Alu()(p) 358 def jmpGen(p: Parameters) = new Jump()(p) 359 def fenceGen(p: Parameters) = new Fence()(p) 360 def csrGen(p: Parameters) = new CSR()(p) 361 def i2fGen(p: Parameters) = new IntToFP()(p) 362 def fmacGen(p: Parameters) = new FMA()(p) 363 def f2iGen(p: Parameters) = new FPToInt()(p) 364 def f2fGen(p: Parameters) = new FPToFP()(p) 365 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 366 367 def f2iSel(x: FunctionUnit): Bool = { 368 x.io.in.bits.uop.ctrl.rfWen 369 } 370 371 def i2fSel(x: FunctionUnit): Bool = { 372 x.io.in.bits.uop.ctrl.fpu.fromInt 373 } 374 375 def f2fSel(x: FunctionUnit): Bool = { 376 val ctrl = x.io.in.bits.uop.ctrl.fpu 377 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 378 } 379 380 def fdivSqrtSel(x: FunctionUnit): Bool = { 381 val ctrl = x.io.in.bits.uop.ctrl.fpu 382 ctrl.div || ctrl.sqrt 383 } 384 385 val aluCfg = FuConfig( 386 fuGen = aluGen, 387 fuSel = _ => true.B, 388 fuType = FuType.alu, 389 numIntSrc = 2, 390 numFpSrc = 0, 391 writeIntRf = true, 392 writeFpRf = false, 393 hasRedirect = true, 394 ) 395 396 val jmpCfg = FuConfig( 397 fuGen = jmpGen, 398 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.jmp, 399 fuType = FuType.jmp, 400 numIntSrc = 1, 401 numFpSrc = 0, 402 writeIntRf = true, 403 writeFpRf = false, 404 hasRedirect = true, 405 ) 406 407 val fenceCfg = FuConfig( 408 fuGen = fenceGen, 409 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.fence, 410 FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 411 UncertainLatency() // TODO: need rewrite latency structure, not just this value 412 ) 413 414 val csrCfg = FuConfig( 415 fuGen = csrGen, 416 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.csr, 417 fuType = FuType.csr, 418 numIntSrc = 1, 419 numFpSrc = 0, 420 writeIntRf = true, 421 writeFpRf = false, 422 hasRedirect = false 423 ) 424 425 val i2fCfg = FuConfig( 426 fuGen = i2fGen, 427 fuSel = i2fSel, 428 FuType.i2f, 429 numIntSrc = 1, 430 numFpSrc = 0, 431 writeIntRf = false, 432 writeFpRf = true, 433 hasRedirect = false, 434 UncertainLatency() 435 ) 436 437 val divCfg = FuConfig( 438 fuGen = dividerGen, 439 fuSel = (x: FunctionUnit) => MDUOpType.isDiv(x.io.in.bits.uop.ctrl.fuOpType), 440 FuType.div, 441 2, 442 0, 443 writeIntRf = true, 444 writeFpRf = false, 445 hasRedirect = false, 446 UncertainLatency() 447 ) 448 449 val mulCfg = FuConfig( 450 fuGen = multiplierGen, 451 fuSel = (x: FunctionUnit) => MDUOpType.isMul(x.io.in.bits.uop.ctrl.fuOpType), 452 FuType.mul, 453 2, 454 0, 455 writeIntRf = true, 456 writeFpRf = false, 457 hasRedirect = false, 458 CertainLatency(2) 459 ) 460 461 val fmacCfg = FuConfig( 462 fuGen = fmacGen, 463 fuSel = _ => true.B, 464 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(4) 465 ) 466 467 val f2iCfg = FuConfig( 468 fuGen = f2iGen, 469 fuSel = f2iSel, 470 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2) 471 ) 472 473 val f2fCfg = FuConfig( 474 fuGen = f2fGen, 475 fuSel = f2fSel, 476 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2) 477 ) 478 479 val fdivSqrtCfg = FuConfig( 480 fuGen = fdivSqrtGen, 481 fuSel = fdivSqrtSel, 482 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, UncertainLatency() 483 ) 484 485 val lduCfg = FuConfig( 486 null, // DontCare 487 null, 488 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false, 489 UncertainLatency() 490 ) 491 492 val stuCfg = FuConfig( 493 null, 494 null, 495 FuType.stu, 2, 1, writeIntRf = false, writeFpRf = false, hasRedirect = false, 496 UncertainLatency() 497 ) 498 499 val mouCfg = FuConfig( 500 null, 501 null, 502 FuType.mou, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 503 UncertainLatency() 504 ) 505 506 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 507 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 508 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg), 1, Int.MaxValue) 509 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 510 val FmiscExeUnitCfg = ExuConfig( 511 "FmiscExeUnit", 512 "Fp", 513 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 514 Int.MaxValue, 1 515 ) 516 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0) 517 val StExeUnitCfg = ExuConfig("StoreExu", "Mem", Seq(stuCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 518}