1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19 20import chipsalliance.rocketchip.config.Parameters 21import freechips.rocketchip.tile.XLen 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 36 def isReg(srcType: UInt) = srcType===reg 37 def isPc(srcType: UInt) = srcType===pc 38 def isImm(srcType: UInt) = srcType===imm 39 def isFp(srcType: UInt) = srcType===fp 40 def isPcImm(srcType: UInt) = srcType(0) 41 def isRegFp(srcType: UInt) = !srcType(0) 42 43 def apply() = UInt(2.W) 44 } 45 46 object SrcState { 47 def busy = "b0".U 48 def rdy = "b1".U 49 // def specRdy = "b10".U // speculative ready, for future use 50 def apply() = UInt(1.W) 51 } 52 53 object FuType { 54 def jmp = "b0000".U 55 def i2f = "b0001".U 56 def csr = "b0010".U 57 def alu = "b0110".U 58 def mul = "b0100".U 59 def div = "b0101".U 60 def fence = "b0011".U 61 def bmu = "b0111".U 62 63 def fmac = "b1000".U 64 def fmisc = "b1011".U 65 def fDivSqrt = "b1010".U 66 67 def ldu = "b1100".U 68 def stu = "b1101".U 69 def mou = "b1111".U // for amo, lr, sc, fence 70 71 def num = 14 72 73 def apply() = UInt(log2Up(num).W) 74 75 def isIntExu(fuType: UInt) = !fuType(3) 76 def isJumpExu(fuType: UInt) = fuType === jmp 77 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 78 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 79 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 80 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 81 def isAMO(fuType: UInt) = fuType(1) 82 83 def jmpCanAccept(fuType: UInt) = !fuType(2) 84 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 85 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 86 87 def fmacCanAccept(fuType: UInt) = !fuType(1) 88 def fmiscCanAccept(fuType: UInt) = fuType(1) 89 90 def loadCanAccept(fuType: UInt) = !fuType(0) 91 def storeCanAccept(fuType: UInt) = fuType(0) 92 93 def storeIsAMO(fuType: UInt) = fuType(1) 94 95 val functionNameMap = Map( 96 jmp.litValue() -> "jmp", 97 i2f.litValue() -> "int to float", 98 csr.litValue() -> "csr", 99 alu.litValue() -> "alu", 100 mul.litValue() -> "mul", 101 div.litValue() -> "div", 102 fence.litValue() -> "fence", 103 fmac.litValue() -> "fmac", 104 fmisc.litValue() -> "fmisc", 105 fDivSqrt.litValue() -> "fdiv/fsqrt", 106 ldu.litValue() -> "load", 107 stu.litValue() -> "store" 108 ) 109 110 } 111 112 object FuOpType { 113 def apply() = UInt(8.W) 114 } 115 116 object CommitType { 117 def NORMAL = "b00".U // int/fp 118 def BRANCH = "b01".U // branch 119 def LOAD = "b10".U // load 120 def STORE = "b11".U // store 121 122 def apply() = UInt(2.W) 123 def isLoadStore(commitType: UInt) = commitType(1) 124 def lsInstIsStore(commitType: UInt) = commitType(0) 125 def isStore(commitType: UInt) = isLoadStore(commitType) && lsInstIsStore(commitType) 126 def isBranch(commitType: UInt) = commitType(0) && !commitType(1) 127 } 128 129 object RedirectLevel { 130 def flushAfter = "b0".U 131 def flush = "b1".U 132 133 def apply() = UInt(1.W) 134 // def isUnconditional(level: UInt) = level(1) 135 def flushItself(level: UInt) = level(0) 136 // def isException(level: UInt) = level(1) && level(0) 137 } 138 139 object ExceptionVec { 140 def apply() = Vec(16, Bool()) 141 } 142 143 object PMAMode { 144 def R = "b1".U << 0 //readable 145 def W = "b1".U << 1 //writeable 146 def X = "b1".U << 2 //executable 147 def I = "b1".U << 3 //cacheable: icache 148 def D = "b1".U << 4 //cacheable: dcache 149 def S = "b1".U << 5 //enable speculative access 150 def A = "b1".U << 6 //enable atomic operation, A imply R & W 151 def C = "b1".U << 7 //if it is cacheable is configable 152 def Reserved = "b0".U 153 154 def apply() = UInt(7.W) 155 156 def read(mode: UInt) = mode(0) 157 def write(mode: UInt) = mode(1) 158 def execute(mode: UInt) = mode(2) 159 def icache(mode: UInt) = mode(3) 160 def dcache(mode: UInt) = mode(4) 161 def speculate(mode: UInt) = mode(5) 162 def atomic(mode: UInt) = mode(6) 163 def configable_cache(mode: UInt) = mode(7) 164 165 def strToMode(s: String) = { 166 var result = 0.U(8.W) 167 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 168 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 169 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 170 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 171 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 172 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 173 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 174 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 175 result 176 } 177 } 178 179 180 object CSROpType { 181 def jmp = "b000".U 182 def wrt = "b001".U 183 def set = "b010".U 184 def clr = "b011".U 185 def wrti = "b101".U 186 def seti = "b110".U 187 def clri = "b111".U 188 } 189 190 // jump 191 object JumpOpType { 192 def jal = "b00".U 193 def jalr = "b01".U 194 def auipc = "b10".U 195// def call = "b11_011".U 196// def ret = "b11_100".U 197 def jumpOpisJalr(op: UInt) = op(0) 198 def jumpOpisAuipc(op: UInt) = op(1) 199 } 200 201 object FenceOpType { 202 def fence = "b10000".U 203 def sfence = "b10001".U 204 def fencei = "b10010".U 205 } 206 207 object ALUOpType { 208 // misc & branch optype 209 def and = "b0_00_00_000".U 210 def andn = "b0_00_00_001".U 211 def or = "b0_00_00_010".U 212 def orn = "b0_00_00_011".U 213 def xor = "b0_00_00_100".U 214 def xnor = "b0_00_00_101".U 215 216 def sext_b = "b0_00_01_000".U 217 def sext_h = "b0_00_01_001".U 218 def zext_h = "b0_00_01_010".U 219 def orc_b = "b0_00_01_100".U 220 def rev8 = "b0_00_01_101".U 221 222 def beq = "b0_00_10_000".U 223 def bne = "b0_00_10_001".U 224 def blt = "b0_00_10_100".U 225 def bge = "b0_00_10_101".U 226 def bltu = "b0_00_10_110".U 227 def bgeu = "b0_00_10_111".U 228 229 // add & sub optype 230 def add_uw = "b0_01_00_000".U 231 def add = "b0_01_00_001".U 232 def sh1add_uw = "b0_01_00_010".U 233 def sh1add = "b0_01_00_011".U 234 def sh2add_uw = "b0_01_00_100".U 235 def sh2add = "b0_01_00_101".U 236 def sh3add_uw = "b0_01_00_110".U 237 def sh3add = "b0_01_00_111".U 238 239 240 // shift optype 241 def slli_uw = "b0_10_00_000".U 242 def sll = "b0_10_00_001".U 243 def bclr = "b0_10_00_100".U 244 def bset = "b0_10_00_101".U 245 def binv = "b0_10_00_110".U 246 247 def srl = "b0_10_01_001".U 248 def bext = "b0_10_01_010".U 249 def sra = "b0_10_01_100".U 250 251 def rol = "b0_10_10_000".U 252 253 def ror = "b0_10_11_000".U 254 255 def sub = "b0_11_00_000".U 256 def sltu = "b0_11_00_001".U 257 def slt = "b0_11_00_010".U 258 def maxu = "b0_11_00_100".U 259 def minu = "b0_11_00_101".U 260 def max = "b0_11_00_110".U 261 def min = "b0_11_00_111".U 262 263 264 265 // RV64 32bit optype 266 def addw = "b1_01_00_001".U 267 def subw = "b1_11_00_000".U 268 def sllw = "b1_10_00_000".U 269 def srlw = "b1_10_01_001".U 270 def sraw = "b1_10_01_100".U 271 def rolw = "b1_10_10_000".U 272 def rorw = "b1_10_11_000".U 273 274 def isWordOp(func: UInt) = func(7) 275 def isBranch(func: UInt) = func(6, 3) === "b0010".U 276 def getBranchType(func: UInt) = func(2, 1) 277 def isBranchInvert(func: UInt) = func(0) 278 279 def apply() = UInt(8.W) 280 } 281 282 object MDUOpType { 283 // mul 284 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 285 def mul = "b00000".U 286 def mulh = "b00001".U 287 def mulhsu = "b00010".U 288 def mulhu = "b00011".U 289 def mulw = "b00100".U 290 291 // div 292 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 293 def div = "b01000".U 294 def divu = "b01010".U 295 def rem = "b01001".U 296 def remu = "b01011".U 297 298 def divw = "b01100".U 299 def divuw = "b01110".U 300 def remw = "b01101".U 301 def remuw = "b01111".U 302 303 // fence 304 // bit encoding: | type (2bit) | padding(1bit)(zero) | opcode(2bit) | 305 def fence = "b10000".U 306 def sfence = "b10001".U 307 def fencei = "b10010".U 308 309 // the highest bits are for instruction types 310 def typeMSB = 4 311 def typeLSB = 3 312 313 def MulType = "b00".U 314 def DivType = "b01".U 315 def FenceType = "b10".U 316 317 def isMul(op: UInt) = op(typeMSB, typeLSB) === MulType 318 def isDiv(op: UInt) = op(typeMSB, typeLSB) === DivType 319 def isFence(op: UInt) = op(typeMSB, typeLSB) === FenceType 320 321 def isDivSign(op: UInt) = isDiv(op) && !op(1) 322 def isW(op: UInt) = op(2) 323 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1,0)=/=0.U) 324 def getMulOp(op: UInt) = op(1,0) 325 } 326 327 object LSUOpType { 328 // normal load/store 329 // bit(1, 0) are size 330 def lb = "b000000".U 331 def lh = "b000001".U 332 def lw = "b000010".U 333 def ld = "b000011".U 334 def lbu = "b000100".U 335 def lhu = "b000101".U 336 def lwu = "b000110".U 337 def sb = "b001000".U 338 def sh = "b001001".U 339 def sw = "b001010".U 340 def sd = "b001011".U 341 342 def isLoad(op: UInt): Bool = !op(3) 343 def isStore(op: UInt): Bool = op(3) 344 345 // atomics 346 // bit(1, 0) are size 347 // since atomics use a different fu type 348 // so we can safely reuse other load/store's encodings 349 def lr_w = "b000010".U 350 def sc_w = "b000110".U 351 def amoswap_w = "b001010".U 352 def amoadd_w = "b001110".U 353 def amoxor_w = "b010010".U 354 def amoand_w = "b010110".U 355 def amoor_w = "b011010".U 356 def amomin_w = "b011110".U 357 def amomax_w = "b100010".U 358 def amominu_w = "b100110".U 359 def amomaxu_w = "b101010".U 360 361 def lr_d = "b000011".U 362 def sc_d = "b000111".U 363 def amoswap_d = "b001011".U 364 def amoadd_d = "b001111".U 365 def amoxor_d = "b010011".U 366 def amoand_d = "b010111".U 367 def amoor_d = "b011011".U 368 def amomin_d = "b011111".U 369 def amomax_d = "b100011".U 370 def amominu_d = "b100111".U 371 def amomaxu_d = "b101011".U 372 } 373 374 object BMUOpType { 375 376 def clmul = "b0000".U 377 def clmulh = "b0010".U 378 def clmulr = "b0100".U 379 380 def clz = "b1000".U 381 def clzw = "b1001".U 382 def ctz = "b1010".U 383 def ctzw = "b1011".U 384 def cpop = "b1100".U 385 def cpopw = "b1101".U 386 } 387 388 object BTBtype { 389 def B = "b00".U // branch 390 def J = "b01".U // jump 391 def I = "b10".U // indirect 392 def R = "b11".U // return 393 394 def apply() = UInt(2.W) 395 } 396 397 object SelImm { 398 def IMM_X = "b0111".U 399 def IMM_S = "b0000".U 400 def IMM_SB = "b0001".U 401 def IMM_U = "b0010".U 402 def IMM_UJ = "b0011".U 403 def IMM_I = "b0100".U 404 def IMM_Z = "b0101".U 405 def INVALID_INSTR = "b0110".U 406 def IMM_B6 = "b1000".U 407 408 def apply() = UInt(4.W) 409 } 410 411 def dividerGen(p: Parameters) = new SRT4Divider(p(XLen))(p) 412 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1, Seq(0, 2))(p) 413 def aluGen(p: Parameters) = new Alu()(p) 414 def bmuGen(p: Parameters) = new Bmu()(p) 415 def jmpGen(p: Parameters) = new Jump()(p) 416 def fenceGen(p: Parameters) = new Fence()(p) 417 def csrGen(p: Parameters) = new CSR()(p) 418 def i2fGen(p: Parameters) = new IntToFP()(p) 419 def fmacGen(p: Parameters) = new FMA()(p) 420 def f2iGen(p: Parameters) = new FPToInt()(p) 421 def f2fGen(p: Parameters) = new FPToFP()(p) 422 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 423 def stdGen(p: Parameters) = new Std()(p) 424 425 def f2iSel(x: FunctionUnit): Bool = { 426 x.io.in.bits.uop.ctrl.rfWen 427 } 428 429 def i2fSel(x: FunctionUnit): Bool = { 430 x.io.in.bits.uop.ctrl.fpu.fromInt 431 } 432 433 def f2fSel(x: FunctionUnit): Bool = { 434 val ctrl = x.io.in.bits.uop.ctrl.fpu 435 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 436 } 437 438 def fdivSqrtSel(x: FunctionUnit): Bool = { 439 val ctrl = x.io.in.bits.uop.ctrl.fpu 440 ctrl.div || ctrl.sqrt 441 } 442 443 val aluCfg = FuConfig( 444 name = "alu", 445 fuGen = aluGen, 446 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.alu, 447 fuType = FuType.alu, 448 numIntSrc = 2, 449 numFpSrc = 0, 450 writeIntRf = true, 451 writeFpRf = false, 452 hasRedirect = true, 453 ) 454 455 val jmpCfg = FuConfig( 456 name = "jmp", 457 fuGen = jmpGen, 458 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.jmp, 459 fuType = FuType.jmp, 460 numIntSrc = 1, 461 numFpSrc = 0, 462 writeIntRf = true, 463 writeFpRf = false, 464 hasRedirect = true, 465 ) 466 467 val fenceCfg = FuConfig( 468 name = "fence", 469 fuGen = fenceGen, 470 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.fence, 471 FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 472 UncertainLatency() // TODO: need rewrite latency structure, not just this value 473 ) 474 475 val csrCfg = FuConfig( 476 name = "csr", 477 fuGen = csrGen, 478 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.csr, 479 fuType = FuType.csr, 480 numIntSrc = 1, 481 numFpSrc = 0, 482 writeIntRf = true, 483 writeFpRf = false, 484 hasRedirect = false 485 ) 486 487 val i2fCfg = FuConfig( 488 name = "i2f", 489 fuGen = i2fGen, 490 fuSel = i2fSel, 491 FuType.i2f, 492 numIntSrc = 1, 493 numFpSrc = 0, 494 writeIntRf = false, 495 writeFpRf = true, 496 hasRedirect = false, 497 UncertainLatency() 498 ) 499 500 val divCfg = FuConfig( 501 name = "div", 502 fuGen = dividerGen, 503 fuSel = (x: FunctionUnit) => MDUOpType.isDiv(x.io.in.bits.uop.ctrl.fuOpType), 504 FuType.div, 505 2, 506 0, 507 writeIntRf = true, 508 writeFpRf = false, 509 hasRedirect = false, 510 latency = UncertainLatency(), 511 fastUopOut = true, 512 fastImplemented = false 513 ) 514 515 val mulCfg = FuConfig( 516 name = "mul", 517 fuGen = multiplierGen, 518 fuSel = (x: FunctionUnit) => MDUOpType.isMul(x.io.in.bits.uop.ctrl.fuOpType), 519 FuType.mul, 520 2, 521 0, 522 writeIntRf = true, 523 writeFpRf = false, 524 hasRedirect = false, 525 // TODO: change this back to 2 when mul is ready for fastUopOut 526 latency = CertainLatency(3), 527 fastUopOut = true, 528 fastImplemented = false 529 ) 530 531 val bmuCfg = FuConfig( 532 name = "bmu", 533 fuGen = bmuGen, 534 fuSel = (x: FunctionUnit) => x.io.in.bits.uop.ctrl.fuType === FuType.bmu, 535 fuType = FuType.bmu, 536 numIntSrc = 2, 537 numFpSrc = 0, 538 writeIntRf = true, 539 writeFpRf = false, 540 hasRedirect = false, 541 latency = CertainLatency(1), 542 fastUopOut = true, 543 fastImplemented = false 544 ) 545 546 val fmacCfg = FuConfig( 547 name = "fmac", 548 fuGen = fmacGen, 549 fuSel = _ => true.B, 550 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(4) 551 ) 552 553 val f2iCfg = FuConfig( 554 name = "f2i", 555 fuGen = f2iGen, 556 fuSel = f2iSel, 557 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2), 558 fastUopOut = true, fastImplemented = false 559 ) 560 561 val f2fCfg = FuConfig( 562 name = "f2f", 563 fuGen = f2fGen, 564 fuSel = f2fSel, 565 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2), 566 fastUopOut = true, fastImplemented = false 567 ) 568 569 val fdivSqrtCfg = FuConfig( 570 name = "fdivSqrt", 571 fuGen = fdivSqrtGen, 572 fuSel = fdivSqrtSel, 573 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, UncertainLatency(), 574 fastUopOut = true, fastImplemented = false 575 ) 576 577 val lduCfg = FuConfig( 578 "ldu", 579 null, // DontCare 580 null, 581 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false, 582 UncertainLatency() 583 ) 584 585 val staCfg = FuConfig( 586 "sta", 587 null, 588 null, 589 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 590 UncertainLatency() 591 ) 592 593 val stdCfg = FuConfig( 594 "std", 595 fuGen = stdGen, fuSel = _ => true.B, FuType.stu, 1, 1, 596 writeIntRf = false, writeFpRf = false, hasRedirect = false, UncertainLatency() 597 ) 598 599 val mouCfg = FuConfig( 600 "mou", 601 null, 602 null, 603 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 604 UncertainLatency() 605 ) 606 607 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 608 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 609 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 610 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bmuCfg), 1, Int.MaxValue) 611 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 612 val FmiscExeUnitCfg = ExuConfig( 613 "FmiscExeUnit", 614 "Fp", 615 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 616 Int.MaxValue, 1 617 ) 618 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0) 619 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 620 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 621} 622