1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 def X = BitPat("b??") 36 37 def isReg(srcType: UInt) = srcType===reg 38 def isPc(srcType: UInt) = srcType===pc 39 def isImm(srcType: UInt) = srcType===imm 40 def isFp(srcType: UInt) = srcType(1) 41 def isPcOrImm(srcType: UInt) = srcType(0) 42 def isRegOrFp(srcType: UInt) = !srcType(0) 43 def regIsFp(srcType: UInt) = srcType(1) 44 45 def apply() = UInt(2.W) 46 } 47 48 object SrcState { 49 def busy = "b0".U 50 def rdy = "b1".U 51 // def specRdy = "b10".U // speculative ready, for future use 52 def apply() = UInt(1.W) 53 } 54 55 object FuType { 56 def jmp = "b0000".U 57 def i2f = "b0001".U 58 def csr = "b0010".U 59 def alu = "b0110".U 60 def mul = "b0100".U 61 def div = "b0101".U 62 def fence = "b0011".U 63 def bku = "b0111".U 64 65 def fmac = "b1000".U 66 def fmisc = "b1011".U 67 def fDivSqrt = "b1010".U 68 69 def ldu = "b1100".U 70 def stu = "b1101".U 71 def mou = "b1111".U // for amo, lr, sc, fence 72 73 def X = BitPat("b????") 74 75 def num = 14 76 77 def apply() = UInt(log2Up(num).W) 78 79 def isIntExu(fuType: UInt) = !fuType(3) 80 def isJumpExu(fuType: UInt) = fuType === jmp 81 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 82 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 83 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 84 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 85 def isAMO(fuType: UInt) = fuType(1) 86 def isFence(fuType: UInt) = fuType === fence 87 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 88 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 89 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 90 91 92 def jmpCanAccept(fuType: UInt) = !fuType(2) 93 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 94 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 95 96 def fmacCanAccept(fuType: UInt) = !fuType(1) 97 def fmiscCanAccept(fuType: UInt) = fuType(1) 98 99 def loadCanAccept(fuType: UInt) = !fuType(0) 100 def storeCanAccept(fuType: UInt) = fuType(0) 101 102 def storeIsAMO(fuType: UInt) = fuType(1) 103 104 val functionNameMap = Map( 105 jmp.litValue() -> "jmp", 106 i2f.litValue() -> "int_to_float", 107 csr.litValue() -> "csr", 108 alu.litValue() -> "alu", 109 mul.litValue() -> "mul", 110 div.litValue() -> "div", 111 fence.litValue() -> "fence", 112 bku.litValue() -> "bku", 113 fmac.litValue() -> "fmac", 114 fmisc.litValue() -> "fmisc", 115 fDivSqrt.litValue() -> "fdiv_fsqrt", 116 ldu.litValue() -> "load", 117 stu.litValue() -> "store", 118 mou.litValue() -> "mou" 119 ) 120 } 121 122 object FuOpType { 123 def apply() = UInt(7.W) 124 def X = BitPat("b???????") 125 } 126 127 object CommitType { 128 def NORMAL = "b000".U // int/fp 129 def BRANCH = "b001".U // branch 130 def LOAD = "b010".U // load 131 def STORE = "b011".U // store 132 133 def apply() = UInt(3.W) 134 def isFused(commitType: UInt): Bool = commitType(2) 135 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 136 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 137 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 138 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 139 } 140 141 object RedirectLevel { 142 def flushAfter = "b0".U 143 def flush = "b1".U 144 145 def apply() = UInt(1.W) 146 // def isUnconditional(level: UInt) = level(1) 147 def flushItself(level: UInt) = level(0) 148 // def isException(level: UInt) = level(1) && level(0) 149 } 150 151 object ExceptionVec { 152 val ExceptionVecSize = 16 153 def apply() = Vec(ExceptionVecSize, Bool()) 154 } 155 156 object PMAMode { 157 def R = "b1".U << 0 //readable 158 def W = "b1".U << 1 //writeable 159 def X = "b1".U << 2 //executable 160 def I = "b1".U << 3 //cacheable: icache 161 def D = "b1".U << 4 //cacheable: dcache 162 def S = "b1".U << 5 //enable speculative access 163 def A = "b1".U << 6 //enable atomic operation, A imply R & W 164 def C = "b1".U << 7 //if it is cacheable is configable 165 def Reserved = "b0".U 166 167 def apply() = UInt(7.W) 168 169 def read(mode: UInt) = mode(0) 170 def write(mode: UInt) = mode(1) 171 def execute(mode: UInt) = mode(2) 172 def icache(mode: UInt) = mode(3) 173 def dcache(mode: UInt) = mode(4) 174 def speculate(mode: UInt) = mode(5) 175 def atomic(mode: UInt) = mode(6) 176 def configable_cache(mode: UInt) = mode(7) 177 178 def strToMode(s: String) = { 179 var result = 0.U(8.W) 180 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 181 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 182 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 183 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 184 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 185 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 186 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 187 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 188 result 189 } 190 } 191 192 193 object CSROpType { 194 def jmp = "b000".U 195 def wrt = "b001".U 196 def set = "b010".U 197 def clr = "b011".U 198 def wfi = "b100".U 199 def wrti = "b101".U 200 def seti = "b110".U 201 def clri = "b111".U 202 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 203 } 204 205 // jump 206 object JumpOpType { 207 def jal = "b00".U 208 def jalr = "b01".U 209 def auipc = "b10".U 210// def call = "b11_011".U 211// def ret = "b11_100".U 212 def jumpOpisJalr(op: UInt) = op(0) 213 def jumpOpisAuipc(op: UInt) = op(1) 214 } 215 216 object FenceOpType { 217 def fence = "b10000".U 218 def sfence = "b10001".U 219 def fencei = "b10010".U 220 def nofence= "b00000".U 221 } 222 223 object ALUOpType { 224 // shift optype 225 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 226 def sll = "b000_0001".U // sll: src1 << src2 227 228 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 229 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 230 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 231 232 def srl = "b000_0101".U // srl: src1 >> src2 233 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 234 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 235 236 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 237 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 238 239 // RV64 32bit optype 240 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 241 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 242 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 243 244 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 245 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 246 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 247 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 248 249 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 250 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 251 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 252 def rolw = "b001_1100".U 253 def rorw = "b001_1101".U 254 255 // ADD-op 256 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 257 def add = "b010_0001".U // add: src1 + src2 258 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 259 260 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 261 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 262 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 263 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 264 265 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 266 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 267 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 268 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 269 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 270 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 271 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 272 273 // SUB-op: src1 - src2 274 def sub = "b011_0000".U 275 def sltu = "b011_0001".U 276 def slt = "b011_0010".U 277 def maxu = "b011_0100".U 278 def minu = "b011_0101".U 279 def max = "b011_0110".U 280 def min = "b011_0111".U 281 282 // branch 283 def beq = "b111_0000".U 284 def bne = "b111_0010".U 285 def blt = "b111_1000".U 286 def bge = "b111_1010".U 287 def bltu = "b111_1100".U 288 def bgeu = "b111_1110".U 289 290 // misc optype 291 def and = "b100_0000".U 292 def andn = "b100_0001".U 293 def or = "b100_0010".U 294 def orn = "b100_0011".U 295 def xor = "b100_0100".U 296 def xnor = "b100_0101".U 297 def orcb = "b100_0110".U 298 299 def sextb = "b100_1000".U 300 def packh = "b100_1001".U 301 def sexth = "b100_1010".U 302 def packw = "b100_1011".U 303 304 def revb = "b101_0000".U 305 def rev8 = "b101_0001".U 306 def pack = "b101_0010".U 307 def orh48 = "b101_0011".U 308 309 def szewl1 = "b101_1000".U 310 def szewl2 = "b101_1001".U 311 def szewl3 = "b101_1010".U 312 def byte2 = "b101_1011".U 313 314 def andlsb = "b110_0000".U 315 def andzexth = "b110_0001".U 316 def orlsb = "b110_0010".U 317 def orzexth = "b110_0011".U 318 def xorlsb = "b110_0100".U 319 def xorzexth = "b110_0101".U 320 def orcblsb = "b110_0110".U 321 def orcbzexth = "b110_0111".U 322 323 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 324 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 325 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 326 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 327 def isBranch(func: UInt) = func(6, 4) === "b111".U 328 def getBranchType(func: UInt) = func(3, 2) 329 def isBranchInvert(func: UInt) = func(1) 330 331 def apply() = UInt(7.W) 332 } 333 334 object MDUOpType { 335 // mul 336 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 337 def mul = "b00000".U 338 def mulh = "b00001".U 339 def mulhsu = "b00010".U 340 def mulhu = "b00011".U 341 def mulw = "b00100".U 342 343 def mulw7 = "b01100".U 344 345 // div 346 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 347 def div = "b10000".U 348 def divu = "b10010".U 349 def rem = "b10001".U 350 def remu = "b10011".U 351 352 def divw = "b10100".U 353 def divuw = "b10110".U 354 def remw = "b10101".U 355 def remuw = "b10111".U 356 357 def isMul(op: UInt) = !op(4) 358 def isDiv(op: UInt) = op(4) 359 360 def isDivSign(op: UInt) = isDiv(op) && !op(1) 361 def isW(op: UInt) = op(2) 362 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 363 def getMulOp(op: UInt) = op(1, 0) 364 } 365 366 object LSUOpType { 367 // load pipeline 368 369 // normal load 370 // Note: bit(1, 0) are size, DO NOT CHANGE 371 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 372 def lb = "b0000".U 373 def lh = "b0001".U 374 def lw = "b0010".U 375 def ld = "b0011".U 376 def lbu = "b0100".U 377 def lhu = "b0101".U 378 def lwu = "b0110".U 379 380 // Zicbop software prefetch 381 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 382 def prefetch_i = "b1000".U // TODO 383 def prefetch_r = "b1001".U 384 def prefetch_w = "b1010".U 385 386 def isPrefetch(op: UInt): Bool = op(3) 387 388 // store pipeline 389 // normal store 390 // bit encoding: | store 00 | size(2bit) | 391 def sb = "b0000".U 392 def sh = "b0001".U 393 def sw = "b0010".U 394 def sd = "b0011".U 395 396 // l1 cache op 397 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 398 def cbo_zero = "b0111".U 399 400 // llc op 401 // bit encoding: | prefetch 11 | suboptype(2bit) | 402 def cbo_clean = "b1100".U 403 def cbo_flush = "b1101".U 404 def cbo_inval = "b1110".U 405 406 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 407 408 // atomics 409 // bit(1, 0) are size 410 // since atomics use a different fu type 411 // so we can safely reuse other load/store's encodings 412 // bit encoding: | optype(4bit) | size (2bit) | 413 def lr_w = "b000010".U 414 def sc_w = "b000110".U 415 def amoswap_w = "b001010".U 416 def amoadd_w = "b001110".U 417 def amoxor_w = "b010010".U 418 def amoand_w = "b010110".U 419 def amoor_w = "b011010".U 420 def amomin_w = "b011110".U 421 def amomax_w = "b100010".U 422 def amominu_w = "b100110".U 423 def amomaxu_w = "b101010".U 424 425 def lr_d = "b000011".U 426 def sc_d = "b000111".U 427 def amoswap_d = "b001011".U 428 def amoadd_d = "b001111".U 429 def amoxor_d = "b010011".U 430 def amoand_d = "b010111".U 431 def amoor_d = "b011011".U 432 def amomin_d = "b011111".U 433 def amomax_d = "b100011".U 434 def amominu_d = "b100111".U 435 def amomaxu_d = "b101011".U 436 437 def size(op: UInt) = op(1,0) 438 } 439 440 object BKUOpType { 441 442 def clmul = "b000000".U 443 def clmulh = "b000001".U 444 def clmulr = "b000010".U 445 def xpermn = "b000100".U 446 def xpermb = "b000101".U 447 448 def clz = "b001000".U 449 def clzw = "b001001".U 450 def ctz = "b001010".U 451 def ctzw = "b001011".U 452 def cpop = "b001100".U 453 def cpopw = "b001101".U 454 455 // 01xxxx is reserve 456 def aes64es = "b100000".U 457 def aes64esm = "b100001".U 458 def aes64ds = "b100010".U 459 def aes64dsm = "b100011".U 460 def aes64im = "b100100".U 461 def aes64ks1i = "b100101".U 462 def aes64ks2 = "b100110".U 463 464 // merge to two instruction sm4ks & sm4ed 465 def sm4ed0 = "b101000".U 466 def sm4ed1 = "b101001".U 467 def sm4ed2 = "b101010".U 468 def sm4ed3 = "b101011".U 469 def sm4ks0 = "b101100".U 470 def sm4ks1 = "b101101".U 471 def sm4ks2 = "b101110".U 472 def sm4ks3 = "b101111".U 473 474 def sha256sum0 = "b110000".U 475 def sha256sum1 = "b110001".U 476 def sha256sig0 = "b110010".U 477 def sha256sig1 = "b110011".U 478 def sha512sum0 = "b110100".U 479 def sha512sum1 = "b110101".U 480 def sha512sig0 = "b110110".U 481 def sha512sig1 = "b110111".U 482 483 def sm3p0 = "b111000".U 484 def sm3p1 = "b111001".U 485 } 486 487 object BTBtype { 488 def B = "b00".U // branch 489 def J = "b01".U // jump 490 def I = "b10".U // indirect 491 def R = "b11".U // return 492 493 def apply() = UInt(2.W) 494 } 495 496 object SelImm { 497 def IMM_X = "b0111".U 498 def IMM_S = "b0000".U 499 def IMM_SB = "b0001".U 500 def IMM_U = "b0010".U 501 def IMM_UJ = "b0011".U 502 def IMM_I = "b0100".U 503 def IMM_Z = "b0101".U 504 def INVALID_INSTR = "b0110".U 505 def IMM_B6 = "b1000".U 506 507 def X = BitPat("b????") 508 509 def apply() = UInt(4.W) 510 } 511 512 object ExceptionNO { 513 def instrAddrMisaligned = 0 514 def instrAccessFault = 1 515 def illegalInstr = 2 516 def breakPoint = 3 517 def loadAddrMisaligned = 4 518 def loadAccessFault = 5 519 def storeAddrMisaligned = 6 520 def storeAccessFault = 7 521 def ecallU = 8 522 def ecallS = 9 523 def ecallM = 11 524 def instrPageFault = 12 525 def loadPageFault = 13 526 // def singleStep = 14 527 def storePageFault = 15 528 def priorities = Seq( 529 breakPoint, // TODO: different BP has different priority 530 instrPageFault, 531 instrAccessFault, 532 illegalInstr, 533 instrAddrMisaligned, 534 ecallM, ecallS, ecallU, 535 storeAddrMisaligned, 536 loadAddrMisaligned, 537 storePageFault, 538 loadPageFault, 539 storeAccessFault, 540 loadAccessFault 541 ) 542 def all = priorities.distinct.sorted 543 def frontendSet = Seq( 544 instrAddrMisaligned, 545 instrAccessFault, 546 illegalInstr, 547 instrPageFault 548 ) 549 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 550 val new_vec = Wire(ExceptionVec()) 551 new_vec.foreach(_ := false.B) 552 select.foreach(i => new_vec(i) := vec(i)) 553 new_vec 554 } 555 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 556 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 557 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 558 partialSelect(vec, fuConfig.exceptionOut) 559 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 560 partialSelect(vec, exuConfig.exceptionOut) 561 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 562 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 563 } 564 565 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 566 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 567 def aluGen(p: Parameters) = new Alu()(p) 568 def bkuGen(p: Parameters) = new Bku()(p) 569 def jmpGen(p: Parameters) = new Jump()(p) 570 def fenceGen(p: Parameters) = new Fence()(p) 571 def csrGen(p: Parameters) = new CSR()(p) 572 def i2fGen(p: Parameters) = new IntToFP()(p) 573 def fmacGen(p: Parameters) = new FMA()(p) 574 def f2iGen(p: Parameters) = new FPToInt()(p) 575 def f2fGen(p: Parameters) = new FPToFP()(p) 576 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 577 def stdGen(p: Parameters) = new Std()(p) 578 def mouDataGen(p: Parameters) = new Std()(p) 579 580 def f2iSel(uop: MicroOp): Bool = { 581 uop.ctrl.rfWen 582 } 583 584 def i2fSel(uop: MicroOp): Bool = { 585 uop.ctrl.fpu.fromInt 586 } 587 588 def f2fSel(uop: MicroOp): Bool = { 589 val ctrl = uop.ctrl.fpu 590 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 591 } 592 593 def fdivSqrtSel(uop: MicroOp): Bool = { 594 val ctrl = uop.ctrl.fpu 595 ctrl.div || ctrl.sqrt 596 } 597 598 val aluCfg = FuConfig( 599 name = "alu", 600 fuGen = aluGen, 601 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 602 fuType = FuType.alu, 603 numIntSrc = 2, 604 numFpSrc = 0, 605 writeIntRf = true, 606 writeFpRf = false, 607 hasRedirect = true, 608 ) 609 610 val jmpCfg = FuConfig( 611 name = "jmp", 612 fuGen = jmpGen, 613 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 614 fuType = FuType.jmp, 615 numIntSrc = 1, 616 numFpSrc = 0, 617 writeIntRf = true, 618 writeFpRf = false, 619 hasRedirect = true, 620 ) 621 622 val fenceCfg = FuConfig( 623 name = "fence", 624 fuGen = fenceGen, 625 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 626 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 627 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 628 flushPipe = true 629 ) 630 631 val csrCfg = FuConfig( 632 name = "csr", 633 fuGen = csrGen, 634 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 635 fuType = FuType.csr, 636 numIntSrc = 1, 637 numFpSrc = 0, 638 writeIntRf = true, 639 writeFpRf = false, 640 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 641 flushPipe = true 642 ) 643 644 val i2fCfg = FuConfig( 645 name = "i2f", 646 fuGen = i2fGen, 647 fuSel = i2fSel, 648 FuType.i2f, 649 numIntSrc = 1, 650 numFpSrc = 0, 651 writeIntRf = false, 652 writeFpRf = true, 653 writeFflags = true, 654 latency = CertainLatency(2), 655 fastUopOut = true, fastImplemented = true 656 ) 657 658 val divCfg = FuConfig( 659 name = "div", 660 fuGen = dividerGen, 661 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 662 FuType.div, 663 2, 664 0, 665 writeIntRf = true, 666 writeFpRf = false, 667 latency = UncertainLatency(), 668 fastUopOut = true, 669 fastImplemented = true, 670 hasInputBuffer = (true, 4, true) 671 ) 672 673 val mulCfg = FuConfig( 674 name = "mul", 675 fuGen = multiplierGen, 676 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 677 FuType.mul, 678 2, 679 0, 680 writeIntRf = true, 681 writeFpRf = false, 682 latency = CertainLatency(2), 683 fastUopOut = true, 684 fastImplemented = true 685 ) 686 687 val bkuCfg = FuConfig( 688 name = "bku", 689 fuGen = bkuGen, 690 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 691 fuType = FuType.bku, 692 numIntSrc = 2, 693 numFpSrc = 0, 694 writeIntRf = true, 695 writeFpRf = false, 696 latency = CertainLatency(1), 697 fastUopOut = true, 698 fastImplemented = true 699 ) 700 701 val fmacCfg = FuConfig( 702 name = "fmac", 703 fuGen = fmacGen, 704 fuSel = _ => true.B, 705 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 706 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 707 ) 708 709 val f2iCfg = FuConfig( 710 name = "f2i", 711 fuGen = f2iGen, 712 fuSel = f2iSel, 713 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 714 fastUopOut = true, fastImplemented = true 715 ) 716 717 val f2fCfg = FuConfig( 718 name = "f2f", 719 fuGen = f2fGen, 720 fuSel = f2fSel, 721 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 722 fastUopOut = true, fastImplemented = true 723 ) 724 725 val fdivSqrtCfg = FuConfig( 726 name = "fdivSqrt", 727 fuGen = fdivSqrtGen, 728 fuSel = fdivSqrtSel, 729 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 730 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 731 ) 732 733 val lduCfg = FuConfig( 734 "ldu", 735 null, // DontCare 736 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 737 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 738 latency = UncertainLatency(), 739 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 740 flushPipe = true, 741 replayInst = true, 742 hasLoadError = true 743 ) 744 745 val staCfg = FuConfig( 746 "sta", 747 null, 748 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 749 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 750 latency = UncertainLatency(), 751 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 752 ) 753 754 val stdCfg = FuConfig( 755 "std", 756 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 757 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 758 ) 759 760 val mouCfg = FuConfig( 761 "mou", 762 null, 763 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 764 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 765 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 766 ) 767 768 val mouDataCfg = FuConfig( 769 "mou", 770 mouDataGen, 771 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 772 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 773 latency = UncertainLatency() 774 ) 775 776 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 777 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 778 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 779 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 780 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 781 val FmiscExeUnitCfg = ExuConfig( 782 "FmiscExeUnit", 783 "Fp", 784 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 785 Int.MaxValue, 1 786 ) 787 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 788 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 789 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 790} 791