1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19 20import chipsalliance.rocketchip.config.Parameters 21import freechips.rocketchip.tile.XLen 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 36 def isReg(srcType: UInt) = srcType===reg 37 def isPc(srcType: UInt) = srcType===pc 38 def isImm(srcType: UInt) = srcType===imm 39 def isFp(srcType: UInt) = srcType===fp 40 def isPcImm(srcType: UInt) = srcType(0) 41 def isRegFp(srcType: UInt) = !srcType(0) 42 43 def apply() = UInt(2.W) 44 } 45 46 object SrcState { 47 def busy = "b0".U 48 def rdy = "b1".U 49 // def specRdy = "b10".U // speculative ready, for future use 50 def apply() = UInt(1.W) 51 } 52 53 object FuType { 54 def jmp = "b0000".U 55 def i2f = "b0001".U 56 def csr = "b0010".U 57 def alu = "b0110".U 58 def mul = "b0100".U 59 def div = "b0101".U 60 def fence = "b0011".U 61 def bmu = "b0111".U 62 63 def fmac = "b1000".U 64 def fmisc = "b1011".U 65 def fDivSqrt = "b1010".U 66 67 def ldu = "b1100".U 68 def stu = "b1101".U 69 def mou = "b1111".U // for amo, lr, sc, fence 70 71 def num = 14 72 73 def apply() = UInt(log2Up(num).W) 74 75 def isIntExu(fuType: UInt) = !fuType(3) 76 def isJumpExu(fuType: UInt) = fuType === jmp 77 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 78 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 79 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 80 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 81 def isAMO(fuType: UInt) = fuType(1) 82 83 def jmpCanAccept(fuType: UInt) = !fuType(2) 84 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 85 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 86 87 def fmacCanAccept(fuType: UInt) = !fuType(1) 88 def fmiscCanAccept(fuType: UInt) = fuType(1) 89 90 def loadCanAccept(fuType: UInt) = !fuType(0) 91 def storeCanAccept(fuType: UInt) = fuType(0) 92 93 def storeIsAMO(fuType: UInt) = fuType(1) 94 95 val functionNameMap = Map( 96 jmp.litValue() -> "jmp", 97 i2f.litValue() -> "int to float", 98 csr.litValue() -> "csr", 99 alu.litValue() -> "alu", 100 mul.litValue() -> "mul", 101 div.litValue() -> "div", 102 fence.litValue() -> "fence", 103 fmac.litValue() -> "fmac", 104 fmisc.litValue() -> "fmisc", 105 fDivSqrt.litValue() -> "fdiv/fsqrt", 106 ldu.litValue() -> "load", 107 stu.litValue() -> "store" 108 ) 109 110 } 111 112 object FuOpType { 113 def apply() = UInt(8.W) 114 } 115 116 object CommitType { 117 def NORMAL = "b00".U // int/fp 118 def BRANCH = "b01".U // branch 119 def LOAD = "b10".U // load 120 def STORE = "b11".U // store 121 122 def apply() = UInt(2.W) 123 def isLoadStore(commitType: UInt) = commitType(1) 124 def lsInstIsStore(commitType: UInt) = commitType(0) 125 def isStore(commitType: UInt) = isLoadStore(commitType) && lsInstIsStore(commitType) 126 def isBranch(commitType: UInt) = commitType(0) && !commitType(1) 127 } 128 129 object RedirectLevel { 130 def flushAfter = "b0".U 131 def flush = "b1".U 132 133 def apply() = UInt(1.W) 134 // def isUnconditional(level: UInt) = level(1) 135 def flushItself(level: UInt) = level(0) 136 // def isException(level: UInt) = level(1) && level(0) 137 } 138 139 object ExceptionVec { 140 def apply() = Vec(16, Bool()) 141 } 142 143 object PMAMode { 144 def R = "b1".U << 0 //readable 145 def W = "b1".U << 1 //writeable 146 def X = "b1".U << 2 //executable 147 def I = "b1".U << 3 //cacheable: icache 148 def D = "b1".U << 4 //cacheable: dcache 149 def S = "b1".U << 5 //enable speculative access 150 def A = "b1".U << 6 //enable atomic operation, A imply R & W 151 def C = "b1".U << 7 //if it is cacheable is configable 152 def Reserved = "b0".U 153 154 def apply() = UInt(7.W) 155 156 def read(mode: UInt) = mode(0) 157 def write(mode: UInt) = mode(1) 158 def execute(mode: UInt) = mode(2) 159 def icache(mode: UInt) = mode(3) 160 def dcache(mode: UInt) = mode(4) 161 def speculate(mode: UInt) = mode(5) 162 def atomic(mode: UInt) = mode(6) 163 def configable_cache(mode: UInt) = mode(7) 164 165 def strToMode(s: String) = { 166 var result = 0.U(8.W) 167 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 168 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 169 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 170 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 171 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 172 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 173 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 174 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 175 result 176 } 177 } 178 179 180 object CSROpType { 181 def jmp = "b000".U 182 def wrt = "b001".U 183 def set = "b010".U 184 def clr = "b011".U 185 def wrti = "b101".U 186 def seti = "b110".U 187 def clri = "b111".U 188 } 189 190 // jump 191 object JumpOpType { 192 def jal = "b00".U 193 def jalr = "b01".U 194 def auipc = "b10".U 195// def call = "b11_011".U 196// def ret = "b11_100".U 197 def jumpOpisJalr(op: UInt) = op(0) 198 def jumpOpisAuipc(op: UInt) = op(1) 199 } 200 201 object FenceOpType { 202 def fence = "b10000".U 203 def sfence = "b10001".U 204 def fencei = "b10010".U 205 } 206 207 object ALUOpType { 208 // misc & branch optype 209 def and = "b0_00_00_000".U 210 def andn = "b0_00_00_001".U 211 def or = "b0_00_00_010".U 212 def orn = "b0_00_00_011".U 213 def xor = "b0_00_00_100".U 214 def xnor = "b0_00_00_101".U 215 def orh48 = "b0_00_00_110".U 216 217 def andlsb = "b0_00_11_000".U 218 def andnlsb = "b0_00_11_001".U 219 def orlsb = "b0_00_11_010".U 220 def ornlsb = "b0_00_11_011".U 221 def xorlsb = "b0_00_11_100".U 222 def xnorlsb = "b0_00_11_101".U 223 224 def sext_b = "b0_00_01_000".U 225 def sext_h = "b0_00_01_001".U 226 def zext_h = "b0_00_01_010".U 227 // TOOD: optimize it 228 def szewl1 = "b0_00_01_011".U 229 def orc_b = "b0_00_01_100".U 230 def rev8 = "b0_00_01_101".U 231 // TOOD: optimize it 232 def szewl2 = "b0_00_01_110".U 233 // TOOD: optimize it 234 def byte2 = "b0_00_01_111".U 235 236 def beq = "b0_00_10_000".U 237 def bne = "b0_00_10_001".U 238 def blt = "b0_00_10_100".U 239 def bge = "b0_00_10_101".U 240 def bltu = "b0_00_10_110".U 241 def bgeu = "b0_00_10_111".U 242 243 // add & sub optype 244 def add_uw = "b0_01_00_000".U 245 def add = "b0_01_00_001".U 246 def oddadd = "b0_01_10_001".U 247 def sh1add_uw = "b0_01_00_010".U 248 def sh1add = "b0_01_00_011".U 249 def sh2add_uw = "b0_01_00_100".U 250 def sh2add = "b0_01_00_101".U 251 def sh3add_uw = "b0_01_00_110".U 252 def sh3add = "b0_01_00_111".U 253 def sh4add = "b0_01_01_001".U 254 def sr30add = "b0_01_01_011".U 255 def sr31add = "b0_01_01_101".U 256 def sr32add = "b0_01_01_111".U 257 258 // shift optype 259 def slli_uw = "b0_10_00_000".U 260 def sll = "b0_10_00_001".U 261 def bclr = "b0_10_00_100".U 262 def bset = "b0_10_00_101".U 263 def binv = "b0_10_00_110".U 264 265 def srl = "b0_10_01_001".U 266 def bext = "b0_10_01_010".U 267 def sra = "b0_10_01_100".U 268 269 def rol = "b0_10_10_000".U 270 271 def ror = "b0_10_11_000".U 272 273 def sub = "b0_11_00_000".U 274 def sltu = "b0_11_00_001".U 275 def slt = "b0_11_00_010".U 276 def maxu = "b0_11_00_100".U 277 def minu = "b0_11_00_101".U 278 def max = "b0_11_00_110".U 279 def min = "b0_11_00_111".U 280 281 // RV64 32bit optype 282 def addw = "b1_01_00_001".U 283 def addwbyte = "b1_01_00_011".U 284 def addwbit = "b1_01_00_101".U 285 def oddaddw = "b1_01_10_001".U 286 def subw = "b1_11_00_000".U 287 def sllw = "b1_10_00_000".U 288 def srlw = "b1_10_01_001".U 289 def sraw = "b1_10_01_100".U 290 def rolw = "b1_10_10_000".U 291 def rorw = "b1_10_11_000".U 292 293 def isWordOp(func: UInt) = func(7) 294 def isAddw(func: UInt) = func(7, 5) === "b101".U 295 def isLogic(func: UInt) = func(7, 3) === "b00000".U 296 def logicToLSB(func: UInt) = Cat(func(7, 5), "b11".U(2.W), func(2, 0)) 297 def isBranch(func: UInt) = func(6, 3) === "b0010".U 298 def getBranchType(func: UInt) = func(2, 1) 299 def isBranchInvert(func: UInt) = func(0) 300 301 def apply() = UInt(8.W) 302 } 303 304 object MDUOpType { 305 // mul 306 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 307 def mul = "b00000".U 308 def mulh = "b00001".U 309 def mulhsu = "b00010".U 310 def mulhu = "b00011".U 311 def mulw = "b00100".U 312 313 def mulw7 = "b01100".U 314 315 // div 316 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 317 def div = "b10000".U 318 def divu = "b10010".U 319 def rem = "b10001".U 320 def remu = "b10011".U 321 322 def divw = "b10100".U 323 def divuw = "b10110".U 324 def remw = "b10101".U 325 def remuw = "b10111".U 326 327 def isMul(op: UInt) = !op(4) 328 def isDiv(op: UInt) = op(4) 329 330 def isDivSign(op: UInt) = isDiv(op) && !op(1) 331 def isW(op: UInt) = op(2) 332 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 333 def getMulOp(op: UInt) = op(1, 0) 334 } 335 336 object LSUOpType { 337 // normal load/store 338 // bit(1, 0) are size 339 def lb = "b000000".U 340 def lh = "b000001".U 341 def lw = "b000010".U 342 def ld = "b000011".U 343 def lbu = "b000100".U 344 def lhu = "b000101".U 345 def lwu = "b000110".U 346 def sb = "b001000".U 347 def sh = "b001001".U 348 def sw = "b001010".U 349 def sd = "b001011".U 350 351 def isLoad(op: UInt): Bool = !op(3) 352 def isStore(op: UInt): Bool = op(3) 353 354 // atomics 355 // bit(1, 0) are size 356 // since atomics use a different fu type 357 // so we can safely reuse other load/store's encodings 358 def lr_w = "b000010".U 359 def sc_w = "b000110".U 360 def amoswap_w = "b001010".U 361 def amoadd_w = "b001110".U 362 def amoxor_w = "b010010".U 363 def amoand_w = "b010110".U 364 def amoor_w = "b011010".U 365 def amomin_w = "b011110".U 366 def amomax_w = "b100010".U 367 def amominu_w = "b100110".U 368 def amomaxu_w = "b101010".U 369 370 def lr_d = "b000011".U 371 def sc_d = "b000111".U 372 def amoswap_d = "b001011".U 373 def amoadd_d = "b001111".U 374 def amoxor_d = "b010011".U 375 def amoand_d = "b010111".U 376 def amoor_d = "b011011".U 377 def amomin_d = "b011111".U 378 def amomax_d = "b100011".U 379 def amominu_d = "b100111".U 380 def amomaxu_d = "b101011".U 381 } 382 383 object BMUOpType { 384 385 def clmul = "b0000".U 386 def clmulh = "b0010".U 387 def clmulr = "b0100".U 388 389 def clz = "b1000".U 390 def clzw = "b1001".U 391 def ctz = "b1010".U 392 def ctzw = "b1011".U 393 def cpop = "b1100".U 394 def cpopw = "b1101".U 395 } 396 397 object BTBtype { 398 def B = "b00".U // branch 399 def J = "b01".U // jump 400 def I = "b10".U // indirect 401 def R = "b11".U // return 402 403 def apply() = UInt(2.W) 404 } 405 406 object SelImm { 407 def IMM_X = "b0111".U 408 def IMM_S = "b0000".U 409 def IMM_SB = "b0001".U 410 def IMM_U = "b0010".U 411 def IMM_UJ = "b0011".U 412 def IMM_I = "b0100".U 413 def IMM_Z = "b0101".U 414 def INVALID_INSTR = "b0110".U 415 def IMM_B6 = "b1000".U 416 417 def apply() = UInt(4.W) 418 } 419 420 def dividerGen(p: Parameters) = new SRT4Divider(p(XLen))(p) 421 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 422 def aluGen(p: Parameters) = new Alu()(p) 423 def bmuGen(p: Parameters) = new Bmu()(p) 424 def jmpGen(p: Parameters) = new Jump()(p) 425 def fenceGen(p: Parameters) = new Fence()(p) 426 def csrGen(p: Parameters) = new CSR()(p) 427 def i2fGen(p: Parameters) = new IntToFP()(p) 428 def fmacGen(p: Parameters) = new FMA()(p) 429 def f2iGen(p: Parameters) = new FPToInt()(p) 430 def f2fGen(p: Parameters) = new FPToFP()(p) 431 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 432 def stdGen(p: Parameters) = new Std()(p) 433 434 def f2iSel(uop: MicroOp): Bool = { 435 uop.ctrl.rfWen 436 } 437 438 def i2fSel(uop: MicroOp): Bool = { 439 uop.ctrl.fpu.fromInt 440 } 441 442 def f2fSel(uop: MicroOp): Bool = { 443 val ctrl = uop.ctrl.fpu 444 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 445 } 446 447 def fdivSqrtSel(uop: MicroOp): Bool = { 448 val ctrl = uop.ctrl.fpu 449 ctrl.div || ctrl.sqrt 450 } 451 452 val aluCfg = FuConfig( 453 name = "alu", 454 fuGen = aluGen, 455 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 456 fuType = FuType.alu, 457 numIntSrc = 2, 458 numFpSrc = 0, 459 writeIntRf = true, 460 writeFpRf = false, 461 hasRedirect = true, 462 ) 463 464 val jmpCfg = FuConfig( 465 name = "jmp", 466 fuGen = jmpGen, 467 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 468 fuType = FuType.jmp, 469 numIntSrc = 1, 470 numFpSrc = 0, 471 writeIntRf = true, 472 writeFpRf = false, 473 hasRedirect = true, 474 ) 475 476 val fenceCfg = FuConfig( 477 name = "fence", 478 fuGen = fenceGen, 479 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 480 FuType.fence, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 481 UncertainLatency() // TODO: need rewrite latency structure, not just this value 482 ) 483 484 val csrCfg = FuConfig( 485 name = "csr", 486 fuGen = csrGen, 487 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 488 fuType = FuType.csr, 489 numIntSrc = 1, 490 numFpSrc = 0, 491 writeIntRf = true, 492 writeFpRf = false, 493 hasRedirect = false 494 ) 495 496 val i2fCfg = FuConfig( 497 name = "i2f", 498 fuGen = i2fGen, 499 fuSel = i2fSel, 500 FuType.i2f, 501 numIntSrc = 1, 502 numFpSrc = 0, 503 writeIntRf = false, 504 writeFpRf = true, 505 hasRedirect = false, 506 latency = CertainLatency(2), 507 fastUopOut = true, fastImplemented = true 508 ) 509 510 val divCfg = FuConfig( 511 name = "div", 512 fuGen = dividerGen, 513 fuSel = (uop: MicroOp) => MDUOpType.isDiv(uop.ctrl.fuOpType), 514 FuType.div, 515 2, 516 0, 517 writeIntRf = true, 518 writeFpRf = false, 519 hasRedirect = false, 520 latency = UncertainLatency(), 521 fastUopOut = true, 522 fastImplemented = false 523 ) 524 525 val mulCfg = FuConfig( 526 name = "mul", 527 fuGen = multiplierGen, 528 fuSel = (uop: MicroOp) => MDUOpType.isMul(uop.ctrl.fuOpType), 529 FuType.mul, 530 2, 531 0, 532 writeIntRf = true, 533 writeFpRf = false, 534 hasRedirect = false, 535 latency = CertainLatency(2), 536 fastUopOut = true, 537 fastImplemented = true 538 ) 539 540 val bmuCfg = FuConfig( 541 name = "bmu", 542 fuGen = bmuGen, 543 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bmu, 544 fuType = FuType.bmu, 545 numIntSrc = 2, 546 numFpSrc = 0, 547 writeIntRf = true, 548 writeFpRf = false, 549 hasRedirect = false, 550 latency = CertainLatency(1), 551 fastUopOut = true, 552 fastImplemented = false 553 ) 554 555 val fmacCfg = FuConfig( 556 name = "fmac", 557 fuGen = fmacGen, 558 fuSel = _ => true.B, 559 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false, 560 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 561 ) 562 563 val f2iCfg = FuConfig( 564 name = "f2i", 565 fuGen = f2iGen, 566 fuSel = f2iSel, 567 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2), 568 fastUopOut = true, fastImplemented = true 569 ) 570 571 val f2fCfg = FuConfig( 572 name = "f2f", 573 fuGen = f2fGen, 574 fuSel = f2fSel, 575 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2), 576 fastUopOut = true, fastImplemented = true 577 ) 578 579 val fdivSqrtCfg = FuConfig( 580 name = "fdivSqrt", 581 fuGen = fdivSqrtGen, 582 fuSel = fdivSqrtSel, 583 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, UncertainLatency(), 584 fastUopOut = true, fastImplemented = false, hasInputBuffer = true 585 ) 586 587 val lduCfg = FuConfig( 588 "ldu", 589 null, // DontCare 590 null, 591 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false, 592 UncertainLatency() 593 ) 594 595 val staCfg = FuConfig( 596 "sta", 597 null, 598 null, 599 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 600 UncertainLatency() 601 ) 602 603 val stdCfg = FuConfig( 604 "std", 605 fuGen = stdGen, fuSel = _ => true.B, FuType.stu, 1, 1, 606 writeIntRf = false, writeFpRf = false, hasRedirect = false, latency = CertainLatency(1) 607 ) 608 609 val mouCfg = FuConfig( 610 "mou", 611 null, 612 null, 613 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 614 UncertainLatency() 615 ) 616 617 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 618 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 619 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 620 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bmuCfg), 1, Int.MaxValue) 621 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 622 val FmiscExeUnitCfg = ExuConfig( 623 "FmiscExeUnit", 624 "Fp", 625 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 626 Int.MaxValue, 1 627 ) 628 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0) 629 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 630 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue) 631} 632