1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 def X = BitPat("b??") 36 37 def isReg(srcType: UInt) = srcType===reg 38 def isPc(srcType: UInt) = srcType===pc 39 def isImm(srcType: UInt) = srcType===imm 40 def isFp(srcType: UInt) = srcType(1) 41 def isPcOrImm(srcType: UInt) = srcType(0) 42 def isRegOrFp(srcType: UInt) = !srcType(0) 43 def regIsFp(srcType: UInt) = srcType(1) 44 45 def apply() = UInt(2.W) 46 } 47 48 object SrcState { 49 def busy = "b0".U 50 def rdy = "b1".U 51 // def specRdy = "b10".U // speculative ready, for future use 52 def apply() = UInt(1.W) 53 } 54 55 object FuType { 56 def jmp = "b0000".U 57 def i2f = "b0001".U 58 def csr = "b0010".U 59 def alu = "b0110".U 60 def mul = "b0100".U 61 def div = "b0101".U 62 def fence = "b0011".U 63 def bku = "b0111".U 64 65 def fmac = "b1000".U 66 def fmisc = "b1011".U 67 def fDivSqrt = "b1010".U 68 69 def ldu = "b1100".U 70 def stu = "b1101".U 71 def mou = "b1111".U // for amo, lr, sc, fence 72 73 def X = BitPat("b????") 74 75 def num = 14 76 77 def apply() = UInt(log2Up(num).W) 78 79 def isIntExu(fuType: UInt) = !fuType(3) 80 def isJumpExu(fuType: UInt) = fuType === jmp 81 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 82 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 83 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 84 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 85 def isAMO(fuType: UInt) = fuType(1) 86 def isFence(fuType: UInt) = fuType === fence 87 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 88 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 89 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 90 91 92 def jmpCanAccept(fuType: UInt) = !fuType(2) 93 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 94 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 95 96 def fmacCanAccept(fuType: UInt) = !fuType(1) 97 def fmiscCanAccept(fuType: UInt) = fuType(1) 98 99 def loadCanAccept(fuType: UInt) = !fuType(0) 100 def storeCanAccept(fuType: UInt) = fuType(0) 101 102 def storeIsAMO(fuType: UInt) = fuType(1) 103 104 val functionNameMap = Map( 105 jmp.litValue() -> "jmp", 106 i2f.litValue() -> "int_to_float", 107 csr.litValue() -> "csr", 108 alu.litValue() -> "alu", 109 mul.litValue() -> "mul", 110 div.litValue() -> "div", 111 fence.litValue() -> "fence", 112 bku.litValue() -> "bku", 113 fmac.litValue() -> "fmac", 114 fmisc.litValue() -> "fmisc", 115 fDivSqrt.litValue() -> "fdiv_fsqrt", 116 ldu.litValue() -> "load", 117 stu.litValue() -> "store", 118 mou.litValue() -> "mou" 119 ) 120 } 121 122 object FuOpType { 123 def apply() = UInt(7.W) 124 def X = BitPat("b???????") 125 } 126 127 object CommitType { 128 def NORMAL = "b000".U // int/fp 129 def BRANCH = "b001".U // branch 130 def LOAD = "b010".U // load 131 def STORE = "b011".U // store 132 133 def apply() = UInt(3.W) 134 def isFused(commitType: UInt): Bool = commitType(2) 135 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 136 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 137 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 138 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 139 } 140 141 object RedirectLevel { 142 def flushAfter = "b0".U 143 def flush = "b1".U 144 145 def apply() = UInt(1.W) 146 // def isUnconditional(level: UInt) = level(1) 147 def flushItself(level: UInt) = level(0) 148 // def isException(level: UInt) = level(1) && level(0) 149 } 150 151 object ExceptionVec { 152 def apply() = Vec(16, Bool()) 153 } 154 155 object PMAMode { 156 def R = "b1".U << 0 //readable 157 def W = "b1".U << 1 //writeable 158 def X = "b1".U << 2 //executable 159 def I = "b1".U << 3 //cacheable: icache 160 def D = "b1".U << 4 //cacheable: dcache 161 def S = "b1".U << 5 //enable speculative access 162 def A = "b1".U << 6 //enable atomic operation, A imply R & W 163 def C = "b1".U << 7 //if it is cacheable is configable 164 def Reserved = "b0".U 165 166 def apply() = UInt(7.W) 167 168 def read(mode: UInt) = mode(0) 169 def write(mode: UInt) = mode(1) 170 def execute(mode: UInt) = mode(2) 171 def icache(mode: UInt) = mode(3) 172 def dcache(mode: UInt) = mode(4) 173 def speculate(mode: UInt) = mode(5) 174 def atomic(mode: UInt) = mode(6) 175 def configable_cache(mode: UInt) = mode(7) 176 177 def strToMode(s: String) = { 178 var result = 0.U(8.W) 179 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 180 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 181 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 182 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 183 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 184 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 185 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 186 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 187 result 188 } 189 } 190 191 192 object CSROpType { 193 def jmp = "b000".U 194 def wrt = "b001".U 195 def set = "b010".U 196 def clr = "b011".U 197 def wfi = "b100".U 198 def wrti = "b101".U 199 def seti = "b110".U 200 def clri = "b111".U 201 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 202 } 203 204 // jump 205 object JumpOpType { 206 def jal = "b00".U 207 def jalr = "b01".U 208 def auipc = "b10".U 209// def call = "b11_011".U 210// def ret = "b11_100".U 211 def jumpOpisJalr(op: UInt) = op(0) 212 def jumpOpisAuipc(op: UInt) = op(1) 213 } 214 215 object FenceOpType { 216 def fence = "b10000".U 217 def sfence = "b10001".U 218 def fencei = "b10010".U 219 def nofence= "b00000".U 220 } 221 222 object ALUOpType { 223 // shift optype 224 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 225 def sll = "b000_0001".U // sll: src1 << src2 226 227 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 228 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 229 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 230 231 def srl = "b000_0101".U // srl: src1 >> src2 232 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 233 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 234 235 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 236 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 237 238 // RV64 32bit optype 239 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 240 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 241 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 242 243 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 244 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 245 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 246 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 247 248 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 249 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 250 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 251 def rolw = "b001_1100".U 252 def rorw = "b001_1101".U 253 254 // ADD-op 255 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 256 def add = "b010_0001".U // add: src1 + src2 257 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 258 259 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 260 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 261 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 262 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 263 264 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 265 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 266 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 267 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 268 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 269 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 270 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 271 272 // SUB-op: src1 - src2 273 def sub = "b011_0000".U 274 def sltu = "b011_0001".U 275 def slt = "b011_0010".U 276 def maxu = "b011_0100".U 277 def minu = "b011_0101".U 278 def max = "b011_0110".U 279 def min = "b011_0111".U 280 281 // branch 282 def beq = "b111_0000".U 283 def bne = "b111_0010".U 284 def blt = "b111_1000".U 285 def bge = "b111_1010".U 286 def bltu = "b111_1100".U 287 def bgeu = "b111_1110".U 288 289 // misc optype 290 def and = "b100_0000".U 291 def andn = "b100_0001".U 292 def or = "b100_0010".U 293 def orn = "b100_0011".U 294 def xor = "b100_0100".U 295 def xnor = "b100_0101".U 296 def orcb = "b100_0110".U 297 298 def sextb = "b100_1000".U 299 def packh = "b100_1001".U 300 def sexth = "b100_1010".U 301 def packw = "b100_1011".U 302 303 def revb = "b101_0000".U 304 def rev8 = "b101_0001".U 305 def pack = "b101_0010".U 306 def orh48 = "b101_0011".U 307 308 def szewl1 = "b101_1000".U 309 def szewl2 = "b101_1001".U 310 def szewl3 = "b101_1010".U 311 def byte2 = "b101_1011".U 312 313 def andlsb = "b110_0000".U 314 def andzexth = "b110_0001".U 315 def orlsb = "b110_0010".U 316 def orzexth = "b110_0011".U 317 def xorlsb = "b110_0100".U 318 def xorzexth = "b110_0101".U 319 def orcblsb = "b110_0110".U 320 def orcbzexth = "b110_0111".U 321 322 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 323 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 324 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 325 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 326 def isBranch(func: UInt) = func(6, 4) === "b111".U 327 def getBranchType(func: UInt) = func(3, 2) 328 def isBranchInvert(func: UInt) = func(1) 329 330 def apply() = UInt(7.W) 331 } 332 333 object MDUOpType { 334 // mul 335 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 336 def mul = "b00000".U 337 def mulh = "b00001".U 338 def mulhsu = "b00010".U 339 def mulhu = "b00011".U 340 def mulw = "b00100".U 341 342 def mulw7 = "b01100".U 343 344 // div 345 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 346 def div = "b10000".U 347 def divu = "b10010".U 348 def rem = "b10001".U 349 def remu = "b10011".U 350 351 def divw = "b10100".U 352 def divuw = "b10110".U 353 def remw = "b10101".U 354 def remuw = "b10111".U 355 356 def isMul(op: UInt) = !op(4) 357 def isDiv(op: UInt) = op(4) 358 359 def isDivSign(op: UInt) = isDiv(op) && !op(1) 360 def isW(op: UInt) = op(2) 361 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 362 def getMulOp(op: UInt) = op(1, 0) 363 } 364 365 object LSUOpType { 366 // load pipeline 367 368 // normal load 369 // Note: bit(1, 0) are size, DO NOT CHANGE 370 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 371 def lb = "b0000".U 372 def lh = "b0001".U 373 def lw = "b0010".U 374 def ld = "b0011".U 375 def lbu = "b0100".U 376 def lhu = "b0101".U 377 def lwu = "b0110".U 378 379 // Zicbop software prefetch 380 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 381 def prefetch_i = "b1000".U // TODO 382 def prefetch_r = "b1001".U 383 def prefetch_w = "b1010".U 384 385 def isPrefetch(op: UInt): Bool = op(3) 386 387 // store pipeline 388 // normal store 389 // bit encoding: | store 00 | size(2bit) | 390 def sb = "b0000".U 391 def sh = "b0001".U 392 def sw = "b0010".U 393 def sd = "b0011".U 394 395 // l1 cache op 396 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 397 def cbo_zero = "b0111".U 398 399 // llc op 400 // bit encoding: | prefetch 11 | suboptype(2bit) | 401 def cbo_clean = "b1100".U 402 def cbo_flush = "b1101".U 403 def cbo_inval = "b1110".U 404 405 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 406 407 // atomics 408 // bit(1, 0) are size 409 // since atomics use a different fu type 410 // so we can safely reuse other load/store's encodings 411 // bit encoding: | optype(4bit) | size (2bit) | 412 def lr_w = "b000010".U 413 def sc_w = "b000110".U 414 def amoswap_w = "b001010".U 415 def amoadd_w = "b001110".U 416 def amoxor_w = "b010010".U 417 def amoand_w = "b010110".U 418 def amoor_w = "b011010".U 419 def amomin_w = "b011110".U 420 def amomax_w = "b100010".U 421 def amominu_w = "b100110".U 422 def amomaxu_w = "b101010".U 423 424 def lr_d = "b000011".U 425 def sc_d = "b000111".U 426 def amoswap_d = "b001011".U 427 def amoadd_d = "b001111".U 428 def amoxor_d = "b010011".U 429 def amoand_d = "b010111".U 430 def amoor_d = "b011011".U 431 def amomin_d = "b011111".U 432 def amomax_d = "b100011".U 433 def amominu_d = "b100111".U 434 def amomaxu_d = "b101011".U 435 436 def size(op: UInt) = op(1,0) 437 } 438 439 object BKUOpType { 440 441 def clmul = "b000000".U 442 def clmulh = "b000001".U 443 def clmulr = "b000010".U 444 def xpermn = "b000100".U 445 def xpermb = "b000101".U 446 447 def clz = "b001000".U 448 def clzw = "b001001".U 449 def ctz = "b001010".U 450 def ctzw = "b001011".U 451 def cpop = "b001100".U 452 def cpopw = "b001101".U 453 454 // 01xxxx is reserve 455 def aes64es = "b100000".U 456 def aes64esm = "b100001".U 457 def aes64ds = "b100010".U 458 def aes64dsm = "b100011".U 459 def aes64im = "b100100".U 460 def aes64ks1i = "b100101".U 461 def aes64ks2 = "b100110".U 462 463 // merge to two instruction sm4ks & sm4ed 464 def sm4ed0 = "b101000".U 465 def sm4ed1 = "b101001".U 466 def sm4ed2 = "b101010".U 467 def sm4ed3 = "b101011".U 468 def sm4ks0 = "b101100".U 469 def sm4ks1 = "b101101".U 470 def sm4ks2 = "b101110".U 471 def sm4ks3 = "b101111".U 472 473 def sha256sum0 = "b110000".U 474 def sha256sum1 = "b110001".U 475 def sha256sig0 = "b110010".U 476 def sha256sig1 = "b110011".U 477 def sha512sum0 = "b110100".U 478 def sha512sum1 = "b110101".U 479 def sha512sig0 = "b110110".U 480 def sha512sig1 = "b110111".U 481 482 def sm3p0 = "b111000".U 483 def sm3p1 = "b111001".U 484 } 485 486 object BTBtype { 487 def B = "b00".U // branch 488 def J = "b01".U // jump 489 def I = "b10".U // indirect 490 def R = "b11".U // return 491 492 def apply() = UInt(2.W) 493 } 494 495 object SelImm { 496 def IMM_X = "b0111".U 497 def IMM_S = "b0000".U 498 def IMM_SB = "b0001".U 499 def IMM_U = "b0010".U 500 def IMM_UJ = "b0011".U 501 def IMM_I = "b0100".U 502 def IMM_Z = "b0101".U 503 def INVALID_INSTR = "b0110".U 504 def IMM_B6 = "b1000".U 505 506 def X = BitPat("b????") 507 508 def apply() = UInt(4.W) 509 } 510 511 object ExceptionNO { 512 def instrAddrMisaligned = 0 513 def instrAccessFault = 1 514 def illegalInstr = 2 515 def breakPoint = 3 516 def loadAddrMisaligned = 4 517 def loadAccessFault = 5 518 def storeAddrMisaligned = 6 519 def storeAccessFault = 7 520 def ecallU = 8 521 def ecallS = 9 522 def ecallM = 11 523 def instrPageFault = 12 524 def loadPageFault = 13 525 // def singleStep = 14 526 def storePageFault = 15 527 def priorities = Seq( 528 breakPoint, // TODO: different BP has different priority 529 instrPageFault, 530 instrAccessFault, 531 illegalInstr, 532 instrAddrMisaligned, 533 ecallM, ecallS, ecallU, 534 storeAddrMisaligned, 535 loadAddrMisaligned, 536 storePageFault, 537 loadPageFault, 538 storeAccessFault, 539 loadAccessFault 540 ) 541 def all = priorities.distinct.sorted 542 def frontendSet = Seq( 543 instrAddrMisaligned, 544 instrAccessFault, 545 illegalInstr, 546 instrPageFault 547 ) 548 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 549 val new_vec = Wire(ExceptionVec()) 550 new_vec.foreach(_ := false.B) 551 select.foreach(i => new_vec(i) := vec(i)) 552 new_vec 553 } 554 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 555 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 556 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 557 partialSelect(vec, fuConfig.exceptionOut) 558 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 559 partialSelect(vec, exuConfig.exceptionOut) 560 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 561 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 562 } 563 564 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 565 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 566 def aluGen(p: Parameters) = new Alu()(p) 567 def bkuGen(p: Parameters) = new Bku()(p) 568 def jmpGen(p: Parameters) = new Jump()(p) 569 def fenceGen(p: Parameters) = new Fence()(p) 570 def csrGen(p: Parameters) = new CSR()(p) 571 def i2fGen(p: Parameters) = new IntToFP()(p) 572 def fmacGen(p: Parameters) = new FMA()(p) 573 def f2iGen(p: Parameters) = new FPToInt()(p) 574 def f2fGen(p: Parameters) = new FPToFP()(p) 575 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 576 def stdGen(p: Parameters) = new Std()(p) 577 def mouDataGen(p: Parameters) = new Std()(p) 578 579 def f2iSel(uop: MicroOp): Bool = { 580 uop.ctrl.rfWen 581 } 582 583 def i2fSel(uop: MicroOp): Bool = { 584 uop.ctrl.fpu.fromInt 585 } 586 587 def f2fSel(uop: MicroOp): Bool = { 588 val ctrl = uop.ctrl.fpu 589 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 590 } 591 592 def fdivSqrtSel(uop: MicroOp): Bool = { 593 val ctrl = uop.ctrl.fpu 594 ctrl.div || ctrl.sqrt 595 } 596 597 val aluCfg = FuConfig( 598 name = "alu", 599 fuGen = aluGen, 600 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 601 fuType = FuType.alu, 602 numIntSrc = 2, 603 numFpSrc = 0, 604 writeIntRf = true, 605 writeFpRf = false, 606 hasRedirect = true, 607 ) 608 609 val jmpCfg = FuConfig( 610 name = "jmp", 611 fuGen = jmpGen, 612 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 613 fuType = FuType.jmp, 614 numIntSrc = 1, 615 numFpSrc = 0, 616 writeIntRf = true, 617 writeFpRf = false, 618 hasRedirect = true, 619 ) 620 621 val fenceCfg = FuConfig( 622 name = "fence", 623 fuGen = fenceGen, 624 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 625 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 626 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 627 flushPipe = true 628 ) 629 630 val csrCfg = FuConfig( 631 name = "csr", 632 fuGen = csrGen, 633 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 634 fuType = FuType.csr, 635 numIntSrc = 1, 636 numFpSrc = 0, 637 writeIntRf = true, 638 writeFpRf = false, 639 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 640 flushPipe = true 641 ) 642 643 val i2fCfg = FuConfig( 644 name = "i2f", 645 fuGen = i2fGen, 646 fuSel = i2fSel, 647 FuType.i2f, 648 numIntSrc = 1, 649 numFpSrc = 0, 650 writeIntRf = false, 651 writeFpRf = true, 652 writeFflags = true, 653 latency = CertainLatency(2), 654 fastUopOut = true, fastImplemented = true 655 ) 656 657 val divCfg = FuConfig( 658 name = "div", 659 fuGen = dividerGen, 660 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 661 FuType.div, 662 2, 663 0, 664 writeIntRf = true, 665 writeFpRf = false, 666 latency = UncertainLatency(), 667 fastUopOut = true, 668 fastImplemented = true, 669 hasInputBuffer = (true, 4, true) 670 ) 671 672 val mulCfg = FuConfig( 673 name = "mul", 674 fuGen = multiplierGen, 675 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 676 FuType.mul, 677 2, 678 0, 679 writeIntRf = true, 680 writeFpRf = false, 681 latency = CertainLatency(2), 682 fastUopOut = true, 683 fastImplemented = true 684 ) 685 686 val bkuCfg = FuConfig( 687 name = "bku", 688 fuGen = bkuGen, 689 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 690 fuType = FuType.bku, 691 numIntSrc = 2, 692 numFpSrc = 0, 693 writeIntRf = true, 694 writeFpRf = false, 695 latency = CertainLatency(1), 696 fastUopOut = true, 697 fastImplemented = true 698 ) 699 700 val fmacCfg = FuConfig( 701 name = "fmac", 702 fuGen = fmacGen, 703 fuSel = _ => true.B, 704 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 705 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 706 ) 707 708 val f2iCfg = FuConfig( 709 name = "f2i", 710 fuGen = f2iGen, 711 fuSel = f2iSel, 712 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 713 fastUopOut = true, fastImplemented = true 714 ) 715 716 val f2fCfg = FuConfig( 717 name = "f2f", 718 fuGen = f2fGen, 719 fuSel = f2fSel, 720 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 721 fastUopOut = true, fastImplemented = true 722 ) 723 724 val fdivSqrtCfg = FuConfig( 725 name = "fdivSqrt", 726 fuGen = fdivSqrtGen, 727 fuSel = fdivSqrtSel, 728 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 729 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 730 ) 731 732 val lduCfg = FuConfig( 733 "ldu", 734 null, // DontCare 735 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 736 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 737 latency = UncertainLatency(), 738 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 739 flushPipe = true, 740 replayInst = true, 741 hasLoadError = true 742 ) 743 744 val staCfg = FuConfig( 745 "sta", 746 null, 747 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 748 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 749 latency = UncertainLatency(), 750 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 751 ) 752 753 val stdCfg = FuConfig( 754 "std", 755 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 756 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 757 ) 758 759 val mouCfg = FuConfig( 760 "mou", 761 null, 762 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 763 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 764 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 765 ) 766 767 val mouDataCfg = FuConfig( 768 "mou", 769 mouDataGen, 770 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 771 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 772 latency = UncertainLatency() 773 ) 774 775 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 776 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 777 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 778 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 779 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 780 val FmiscExeUnitCfg = ExuConfig( 781 "FmiscExeUnit", 782 "Fp", 783 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 784 Int.MaxValue, 1 785 ) 786 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 787 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 788 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 789} 790