1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 36 def isReg(srcType: UInt) = srcType===reg 37 def isPc(srcType: UInt) = srcType===pc 38 def isImm(srcType: UInt) = srcType===imm 39 def isFp(srcType: UInt) = srcType(1) 40 def isPcOrImm(srcType: UInt) = srcType(0) 41 def isRegOrFp(srcType: UInt) = !srcType(0) 42 def regIsFp(srcType: UInt) = srcType(1) 43 44 def apply() = UInt(2.W) 45 } 46 47 object SrcState { 48 def busy = "b0".U 49 def rdy = "b1".U 50 // def specRdy = "b10".U // speculative ready, for future use 51 def apply() = UInt(1.W) 52 } 53 54 object FuType { 55 def jmp = "b0000".U 56 def i2f = "b0001".U 57 def csr = "b0010".U 58 def alu = "b0110".U 59 def mul = "b0100".U 60 def div = "b0101".U 61 def fence = "b0011".U 62 def bku = "b0111".U 63 64 def fmac = "b1000".U 65 def fmisc = "b1011".U 66 def fDivSqrt = "b1010".U 67 68 def ldu = "b1100".U 69 def stu = "b1101".U 70 def mou = "b1111".U // for amo, lr, sc, fence 71 72 def num = 14 73 74 def apply() = UInt(log2Up(num).W) 75 76 def isIntExu(fuType: UInt) = !fuType(3) 77 def isJumpExu(fuType: UInt) = fuType === jmp 78 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 79 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 80 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 81 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 82 def isAMO(fuType: UInt) = fuType(1) 83 def isFence(fuType: UInt) = fuType === fence 84 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 85 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 86 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 87 88 89 def jmpCanAccept(fuType: UInt) = !fuType(2) 90 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 91 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 92 93 def fmacCanAccept(fuType: UInt) = !fuType(1) 94 def fmiscCanAccept(fuType: UInt) = fuType(1) 95 96 def loadCanAccept(fuType: UInt) = !fuType(0) 97 def storeCanAccept(fuType: UInt) = fuType(0) 98 99 def storeIsAMO(fuType: UInt) = fuType(1) 100 101 val functionNameMap = Map( 102 jmp.litValue() -> "jmp", 103 i2f.litValue() -> "int_to_float", 104 csr.litValue() -> "csr", 105 alu.litValue() -> "alu", 106 mul.litValue() -> "mul", 107 div.litValue() -> "div", 108 fence.litValue() -> "fence", 109 bku.litValue() -> "bku", 110 fmac.litValue() -> "fmac", 111 fmisc.litValue() -> "fmisc", 112 fDivSqrt.litValue() -> "fdiv/fsqrt", 113 ldu.litValue() -> "load", 114 stu.litValue() -> "store", 115 mou.litValue() -> "mou" 116 ) 117 } 118 119 object FuOpType { 120 def apply() = UInt(7.W) 121 } 122 123 object CommitType { 124 def NORMAL = "b000".U // int/fp 125 def BRANCH = "b001".U // branch 126 def LOAD = "b010".U // load 127 def STORE = "b011".U // store 128 129 def apply() = UInt(3.W) 130 def isFused(commitType: UInt): Bool = commitType(2) 131 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 132 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 133 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 134 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 135 } 136 137 object RedirectLevel { 138 def flushAfter = "b0".U 139 def flush = "b1".U 140 141 def apply() = UInt(1.W) 142 // def isUnconditional(level: UInt) = level(1) 143 def flushItself(level: UInt) = level(0) 144 // def isException(level: UInt) = level(1) && level(0) 145 } 146 147 object ExceptionVec { 148 def apply() = Vec(16, Bool()) 149 } 150 151 object PMAMode { 152 def R = "b1".U << 0 //readable 153 def W = "b1".U << 1 //writeable 154 def X = "b1".U << 2 //executable 155 def I = "b1".U << 3 //cacheable: icache 156 def D = "b1".U << 4 //cacheable: dcache 157 def S = "b1".U << 5 //enable speculative access 158 def A = "b1".U << 6 //enable atomic operation, A imply R & W 159 def C = "b1".U << 7 //if it is cacheable is configable 160 def Reserved = "b0".U 161 162 def apply() = UInt(7.W) 163 164 def read(mode: UInt) = mode(0) 165 def write(mode: UInt) = mode(1) 166 def execute(mode: UInt) = mode(2) 167 def icache(mode: UInt) = mode(3) 168 def dcache(mode: UInt) = mode(4) 169 def speculate(mode: UInt) = mode(5) 170 def atomic(mode: UInt) = mode(6) 171 def configable_cache(mode: UInt) = mode(7) 172 173 def strToMode(s: String) = { 174 var result = 0.U(8.W) 175 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 176 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 177 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 178 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 179 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 180 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 181 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 182 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 183 result 184 } 185 } 186 187 188 object CSROpType { 189 def jmp = "b000".U 190 def wrt = "b001".U 191 def set = "b010".U 192 def clr = "b011".U 193 def wrti = "b101".U 194 def seti = "b110".U 195 def clri = "b111".U 196 } 197 198 // jump 199 object JumpOpType { 200 def jal = "b00".U 201 def jalr = "b01".U 202 def auipc = "b10".U 203// def call = "b11_011".U 204// def ret = "b11_100".U 205 def jumpOpisJalr(op: UInt) = op(0) 206 def jumpOpisAuipc(op: UInt) = op(1) 207 } 208 209 object FenceOpType { 210 def fence = "b10000".U 211 def sfence = "b10001".U 212 def fencei = "b10010".U 213 def nofence= "b00000".U 214 } 215 216 object ALUOpType { 217 // shift optype 218 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 219 def sll = "b000_0001".U // sll: src1 << src2 220 221 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 222 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 223 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 224 225 def srl = "b000_0101".U // srl: src1 >> src2 226 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 227 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 228 229 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 230 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 231 232 // RV64 32bit optype 233 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 234 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 235 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 236 237 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 238 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 239 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 240 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 241 242 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 243 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 244 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 245 def rolw = "b001_1100".U 246 def rorw = "b001_1101".U 247 248 // ADD-op 249 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 250 def add = "b010_0001".U // add: src1 + src2 251 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 252 253 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 254 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 255 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 256 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 257 258 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 259 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 260 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 261 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 262 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 263 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 264 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 265 266 // SUB-op: src1 - src2 267 def sub = "b011_0000".U 268 def sltu = "b011_0001".U 269 def slt = "b011_0010".U 270 def maxu = "b011_0100".U 271 def minu = "b011_0101".U 272 def max = "b011_0110".U 273 def min = "b011_0111".U 274 275 // branch 276 def beq = "b111_0000".U 277 def bne = "b111_0010".U 278 def blt = "b111_1000".U 279 def bge = "b111_1010".U 280 def bltu = "b111_1100".U 281 def bgeu = "b111_1110".U 282 283 // misc optype 284 def and = "b100_0000".U 285 def andn = "b100_0001".U 286 def or = "b100_0010".U 287 def orn = "b100_0011".U 288 def xor = "b100_0100".U 289 def xnor = "b100_0101".U 290 def orcb = "b100_0110".U 291 292 def sextb = "b100_1000".U 293 def packh = "b100_1001".U 294 def sexth = "b100_1010".U 295 def packw = "b100_1011".U 296 297 def revb = "b101_0000".U 298 def rev8 = "b101_0001".U 299 def pack = "b101_0010".U 300 def orh48 = "b101_0011".U 301 302 def szewl1 = "b101_1000".U 303 def szewl2 = "b101_1001".U 304 def szewl3 = "b101_1010".U 305 def byte2 = "b101_1011".U 306 307 def andlsb = "b110_0000".U 308 def andzexth = "b110_0001".U 309 def orlsb = "b110_0010".U 310 def orzexth = "b110_0011".U 311 def xorlsb = "b110_0100".U 312 def xorzexth = "b110_0101".U 313 def orcblsb = "b110_0110".U 314 def orcbzexth = "b110_0111".U 315 316 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 317 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 318 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 319 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 320 def isBranch(func: UInt) = func(6, 4) === "b111".U 321 def getBranchType(func: UInt) = func(3, 2) 322 def isBranchInvert(func: UInt) = func(1) 323 324 def apply() = UInt(7.W) 325 } 326 327 object MDUOpType { 328 // mul 329 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 330 def mul = "b00000".U 331 def mulh = "b00001".U 332 def mulhsu = "b00010".U 333 def mulhu = "b00011".U 334 def mulw = "b00100".U 335 336 def mulw7 = "b01100".U 337 338 // div 339 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 340 def div = "b10000".U 341 def divu = "b10010".U 342 def rem = "b10001".U 343 def remu = "b10011".U 344 345 def divw = "b10100".U 346 def divuw = "b10110".U 347 def remw = "b10101".U 348 def remuw = "b10111".U 349 350 def isMul(op: UInt) = !op(4) 351 def isDiv(op: UInt) = op(4) 352 353 def isDivSign(op: UInt) = isDiv(op) && !op(1) 354 def isW(op: UInt) = op(2) 355 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 356 def getMulOp(op: UInt) = op(1, 0) 357 } 358 359 object LSUOpType { 360 // load pipeline 361 362 // normal load 363 // Note: bit(1, 0) are size, DO NOT CHANGE 364 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 365 def lb = "b0000".U 366 def lh = "b0001".U 367 def lw = "b0010".U 368 def ld = "b0011".U 369 def lbu = "b0100".U 370 def lhu = "b0101".U 371 def lwu = "b0110".U 372 373 // Zicbop software prefetch 374 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 375 def prefetch_i = "b1000".U // TODO 376 def prefetch_r = "b1001".U 377 def prefetch_w = "b1010".U 378 379 def isPrefetch(op: UInt): Bool = op(3) 380 381 // store pipeline 382 // normal store 383 // bit encoding: | store 00 | size(2bit) | 384 def sb = "b0000".U 385 def sh = "b0001".U 386 def sw = "b0010".U 387 def sd = "b0011".U 388 389 // l1 cache op 390 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 391 def cbo_zero = "b0111".U 392 393 // llc op 394 // bit encoding: | prefetch 11 | suboptype(2bit) | 395 def cbo_clean = "b1100".U 396 def cbo_flush = "b1101".U 397 def cbo_inval = "b1110".U 398 399 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 400 401 // atomics 402 // bit(1, 0) are size 403 // since atomics use a different fu type 404 // so we can safely reuse other load/store's encodings 405 // bit encoding: | optype(4bit) | size (2bit) | 406 def lr_w = "b000010".U 407 def sc_w = "b000110".U 408 def amoswap_w = "b001010".U 409 def amoadd_w = "b001110".U 410 def amoxor_w = "b010010".U 411 def amoand_w = "b010110".U 412 def amoor_w = "b011010".U 413 def amomin_w = "b011110".U 414 def amomax_w = "b100010".U 415 def amominu_w = "b100110".U 416 def amomaxu_w = "b101010".U 417 418 def lr_d = "b000011".U 419 def sc_d = "b000111".U 420 def amoswap_d = "b001011".U 421 def amoadd_d = "b001111".U 422 def amoxor_d = "b010011".U 423 def amoand_d = "b010111".U 424 def amoor_d = "b011011".U 425 def amomin_d = "b011111".U 426 def amomax_d = "b100011".U 427 def amominu_d = "b100111".U 428 def amomaxu_d = "b101011".U 429 430 def size(op: UInt) = op(1,0) 431 } 432 433 object BKUOpType { 434 435 def clmul = "b000000".U 436 def clmulh = "b000001".U 437 def clmulr = "b000010".U 438 def xpermn = "b000100".U 439 def xpermb = "b000101".U 440 441 def clz = "b001000".U 442 def clzw = "b001001".U 443 def ctz = "b001010".U 444 def ctzw = "b001011".U 445 def cpop = "b001100".U 446 def cpopw = "b001101".U 447 448 // 01xxxx is reserve 449 def aes64es = "b100000".U 450 def aes64esm = "b100001".U 451 def aes64ds = "b100010".U 452 def aes64dsm = "b100011".U 453 def aes64im = "b100100".U 454 def aes64ks1i = "b100101".U 455 def aes64ks2 = "b100110".U 456 457 // merge to two instruction sm4ks & sm4ed 458 def sm4ed0 = "b101000".U 459 def sm4ed1 = "b101001".U 460 def sm4ed2 = "b101010".U 461 def sm4ed3 = "b101011".U 462 def sm4ks0 = "b101100".U 463 def sm4ks1 = "b101101".U 464 def sm4ks2 = "b101110".U 465 def sm4ks3 = "b101111".U 466 467 def sha256sum0 = "b110000".U 468 def sha256sum1 = "b110001".U 469 def sha256sig0 = "b110010".U 470 def sha256sig1 = "b110011".U 471 def sha512sum0 = "b110100".U 472 def sha512sum1 = "b110101".U 473 def sha512sig0 = "b110110".U 474 def sha512sig1 = "b110111".U 475 476 def sm3p0 = "b111000".U 477 def sm3p1 = "b111001".U 478 } 479 480 object BTBtype { 481 def B = "b00".U // branch 482 def J = "b01".U // jump 483 def I = "b10".U // indirect 484 def R = "b11".U // return 485 486 def apply() = UInt(2.W) 487 } 488 489 object SelImm { 490 def IMM_X = "b0111".U 491 def IMM_S = "b0000".U 492 def IMM_SB = "b0001".U 493 def IMM_U = "b0010".U 494 def IMM_UJ = "b0011".U 495 def IMM_I = "b0100".U 496 def IMM_Z = "b0101".U 497 def INVALID_INSTR = "b0110".U 498 def IMM_B6 = "b1000".U 499 500 def apply() = UInt(4.W) 501 } 502 503 object ExceptionNO { 504 def instrAddrMisaligned = 0 505 def instrAccessFault = 1 506 def illegalInstr = 2 507 def breakPoint = 3 508 def loadAddrMisaligned = 4 509 def loadAccessFault = 5 510 def storeAddrMisaligned = 6 511 def storeAccessFault = 7 512 def ecallU = 8 513 def ecallS = 9 514 def ecallM = 11 515 def instrPageFault = 12 516 def loadPageFault = 13 517 // def singleStep = 14 518 def storePageFault = 15 519 def priorities = Seq( 520 breakPoint, // TODO: different BP has different priority 521 instrPageFault, 522 instrAccessFault, 523 illegalInstr, 524 instrAddrMisaligned, 525 ecallM, ecallS, ecallU, 526 storePageFault, 527 loadPageFault, 528 storeAccessFault, 529 loadAccessFault, 530 storeAddrMisaligned, 531 loadAddrMisaligned 532 ) 533 def all = priorities.distinct.sorted 534 def frontendSet = Seq( 535 instrAddrMisaligned, 536 instrAccessFault, 537 illegalInstr, 538 instrPageFault 539 ) 540 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 541 val new_vec = Wire(ExceptionVec()) 542 new_vec.foreach(_ := false.B) 543 select.foreach(i => new_vec(i) := vec(i)) 544 new_vec 545 } 546 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 547 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 548 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 549 partialSelect(vec, fuConfig.exceptionOut) 550 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 551 partialSelect(vec, exuConfig.exceptionOut) 552 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 553 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 554 } 555 556 def dividerGen(p: Parameters) = new SRT16Divider(p(XLen))(p) 557 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 558 def aluGen(p: Parameters) = new Alu()(p) 559 def bkuGen(p: Parameters) = new Bku()(p) 560 def jmpGen(p: Parameters) = new Jump()(p) 561 def fenceGen(p: Parameters) = new Fence()(p) 562 def csrGen(p: Parameters) = new CSR()(p) 563 def i2fGen(p: Parameters) = new IntToFP()(p) 564 def fmacGen(p: Parameters) = new FMA()(p) 565 def f2iGen(p: Parameters) = new FPToInt()(p) 566 def f2fGen(p: Parameters) = new FPToFP()(p) 567 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 568 def stdGen(p: Parameters) = new Std()(p) 569 def mouDataGen(p: Parameters) = new Std()(p) 570 571 def f2iSel(uop: MicroOp): Bool = { 572 uop.ctrl.rfWen 573 } 574 575 def i2fSel(uop: MicroOp): Bool = { 576 uop.ctrl.fpu.fromInt 577 } 578 579 def f2fSel(uop: MicroOp): Bool = { 580 val ctrl = uop.ctrl.fpu 581 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 582 } 583 584 def fdivSqrtSel(uop: MicroOp): Bool = { 585 val ctrl = uop.ctrl.fpu 586 ctrl.div || ctrl.sqrt 587 } 588 589 val aluCfg = FuConfig( 590 name = "alu", 591 fuGen = aluGen, 592 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 593 fuType = FuType.alu, 594 numIntSrc = 2, 595 numFpSrc = 0, 596 writeIntRf = true, 597 writeFpRf = false, 598 hasRedirect = true, 599 ) 600 601 val jmpCfg = FuConfig( 602 name = "jmp", 603 fuGen = jmpGen, 604 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 605 fuType = FuType.jmp, 606 numIntSrc = 1, 607 numFpSrc = 0, 608 writeIntRf = true, 609 writeFpRf = false, 610 hasRedirect = true, 611 ) 612 613 val fenceCfg = FuConfig( 614 name = "fence", 615 fuGen = fenceGen, 616 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 617 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 618 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr) // TODO: need rewrite latency structure, not just this value, 619 ) 620 621 val csrCfg = FuConfig( 622 name = "csr", 623 fuGen = csrGen, 624 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 625 fuType = FuType.csr, 626 numIntSrc = 1, 627 numFpSrc = 0, 628 writeIntRf = true, 629 writeFpRf = false, 630 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 631 flushPipe = true 632 ) 633 634 val i2fCfg = FuConfig( 635 name = "i2f", 636 fuGen = i2fGen, 637 fuSel = i2fSel, 638 FuType.i2f, 639 numIntSrc = 1, 640 numFpSrc = 0, 641 writeIntRf = false, 642 writeFpRf = true, 643 writeFflags = true, 644 latency = CertainLatency(2), 645 fastUopOut = true, fastImplemented = true 646 ) 647 648 val divCfg = FuConfig( 649 name = "div", 650 fuGen = dividerGen, 651 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 652 FuType.div, 653 2, 654 0, 655 writeIntRf = true, 656 writeFpRf = false, 657 latency = UncertainLatency(), 658 fastUopOut = true, 659 fastImplemented = true 660 ) 661 662 val mulCfg = FuConfig( 663 name = "mul", 664 fuGen = multiplierGen, 665 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 666 FuType.mul, 667 2, 668 0, 669 writeIntRf = true, 670 writeFpRf = false, 671 latency = CertainLatency(2), 672 fastUopOut = true, 673 fastImplemented = true 674 ) 675 676 val bkuCfg = FuConfig( 677 name = "bku", 678 fuGen = bkuGen, 679 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 680 fuType = FuType.bku, 681 numIntSrc = 2, 682 numFpSrc = 0, 683 writeIntRf = true, 684 writeFpRf = false, 685 latency = CertainLatency(1), 686 fastUopOut = true, 687 fastImplemented = true 688 ) 689 690 val fmacCfg = FuConfig( 691 name = "fmac", 692 fuGen = fmacGen, 693 fuSel = _ => true.B, 694 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 695 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 696 ) 697 698 val f2iCfg = FuConfig( 699 name = "f2i", 700 fuGen = f2iGen, 701 fuSel = f2iSel, 702 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 703 fastUopOut = true, fastImplemented = true 704 ) 705 706 val f2fCfg = FuConfig( 707 name = "f2f", 708 fuGen = f2fGen, 709 fuSel = f2fSel, 710 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 711 fastUopOut = true, fastImplemented = true 712 ) 713 714 val fdivSqrtCfg = FuConfig( 715 name = "fdivSqrt", 716 fuGen = fdivSqrtGen, 717 fuSel = fdivSqrtSel, 718 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 719 fastUopOut = true, fastImplemented = true, hasInputBuffer = true 720 ) 721 722 val lduCfg = FuConfig( 723 "ldu", 724 null, // DontCare 725 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 726 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 727 latency = UncertainLatency(), 728 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 729 flushPipe = true, 730 replayInst = true 731 ) 732 733 val staCfg = FuConfig( 734 "sta", 735 null, 736 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 737 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 738 latency = UncertainLatency(), 739 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 740 ) 741 742 val stdCfg = FuConfig( 743 "std", 744 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 745 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 746 ) 747 748 val mouCfg = FuConfig( 749 "mou", 750 null, 751 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 752 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 753 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 754 ) 755 756 val mouDataCfg = FuConfig( 757 "mou", 758 mouDataGen, 759 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 760 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 761 latency = UncertainLatency() 762 ) 763 764 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 765 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 766 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 767 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 768 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 769 val FmiscExeUnitCfg = ExuConfig( 770 "FmiscExeUnit", 771 "Fp", 772 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 773 Int.MaxValue, 1 774 ) 775 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 776 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 777 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 778} 779