1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.fu.vector._ 25import xiangshan.backend.issue._ 26import xiangshan.backend.fu.FuConfig 27import xiangshan.backend.decode.{Imm, ImmUnion} 28 29package object xiangshan { 30 object SrcType { 31 def imm = "b000".U 32 def pc = "b000".U 33 def xp = "b001".U 34 def fp = "b010".U 35 def vp = "b100".U 36 def no = "b000".U // this src read no reg but cannot be Any value 37 38 // alias 39 def reg = this.xp 40 def DC = imm // Don't Care 41 def X = BitPat("b000") 42 43 def isPc(srcType: UInt) = srcType===pc 44 def isImm(srcType: UInt) = srcType===imm 45 def isReg(srcType: UInt) = srcType(0) 46 def isXp(srcType: UInt) = srcType(0) 47 def isFp(srcType: UInt) = srcType(1) 48 def isVp(srcType: UInt) = srcType(2) 49 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 50 def isNotReg(srcType: UInt): Bool = !srcType.orR 51 def isVfp(srcType: UInt) = isVp(srcType) || isFp(srcType) 52 def apply() = UInt(3.W) 53 } 54 55 object SrcState { 56 def busy = "b0".U 57 def rdy = "b1".U 58 // def specRdy = "b10".U // speculative ready, for future use 59 def apply() = UInt(1.W) 60 61 def isReady(state: UInt): Bool = state === this.rdy 62 def isBusy(state: UInt): Bool = state === this.busy 63 } 64 65 def FuOpTypeWidth = 9 66 object FuOpType { 67 def apply() = UInt(FuOpTypeWidth.W) 68 def X = BitPat("b0_0000_0000") 69 def FMVXF = BitPat("b1_1000_0000") //for fmv_x_d & fmv_x_w 70 } 71 72 object VlduType { 73 // bit encoding: | vector or scala (2bit) || mop (2bit) | lumop(5bit) | 74 // only unit-stride use lumop 75 // mop [1:0] 76 // 0 0 : unit-stride 77 // 0 1 : indexed-unordered 78 // 1 0 : strided 79 // 1 1 : indexed-ordered 80 // lumop[4:0] 81 // 0 0 0 0 0 : unit-stride load 82 // 0 1 0 0 0 : unit-stride, whole register load 83 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 84 // 1 0 0 0 0 : unit-stride fault-only-first 85 def vle = "b01_00_00000".U 86 def vlr = "b01_00_01000".U // whole 87 def vlm = "b01_00_01011".U // mask 88 def vleff = "b01_00_10000".U 89 def vluxe = "b01_01_00000".U // index 90 def vlse = "b01_10_00000".U // strided 91 def vloxe = "b01_11_00000".U // index 92 93 def isWhole (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01000".U 94 def isMasked (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01011".U 95 def isStrided(fuOpType: UInt): Bool = fuOpType(6, 5) === "b10".U 96 def isIndexed(fuOpType: UInt): Bool = fuOpType(5) 97 def isVecLd (fuOpType: UInt): Bool = fuOpType(8, 7) === "b01".U 98 } 99 100 object VstuType { 101 // bit encoding: | padding (2bit) || mop (2bit) | sumop(5bit) | 102 // only unit-stride use sumop 103 // mop [1:0] 104 // 0 0 : unit-stride 105 // 0 1 : indexed-unordered 106 // 1 0 : strided 107 // 1 1 : indexed-ordered 108 // sumop[4:0] 109 // 0 0 0 0 0 : unit-stride load 110 // 0 1 0 0 0 : unit-stride, whole register load 111 // 0 1 0 1 1 : unit-stride, mask load, EEW=8 112 def vse = "b10_00_00000".U 113 def vsr = "b10_00_01000".U // whole 114 def vsm = "b10_00_01011".U // mask 115 def vsuxe = "b10_01_00000".U // index 116 def vsse = "b10_10_00000".U // strided 117 def vsoxe = "b10_11_00000".U // index 118 119 def isWhole (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01000".U 120 def isMasked (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01011".U 121 def isStrided(fuOpType: UInt): Bool = fuOpType(6, 5) === "b10".U 122 def isIndexed(fuOpType: UInt): Bool = fuOpType(5) 123 def isVecSt (fuOpType: UInt): Bool = fuOpType(8, 7) === "b10".U 124 } 125 126 object IF2VectorType { 127 // use last 2 bits for vsew 128 def iDup2Vec = "b1_00".U 129 def fDup2Vec = "b1_01".U 130 def immDup2Vec = "b1_10".U 131 def i2Vec = "b0_00".U 132 def f2Vec = "b0_01".U 133 def imm2Vec = "b0_10".U 134 def needDup(bits: UInt): Bool = bits(2) 135 def isImm(bits: UInt): Bool = bits(1) 136 def isFp(bits: UInt): Bool = bits(0) 137 def isFmv(bits: UInt): Bool = bits(0) & !bits(2) 138 def FMX_D_X = "b0_01_11".U 139 def FMX_W_X = "b0_01_10".U 140 } 141 142 object CommitType { 143 def NORMAL = "b000".U // int/fp 144 def BRANCH = "b001".U // branch 145 def LOAD = "b010".U // load 146 def STORE = "b011".U // store 147 148 def apply() = UInt(3.W) 149 def isFused(commitType: UInt): Bool = commitType(2) 150 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 151 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 152 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 153 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 154 } 155 156 object RedirectLevel { 157 def flushAfter = "b0".U 158 def flush = "b1".U 159 160 def apply() = UInt(1.W) 161 // def isUnconditional(level: UInt) = level(1) 162 def flushItself(level: UInt) = level(0) 163 // def isException(level: UInt) = level(1) && level(0) 164 } 165 166 object ExceptionVec { 167 val ExceptionVecSize = 24 168 def apply() = Vec(ExceptionVecSize, Bool()) 169 } 170 171 object PMAMode { 172 def R = "b1".U << 0 //readable 173 def W = "b1".U << 1 //writeable 174 def X = "b1".U << 2 //executable 175 def I = "b1".U << 3 //cacheable: icache 176 def D = "b1".U << 4 //cacheable: dcache 177 def S = "b1".U << 5 //enable speculative access 178 def A = "b1".U << 6 //enable atomic operation, A imply R & W 179 def C = "b1".U << 7 //if it is cacheable is configable 180 def Reserved = "b0".U 181 182 def apply() = UInt(7.W) 183 184 def read(mode: UInt) = mode(0) 185 def write(mode: UInt) = mode(1) 186 def execute(mode: UInt) = mode(2) 187 def icache(mode: UInt) = mode(3) 188 def dcache(mode: UInt) = mode(4) 189 def speculate(mode: UInt) = mode(5) 190 def atomic(mode: UInt) = mode(6) 191 def configable_cache(mode: UInt) = mode(7) 192 193 def strToMode(s: String) = { 194 var result = 0.U(8.W) 195 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 196 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 197 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 198 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 199 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 200 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 201 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 202 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 203 result 204 } 205 } 206 207 208 object CSROpType { 209 def jmp = "b000".U 210 def wrt = "b001".U 211 def set = "b010".U 212 def clr = "b011".U 213 def wfi = "b100".U 214 def wrti = "b101".U 215 def seti = "b110".U 216 def clri = "b111".U 217 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 218 } 219 220 // jump 221 object JumpOpType { 222 def jal = "b00".U 223 def jalr = "b01".U 224 def auipc = "b10".U 225// def call = "b11_011".U 226// def ret = "b11_100".U 227 def jumpOpisJalr(op: UInt) = op(0) 228 def jumpOpisAuipc(op: UInt) = op(1) 229 } 230 231 object FenceOpType { 232 def fence = "b10000".U 233 def sfence = "b10001".U 234 def fencei = "b10010".U 235 def hfence_v = "b10011".U 236 def hfence_g = "b10100".U 237 def nofence= "b00000".U 238 } 239 240 object ALUOpType { 241 // shift optype 242 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 243 def sll = "b000_0001".U // sll: src1 << src2 244 245 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 246 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 247 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 248 249 def srl = "b000_0101".U // srl: src1 >> src2 250 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 251 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 252 253 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 254 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 255 256 // RV64 32bit optype 257 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 258 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 259 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 260 def lui32addw = "b001_0011".U // lui32addw: SEXT(SEXT(src2[11:0], 32) + {src2[31:12], 12'b0}, 64) 261 262 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 263 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 264 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 265 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 266 267 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 268 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 269 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 270 def rolw = "b001_1100".U 271 def rorw = "b001_1101".U 272 273 // ADD-op 274 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 275 def add = "b010_0001".U // add: src1 + src2 276 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 277 def lui32add = "b010_0011".U // lui32add: SEXT(src2[11:0]) + {src2[63:12], 12'b0} 278 279 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 280 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 281 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 282 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 283 284 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 285 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 286 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 287 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 288 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 289 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 290 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 291 292 // SUB-op: src1 - src2 293 def sub = "b011_0000".U 294 def sltu = "b011_0001".U 295 def slt = "b011_0010".U 296 def maxu = "b011_0100".U 297 def minu = "b011_0101".U 298 def max = "b011_0110".U 299 def min = "b011_0111".U 300 301 // branch 302 def beq = "b111_0000".U 303 def bne = "b111_0010".U 304 def blt = "b111_1000".U 305 def bge = "b111_1010".U 306 def bltu = "b111_1100".U 307 def bgeu = "b111_1110".U 308 309 // Zicond 310 def czero_eqz = "b111_0100".U 311 def czero_nez = "b111_0110".U 312 313 // misc optype 314 def and = "b100_0000".U 315 def andn = "b100_0001".U 316 def or = "b100_0010".U 317 def orn = "b100_0011".U 318 def xor = "b100_0100".U 319 def xnor = "b100_0101".U 320 def orcb = "b100_0110".U 321 322 def sextb = "b100_1000".U 323 def packh = "b100_1001".U 324 def sexth = "b100_1010".U 325 def packw = "b100_1011".U 326 327 def revb = "b101_0000".U 328 def rev8 = "b101_0001".U 329 def pack = "b101_0010".U 330 def orh48 = "b101_0011".U 331 332 def szewl1 = "b101_1000".U 333 def szewl2 = "b101_1001".U 334 def szewl3 = "b101_1010".U 335 def byte2 = "b101_1011".U 336 337 def andlsb = "b110_0000".U 338 def andzexth = "b110_0001".U 339 def orlsb = "b110_0010".U 340 def orzexth = "b110_0011".U 341 def xorlsb = "b110_0100".U 342 def xorzexth = "b110_0101".U 343 def orcblsb = "b110_0110".U 344 def orcbzexth = "b110_0111".U 345 346 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 347 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 348 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 349 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 350 351 def apply() = UInt(FuOpTypeWidth.W) 352 } 353 354 object VSETOpType { 355 val setVlmaxBit = 0 356 val keepVlBit = 1 357 // destTypeBit == 0: write vl to rd 358 // destTypeBit == 1: write vconfig 359 val destTypeBit = 5 360 361 // vsetvli's uop 362 // rs1!=x0, normal 363 // uop0: r(rs1), w(vconfig) | x[rs1],vtypei -> vconfig 364 // uop1: r(rs1), w(rd) | x[rs1],vtypei -> x[rd] 365 def uvsetvcfg_xi = "b1010_0000".U 366 def uvsetrd_xi = "b1000_0000".U 367 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 368 // uop0: w(vconfig) | vlmax, vtypei -> vconfig 369 // uop1: w(rd) | vlmax, vtypei -> x[rd] 370 def uvsetvcfg_vlmax_i = "b1010_0001".U 371 def uvsetrd_vlmax_i = "b1000_0001".U 372 // rs1==x0, rd==x0, keep vl, set vtype 373 // uop0: r(vconfig), w(vconfig) | ld_vconfig.vl, vtypei -> vconfig 374 def uvsetvcfg_keep_v = "b1010_0010".U 375 376 // vsetvl's uop 377 // rs1!=x0, normal 378 // uop0: r(rs1,rs2), w(vconfig) | x[rs1],x[rs2] -> vconfig 379 // uop1: r(rs1,rs2), w(rd) | x[rs1],x[rs2] -> x[rd] 380 def uvsetvcfg_xx = "b0110_0000".U 381 def uvsetrd_xx = "b0100_0000".U 382 // rs1==x0, rd!=x0, set vl to vlmax, set rd to vlmax, set vtype 383 // uop0: r(rs2), w(vconfig) | vlmax, vtypei -> vconfig 384 // uop1: r(rs2), w(rd) | vlmax, vtypei -> x[rd] 385 def uvsetvcfg_vlmax_x = "b0110_0001".U 386 def uvsetrd_vlmax_x = "b0100_0001".U 387 // rs1==x0, rd==x0, keep vl, set vtype 388 // uop0: r(rs2), w(vtmp) | x[rs2] -> vtmp 389 // uop0: r(vconfig,vtmp), w(vconfig) | old_vconfig.vl, vtmp -> vconfig 390 def uvmv_v_x = "b0110_0010".U 391 def uvsetvcfg_vv = "b0111_0010".U 392 393 // vsetivli's uop 394 // uop0: w(vconfig) | vli, vtypei -> vconfig 395 // uop1: w(rd) | vli, vtypei -> x[rd] 396 def uvsetvcfg_ii = "b0010_0000".U 397 def uvsetrd_ii = "b0000_0000".U 398 399 def isVsetvl (func: UInt) = func(6) 400 def isVsetvli (func: UInt) = func(7) 401 def isVsetivli(func: UInt) = func(7, 6) === 0.U 402 def isNormal (func: UInt) = func(1, 0) === 0.U 403 def isSetVlmax(func: UInt) = func(setVlmaxBit) 404 def isKeepVl (func: UInt) = func(keepVlBit) 405 // RG: region 406 def writeIntRG(func: UInt) = !func(5) 407 def writeVecRG(func: UInt) = func(5) 408 def readIntRG (func: UInt) = !func(4) 409 def readVecRG (func: UInt) = func(4) 410 // modify fuOpType 411 def keepVl(func: UInt) = func | (1 << keepVlBit).U 412 def setVlmax(func: UInt) = func | (1 << setVlmaxBit).U 413 } 414 415 object BRUOpType { 416 // branch 417 def beq = "b000_000".U 418 def bne = "b000_001".U 419 def blt = "b000_100".U 420 def bge = "b000_101".U 421 def bltu = "b001_000".U 422 def bgeu = "b001_001".U 423 424 def getBranchType(func: UInt) = func(3, 1) 425 def isBranchInvert(func: UInt) = func(0) 426 } 427 428 object MULOpType { 429 // mul 430 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 431 def mul = "b00000".U 432 def mulh = "b00001".U 433 def mulhsu = "b00010".U 434 def mulhu = "b00011".U 435 def mulw = "b00100".U 436 437 def mulw7 = "b01100".U 438 def isSign(op: UInt) = !op(1) 439 def isW(op: UInt) = op(2) 440 def isH(op: UInt) = op(1, 0) =/= 0.U 441 def getOp(op: UInt) = Cat(op(3), op(1, 0)) 442 } 443 444 object DIVOpType { 445 // div 446 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 447 def div = "b10000".U 448 def divu = "b10010".U 449 def rem = "b10001".U 450 def remu = "b10011".U 451 452 def divw = "b10100".U 453 def divuw = "b10110".U 454 def remw = "b10101".U 455 def remuw = "b10111".U 456 457 def isSign(op: UInt) = !op(1) 458 def isW(op: UInt) = op(2) 459 def isH(op: UInt) = op(0) 460 } 461 462 object MDUOpType { 463 // mul 464 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 465 def mul = "b00000".U 466 def mulh = "b00001".U 467 def mulhsu = "b00010".U 468 def mulhu = "b00011".U 469 def mulw = "b00100".U 470 471 def mulw7 = "b01100".U 472 473 // div 474 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 475 def div = "b10000".U 476 def divu = "b10010".U 477 def rem = "b10001".U 478 def remu = "b10011".U 479 480 def divw = "b10100".U 481 def divuw = "b10110".U 482 def remw = "b10101".U 483 def remuw = "b10111".U 484 485 def isMul(op: UInt) = !op(4) 486 def isDiv(op: UInt) = op(4) 487 488 def isDivSign(op: UInt) = isDiv(op) && !op(1) 489 def isW(op: UInt) = op(2) 490 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 491 def getMulOp(op: UInt) = op(1, 0) 492 } 493 494 object LSUOpType { 495 // load pipeline 496 497 // normal load 498 // Note: bit(1, 0) are size, DO NOT CHANGE 499 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 500 def lb = "b0000".U 501 def lh = "b0001".U 502 def lw = "b0010".U 503 def ld = "b0011".U 504 def lbu = "b0100".U 505 def lhu = "b0101".U 506 def lwu = "b0110".U 507 // hypervior load 508 // bit encoding: | hlvx 1 | hlv 1 | load 0 | is unsigned(1bit) | size(2bit) | 509 def hlvb = "b10000".U 510 def hlvh = "b10001".U 511 def hlvw = "b10010".U 512 def hlvd = "b10011".U 513 def hlvbu = "b10100".U 514 def hlvhu = "b10101".U 515 def hlvwu = "b10110".U 516 def hlvxhu = "b110101".U 517 def hlvxwu = "b110110".U 518 def isHlv(op: UInt): Bool = op(4) 519 def isHlvx(op: UInt): Bool = op(5) 520 521 // Zicbop software prefetch 522 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 523 def prefetch_i = "b1000".U // TODO 524 def prefetch_r = "b1001".U 525 def prefetch_w = "b1010".U 526 527 def isPrefetch(op: UInt): Bool = op(3) 528 529 // store pipeline 530 // normal store 531 // bit encoding: | store 00 | size(2bit) | 532 def sb = "b0000".U 533 def sh = "b0001".U 534 def sw = "b0010".U 535 def sd = "b0011".U 536 537 //hypervisor store 538 // bit encoding: |hsv 1 | store 00 | size(2bit) | 539 def hsvb = "b10000".U 540 def hsvh = "b10001".U 541 def hsvw = "b10010".U 542 def hsvd = "b10011".U 543 def isHsv(op: UInt): Bool = op(4) 544 545 // l1 cache op 546 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 547 def cbo_zero = "b0111".U 548 549 // llc op 550 // bit encoding: | prefetch 11 | suboptype(2bit) | 551 def cbo_clean = "b1100".U 552 def cbo_flush = "b1101".U 553 def cbo_inval = "b1110".U 554 555 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 556 557 // atomics 558 // bit(1, 0) are size 559 // since atomics use a different fu type 560 // so we can safely reuse other load/store's encodings 561 // bit encoding: | optype(4bit) | size (2bit) | 562 def lr_w = "b000010".U 563 def sc_w = "b000110".U 564 def amoswap_w = "b001010".U 565 def amoadd_w = "b001110".U 566 def amoxor_w = "b010010".U 567 def amoand_w = "b010110".U 568 def amoor_w = "b011010".U 569 def amomin_w = "b011110".U 570 def amomax_w = "b100010".U 571 def amominu_w = "b100110".U 572 def amomaxu_w = "b101010".U 573 574 def lr_d = "b000011".U 575 def sc_d = "b000111".U 576 def amoswap_d = "b001011".U 577 def amoadd_d = "b001111".U 578 def amoxor_d = "b010011".U 579 def amoand_d = "b010111".U 580 def amoor_d = "b011011".U 581 def amomin_d = "b011111".U 582 def amomax_d = "b100011".U 583 def amominu_d = "b100111".U 584 def amomaxu_d = "b101011".U 585 586 def size(op: UInt) = op(1,0) 587 588 def getVecLSMop(fuOpType: UInt): UInt = fuOpType(6, 5) 589 590 def isVecLd(fuOpType: UInt): Bool = fuOpType(8, 7) === "b01".U 591 def isVecSt(fuOpType: UInt): Bool = fuOpType(8, 7) === "b10".U 592 def isVecLS(fuOpType: UInt): Bool = fuOpType(8, 7).orR 593 594 def isUStride(fuOpType: UInt): Bool = fuOpType(6, 0) === "b00_00000".U 595 def isWhole (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01000".U 596 def isMasked (fuOpType: UInt): Bool = fuOpType(6, 5) === "b00".U && fuOpType(4, 0) === "b01011".U 597 def isStrided(fuOpType: UInt): Bool = fuOpType(6, 5) === "b10".U 598 def isIndexed(fuOpType: UInt): Bool = fuOpType(5) 599 } 600 601 object BKUOpType { 602 603 def clmul = "b000000".U 604 def clmulh = "b000001".U 605 def clmulr = "b000010".U 606 def xpermn = "b000100".U 607 def xpermb = "b000101".U 608 609 def clz = "b001000".U 610 def clzw = "b001001".U 611 def ctz = "b001010".U 612 def ctzw = "b001011".U 613 def cpop = "b001100".U 614 def cpopw = "b001101".U 615 616 // 01xxxx is reserve 617 def aes64es = "b100000".U 618 def aes64esm = "b100001".U 619 def aes64ds = "b100010".U 620 def aes64dsm = "b100011".U 621 def aes64im = "b100100".U 622 def aes64ks1i = "b100101".U 623 def aes64ks2 = "b100110".U 624 625 // merge to two instruction sm4ks & sm4ed 626 def sm4ed0 = "b101000".U 627 def sm4ed1 = "b101001".U 628 def sm4ed2 = "b101010".U 629 def sm4ed3 = "b101011".U 630 def sm4ks0 = "b101100".U 631 def sm4ks1 = "b101101".U 632 def sm4ks2 = "b101110".U 633 def sm4ks3 = "b101111".U 634 635 def sha256sum0 = "b110000".U 636 def sha256sum1 = "b110001".U 637 def sha256sig0 = "b110010".U 638 def sha256sig1 = "b110011".U 639 def sha512sum0 = "b110100".U 640 def sha512sum1 = "b110101".U 641 def sha512sig0 = "b110110".U 642 def sha512sig1 = "b110111".U 643 644 def sm3p0 = "b111000".U 645 def sm3p1 = "b111001".U 646 } 647 648 object BTBtype { 649 def B = "b00".U // branch 650 def J = "b01".U // jump 651 def I = "b10".U // indirect 652 def R = "b11".U // return 653 654 def apply() = UInt(2.W) 655 } 656 657 object SelImm { 658 def IMM_X = "b0111".U 659 def IMM_S = "b1110".U 660 def IMM_SB = "b0001".U 661 def IMM_U = "b0010".U 662 def IMM_UJ = "b0011".U 663 def IMM_I = "b0100".U 664 def IMM_Z = "b0101".U 665 def INVALID_INSTR = "b0110".U 666 def IMM_B6 = "b1000".U 667 668 def IMM_OPIVIS = "b1001".U 669 def IMM_OPIVIU = "b1010".U 670 def IMM_VSETVLI = "b1100".U 671 def IMM_VSETIVLI = "b1101".U 672 def IMM_LUI32 = "b1011".U 673 def IMM_VRORVI = "b1111".U 674 675 def X = BitPat("b0000") 676 677 def apply() = UInt(4.W) 678 679 def mkString(immType: UInt) : String = { 680 val strMap = Map( 681 IMM_S.litValue -> "S", 682 IMM_SB.litValue -> "SB", 683 IMM_U.litValue -> "U", 684 IMM_UJ.litValue -> "UJ", 685 IMM_I.litValue -> "I", 686 IMM_Z.litValue -> "Z", 687 IMM_B6.litValue -> "B6", 688 IMM_OPIVIS.litValue -> "VIS", 689 IMM_OPIVIU.litValue -> "VIU", 690 IMM_VSETVLI.litValue -> "VSETVLI", 691 IMM_VSETIVLI.litValue -> "VSETIVLI", 692 IMM_LUI32.litValue -> "LUI32", 693 IMM_VRORVI.litValue -> "VRORVI", 694 INVALID_INSTR.litValue -> "INVALID", 695 ) 696 strMap(immType.litValue) 697 } 698 699 def getImmUnion(immType: UInt) : Imm = { 700 val iuMap = Map( 701 IMM_S.litValue -> ImmUnion.S, 702 IMM_SB.litValue -> ImmUnion.B, 703 IMM_U.litValue -> ImmUnion.U, 704 IMM_UJ.litValue -> ImmUnion.J, 705 IMM_I.litValue -> ImmUnion.I, 706 IMM_Z.litValue -> ImmUnion.Z, 707 IMM_B6.litValue -> ImmUnion.B6, 708 IMM_OPIVIS.litValue -> ImmUnion.OPIVIS, 709 IMM_OPIVIU.litValue -> ImmUnion.OPIVIU, 710 IMM_VSETVLI.litValue -> ImmUnion.VSETVLI, 711 IMM_VSETIVLI.litValue -> ImmUnion.VSETIVLI, 712 IMM_LUI32.litValue -> ImmUnion.LUI32, 713 IMM_VRORVI.litValue -> ImmUnion.VRORVI, 714 ) 715 iuMap(immType.litValue) 716 } 717 } 718 719 object UopSplitType { 720 def SCA_SIM = "b000000".U // 721 def VSET = "b010001".U // dirty: vset 722 def VEC_VVV = "b010010".U // VEC_VVV 723 def VEC_VXV = "b010011".U // VEC_VXV 724 def VEC_0XV = "b010100".U // VEC_0XV 725 def VEC_VVW = "b010101".U // VEC_VVW 726 def VEC_WVW = "b010110".U // VEC_WVW 727 def VEC_VXW = "b010111".U // VEC_VXW 728 def VEC_WXW = "b011000".U // VEC_WXW 729 def VEC_WVV = "b011001".U // VEC_WVV 730 def VEC_WXV = "b011010".U // VEC_WXV 731 def VEC_EXT2 = "b011011".U // VF2 0 -> V 732 def VEC_EXT4 = "b011100".U // VF4 0 -> V 733 def VEC_EXT8 = "b011101".U // VF8 0 -> V 734 def VEC_VVM = "b011110".U // VEC_VVM 735 def VEC_VXM = "b011111".U // VEC_VXM 736 def VEC_SLIDE1UP = "b100000".U // vslide1up.vx 737 def VEC_FSLIDE1UP = "b100001".U // vfslide1up.vf 738 def VEC_SLIDE1DOWN = "b100010".U // vslide1down.vx 739 def VEC_FSLIDE1DOWN = "b100011".U // vfslide1down.vf 740 def VEC_VRED = "b100100".U // VEC_VRED 741 def VEC_SLIDEUP = "b100101".U // VEC_SLIDEUP 742 def VEC_SLIDEDOWN = "b100111".U // VEC_SLIDEDOWN 743 def VEC_M0X = "b101001".U // VEC_M0X 0MV 744 def VEC_MVV = "b101010".U // VEC_MVV VMV 745 def VEC_M0X_VFIRST = "b101011".U // 746 def VEC_VWW = "b101100".U // 747 def VEC_RGATHER = "b101101".U // vrgather.vv, vrgather.vi 748 def VEC_RGATHER_VX = "b101110".U // vrgather.vx 749 def VEC_RGATHEREI16 = "b101111".U // vrgatherei16.vv 750 def VEC_COMPRESS = "b110000".U // vcompress.vm 751 def VEC_US_LDST = "b110001".U // vector unit-strided load/store 752 def VEC_S_LDST = "b110010".U // vector strided load/store 753 def VEC_I_LDST = "b110011".U // vector indexed load/store 754 def VEC_VFV = "b111000".U // VEC_VFV 755 def VEC_VFW = "b111001".U // VEC_VFW 756 def VEC_WFW = "b111010".U // VEC_WVW 757 def VEC_VFM = "b111011".U // VEC_VFM 758 def VEC_VFRED = "b111100".U // VEC_VFRED 759 def VEC_VFREDOSUM = "b111101".U // VEC_VFREDOSUM 760 def VEC_M0M = "b000000".U // VEC_M0M 761 def VEC_MMM = "b000000".U // VEC_MMM 762 def VEC_MVNR = "b000100".U // vmvnr 763 def dummy = "b111111".U 764 765 def X = BitPat("b000000") 766 767 def apply() = UInt(6.W) 768 def needSplit(UopSplitType: UInt) = UopSplitType(4) || UopSplitType(5) 769 } 770 771 object ExceptionNO { 772 def instrAddrMisaligned = 0 773 def instrAccessFault = 1 774 def illegalInstr = 2 775 def breakPoint = 3 776 def loadAddrMisaligned = 4 777 def loadAccessFault = 5 778 def storeAddrMisaligned = 6 779 def storeAccessFault = 7 780 def ecallU = 8 781 def ecallS = 9 782 def ecallVS = 10 783 def ecallM = 11 784 def instrPageFault = 12 785 def loadPageFault = 13 786 // def singleStep = 14 787 def storePageFault = 15 788 def instrGuestPageFault = 20 789 def loadGuestPageFault = 21 790 def virtualInstr = 22 791 def storeGuestPageFault = 23 792 def priorities = Seq( 793 breakPoint, // TODO: different BP has different priority 794 instrPageFault, 795 instrGuestPageFault, 796 instrAccessFault, 797 illegalInstr, 798 virtualInstr, 799 instrAddrMisaligned, 800 ecallM, ecallS, ecallVS, ecallU, 801 storeAddrMisaligned, 802 loadAddrMisaligned, 803 storePageFault, 804 loadPageFault, 805 storeGuestPageFault, 806 loadGuestPageFault, 807 storeAccessFault, 808 loadAccessFault 809 ) 810 def all = priorities.distinct.sorted 811 def frontendSet = Seq( 812 instrAddrMisaligned, 813 instrAccessFault, 814 illegalInstr, 815 instrPageFault, 816 instrGuestPageFault, 817 virtualInstr 818 ) 819 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 820 val new_vec = Wire(ExceptionVec()) 821 new_vec.foreach(_ := false.B) 822 select.foreach(i => new_vec(i) := vec(i)) 823 new_vec 824 } 825 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 826 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 827 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 828 partialSelect(vec, fuConfig.exceptionOut) 829 } 830 831 object TopDownCounters extends Enumeration { 832 val NoStall = Value("NoStall") // Base 833 // frontend 834 val OverrideBubble = Value("OverrideBubble") 835 val FtqUpdateBubble = Value("FtqUpdateBubble") 836 // val ControlRedirectBubble = Value("ControlRedirectBubble") 837 val TAGEMissBubble = Value("TAGEMissBubble") 838 val SCMissBubble = Value("SCMissBubble") 839 val ITTAGEMissBubble = Value("ITTAGEMissBubble") 840 val RASMissBubble = Value("RASMissBubble") 841 val MemVioRedirectBubble = Value("MemVioRedirectBubble") 842 val OtherRedirectBubble = Value("OtherRedirectBubble") 843 val FtqFullStall = Value("FtqFullStall") 844 845 val ICacheMissBubble = Value("ICacheMissBubble") 846 val ITLBMissBubble = Value("ITLBMissBubble") 847 val BTBMissBubble = Value("BTBMissBubble") 848 val FetchFragBubble = Value("FetchFragBubble") 849 850 // backend 851 // long inst stall at rob head 852 val DivStall = Value("DivStall") // int div, float div/sqrt 853 val IntNotReadyStall = Value("IntNotReadyStall") // int-inst at rob head not issue 854 val FPNotReadyStall = Value("FPNotReadyStall") // fp-inst at rob head not issue 855 val MemNotReadyStall = Value("MemNotReadyStall") // mem-inst at rob head not issue 856 // freelist full 857 val IntFlStall = Value("IntFlStall") 858 val FpFlStall = Value("FpFlStall") 859 val VecFlStall = Value("VecFlStall") 860 // dispatch queue full 861 val IntDqStall = Value("IntDqStall") 862 val FpDqStall = Value("FpDqStall") 863 val LsDqStall = Value("LsDqStall") 864 865 // memblock 866 val LoadTLBStall = Value("LoadTLBStall") 867 val LoadL1Stall = Value("LoadL1Stall") 868 val LoadL2Stall = Value("LoadL2Stall") 869 val LoadL3Stall = Value("LoadL3Stall") 870 val LoadMemStall = Value("LoadMemStall") 871 val StoreStall = Value("StoreStall") // include store tlb miss 872 val AtomicStall = Value("AtomicStall") // atomic, load reserved, store conditional 873 874 // xs replay (different to gem5) 875 val LoadVioReplayStall = Value("LoadVioReplayStall") 876 val LoadMSHRReplayStall = Value("LoadMSHRReplayStall") 877 878 // bad speculation 879 val ControlRecoveryStall = Value("ControlRecoveryStall") 880 val MemVioRecoveryStall = Value("MemVioRecoveryStall") 881 val OtherRecoveryStall = Value("OtherRecoveryStall") 882 883 val FlushedInsts = Value("FlushedInsts") // control flushed, memvio flushed, others 884 885 val OtherCoreStall = Value("OtherCoreStall") 886 887 val NumStallReasons = Value("NumStallReasons") 888 } 889} 890