1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.rob.RobPtr 27import xiangshan.backend.Bundles._ 28import xiangshan.mem._ 29import xiangshan.backend.fu.vector.Bundles._ 30import xiangshan.backend.fu.FuConfig._ 31import xiangshan.backend.fu.FuType 32 33 34class VSplitPipeline(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 35 val io = IO(new VSplitPipelineIO(isVStore)) 36 // will be override later 37 def us_whole_reg(fuOpType: UInt): Bool = false.B 38 def us_mask(fuOpType: UInt): Bool = false.B 39 def us_fof(fuOpType: UInt): Bool = false.B 40 //TODO vdIdxReg should no longer be useful, don't delete it for now 41 val vdIdxReg = RegInit(0.U(3.W)) 42 43 val s1_ready = WireInit(false.B) 44 io.in.ready := s1_ready 45 46 /**----------------------------------------------------------- 47 * s0 stage 48 * decode and generate AlignedType, uop mask, preIsSplit 49 * ---------------------------------------------------------- 50 */ 51 val s0_uop = io.in.bits.uop 52 val s0_vtype = s0_uop.vpu.vtype 53 val s0_sew = s0_vtype.vsew 54 val s0_eew = s0_uop.vpu.veew 55 val s0_lmul = s0_vtype.vlmul 56 // when load whole register or unit-stride masked , emul should be 1 57 val s0_fuOpType = s0_uop.fuOpType 58 val s0_mop = s0_fuOpType(6, 5) 59 val s0_nf = Mux(us_whole_reg(s0_fuOpType), 0.U, s0_uop.vpu.nf) 60 val s0_vm = s0_uop.vpu.vm 61 val s0_emul = Mux(us_whole_reg(s0_fuOpType) ,GenUSWholeEmul(s0_uop.vpu.nf), Mux(us_mask(s0_fuOpType), 0.U(mulBits.W), EewLog2(s0_eew) - s0_sew + s0_lmul)) 62 val s0_preIsSplit = !isUnitStride(s0_mop) 63 val s0_nfield = s0_nf +& 1.U 64 65 val s0_valid = Wire(Bool()) 66 val s0_kill = io.in.bits.uop.robIdx.needFlush(io.redirect) 67 val s0_can_go = s1_ready 68 val s0_fire = s0_valid && s0_can_go 69 val s0_out = Wire(new VLSBundle(isVStore)) 70 71 val isUsWholeReg = isUnitStride(s0_mop) && us_whole_reg(s0_fuOpType) 72 val isMaskReg = isUnitStride(s0_mop) && us_mask(s0_fuOpType) 73 val isSegment = s0_nf =/= 0.U && !us_whole_reg(s0_fuOpType) 74 val instType = Cat(isSegment, s0_mop) 75 val uopIdx = io.in.bits.uop.vpu.vuopIdx 76 val uopIdxInField = GenUopIdxInField(instType, s0_emul, s0_lmul, uopIdx) 77 val vdIdxInField = GenVdIdxInField(instType, s0_emul, s0_lmul, uopIdxInField) 78 val lmulLog2 = Mux(s0_lmul.asSInt >= 0.S, 0.U, s0_lmul) 79 val emulLog2 = Mux(s0_emul.asSInt >= 0.S, 0.U, s0_emul) 80 val numEewLog2 = emulLog2 - EewLog2(s0_eew) 81 val numSewLog2 = lmulLog2 - s0_sew 82 val numFlowsSameVdLog2 = Mux( 83 isIndexed(instType), 84 log2Up(VLENB).U - s0_sew(1,0), 85 log2Up(VLENB).U - s0_eew 86 ) 87 // numUops = nf * max(lmul, emul) 88 val lmulLog2Pos = Mux(s0_lmul.asSInt < 0.S, 0.U, s0_lmul) 89 val emulLog2Pos = Mux(s0_emul.asSInt < 0.S, 0.U, s0_emul) 90 val numUops = Mux( 91 isIndexed(s0_mop) && s0_lmul.asSInt > s0_emul.asSInt, 92 (s0_nf +& 1.U) << lmulLog2Pos, 93 (s0_nf +& 1.U) << emulLog2Pos 94 ) 95 96 val vvl = io.in.bits.src_vl.asTypeOf(VConfig()).vl 97 val evl = Mux(isUsWholeReg, 98 GenUSWholeRegVL(io.in.bits.uop.vpu.nf +& 1.U, s0_eew), 99 Mux(isMaskReg, 100 GenUSMaskRegVL(vvl), 101 vvl)) 102 val vvstart = io.in.bits.uop.vpu.vstart 103 val alignedType = Mux(isIndexed(instType), s0_sew(1, 0), s0_eew) 104 val broadenAligendType = Mux(s0_preIsSplit, Cat("b0".U, alignedType), "b100".U) // if is unit-stride, use 128-bits memory access 105 val flowsLog2 = GenRealFlowLog2(instType, s0_emul, s0_lmul, s0_eew, s0_sew) 106 val flowsPrevThisUop = (uopIdxInField << flowsLog2).asUInt // # of flows before this uop in a field 107 val flowsPrevThisVd = (vdIdxInField << numFlowsSameVdLog2).asUInt // # of flows before this vd in a field 108 val flowsIncludeThisUop = ((uopIdxInField +& 1.U) << flowsLog2).asUInt // # of flows before this uop besides this uop 109 val flowNum = io.in.bits.flowNum.get 110 // max index in vd, only use in index instructions for calculate index 111 val maxIdxInVdIndex = GenVLMAX(Mux(s0_emul.asSInt > 0.S, 0.U, s0_emul), s0_eew) 112 val indexVlMaxInVd = GenVlMaxMask(maxIdxInVdIndex, elemIdxBits) 113 114 // For vectore indexed instructions: 115 // When emul is greater than lmul, multiple uop correspond to a Vd, e.g: 116 // vsetvli t1,t0,e8,m1,ta,ma lmul = 1 117 // vluxei16.v v2,(a0),v8 emul = 2 118 // In this case, we need to ensure the flownumis right shift by flowsPrevThisUop, However, the mask passed to mergebuff is right shift by flowsPrevThisVd e.g: 119 // vl = 9 120 // srcMask = 0x1FF 121 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x00FF, toMergeBuffMask = 0x01FF 122 // uopIdxInField = 1 and vdIdxInField = 0, flowMask = 0x0001, toMergeBuffMask = 0x01FF 123 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x0000, toMergeBuffMask = 0x0000 124 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x0000, toMergeBuffMask = 0x0000 125 val isSpecialIndexed = isIndexed(instType) && s0_emul.asSInt > s0_lmul.asSInt 126 127 val srcMask = GenFlowMask(Mux(s0_vm, Fill(VLEN, 1.U(1.W)), io.in.bits.src_mask), vvstart, evl, true) 128 val srcMaskShiftBits = Mux(isSpecialIndexed, flowsPrevThisUop, flowsPrevThisVd) 129 130 val flowMask = ((srcMask & 131 UIntToMask(flowsIncludeThisUop.asUInt, VLEN + 1) & 132 (~UIntToMask(flowsPrevThisUop.asUInt, VLEN)).asUInt 133 ) >> srcMaskShiftBits)(VLENB - 1, 0) 134 val indexedSrcMask = (srcMask >> flowsPrevThisVd).asUInt //only for index instructions 135 136 // Used to calculate the element index. 137 // See 'splitbuffer' for 'io.out.splitIdxOffset' and 'mergebuffer' for 'merge data' 138 val indexedSplitOffset = Mux(isSpecialIndexed, flowsPrevThisUop - flowsPrevThisVd, 0.U) // only for index instructions of emul > lmul 139 val vlmax = GenVLMAX(s0_lmul, s0_sew) 140 141 // connect 142 s0_out := DontCare 143 s0_out match {case x => 144 x.uop := io.in.bits.uop 145 x.uop.imm := 0.U 146 x.uop.vpu.vl := evl 147 x.uop.uopIdx := uopIdx 148 x.uop.numUops := numUops 149 x.uop.lastUop := (uopIdx +& 1.U) === numUops 150 x.uop.vpu.nf := s0_nf 151 x.rawNf := io.in.bits.uop.vpu.nf 152 x.flowMask := flowMask 153 x.indexedSrcMask := indexedSrcMask // Only vector indexed instructions uses it 154 x.indexedSplitOffset := indexedSplitOffset 155 x.byteMask := GenUopByteMask(flowMask, Cat("b0".U, alignedType))(VLENB - 1, 0) 156 x.fof := isUnitStride(s0_mop) && us_fof(s0_fuOpType) 157 x.baseAddr := io.in.bits.src_rs1 158 x.stride := io.in.bits.src_stride 159 x.flowNum := flowNum 160 x.nfields := s0_nfield 161 x.vm := s0_vm 162 x.usWholeReg := isUsWholeReg 163 x.usMaskReg := isMaskReg 164 x.eew := s0_eew 165 x.sew := s0_sew 166 x.emul := s0_emul 167 x.lmul := s0_lmul 168 x.vlmax := Mux(isUsWholeReg, evl, vlmax) 169 x.instType := instType 170 x.data := io.in.bits.src_vs3 171 x.vdIdxInField := vdIdxInField 172 x.preIsSplit := s0_preIsSplit 173 x.alignedType := broadenAligendType 174 x.indexVlMaxInVd := indexVlMaxInVd 175 } 176 s0_valid := io.in.valid && !s0_kill 177 /**------------------------------------- 178 * s1 stage 179 * ------------------------------------ 180 * generate UopOffset 181 */ 182 val s1_valid = RegInit(false.B) 183 val s1_kill = Wire(Bool()) 184 val s1_in = Wire(new VLSBundle(isVStore)) 185 val s1_can_go = io.out.ready && io.toMergeBuffer.req.ready 186 val s1_fire = s1_valid && !s1_kill && s1_can_go 187 188 s1_ready := s1_kill || !s1_valid || s1_can_go 189 190 when(s0_fire){ 191 s1_valid := true.B 192 }.elsewhen(s1_fire){ 193 s1_valid := false.B 194 }.elsewhen(s1_kill){ 195 s1_valid := false.B 196 } 197 s1_in := RegEnable(s0_out, s0_fire) 198 199 val s1_flowNum = s1_in.flowNum 200 val s1_uop = s1_in.uop 201 val s1_uopidx = s1_uop.vpu.vuopIdx 202 val s1_nf = s1_uop.vpu.nf 203 val s1_nfields = s1_in.nfields 204 val s1_eew = s1_in.eew 205 val s1_emul = s1_in.emul 206 val s1_lmul = s1_in.lmul 207 val s1_instType = s1_in.instType 208 val s1_stride = s1_in.stride 209 val s1_vmask = FillInterleaved(8, s1_in.byteMask)(VLEN-1, 0) 210 val s1_alignedType = s1_in.alignedType 211 val s1_isSpecialIndexed = isIndexed(s1_instType) && s1_emul.asSInt > s1_lmul.asSInt 212 val s1_mask = Mux(s1_isSpecialIndexed, s1_in.indexedSrcMask, s1_in.flowMask) 213 val s1_vdIdx = s1_in.vdIdxInField 214 val s1_fof = s1_in.fof 215 val s1_notIndexedStride = Mux( // stride for strided/unit-stride instruction 216 isStrided(s1_instType), 217 s1_stride(XLEN - 1, 0), // for strided load, stride = x[rs2] 218 s1_nfields << s1_eew // for unit-stride load, stride = eew * NFIELDS 219 ) 220 221 val stride = Mux(isIndexed(s1_instType), s1_stride, s1_notIndexedStride).asUInt // if is index instructions, get index when split 222 val uopOffset = genVUopOffset(s1_instType, s1_fof, s1_uopidx, s1_nf, s1_eew, stride, s1_alignedType) 223 val activeNum = Mux(s1_in.preIsSplit, PopCount(s1_in.flowMask), s1_flowNum) 224 // for Unit-Stride, if uop's addr is aligned with 128-bits, split it to one flow, otherwise split two 225 val usLowBitsAddr = getCheckAddrLowBits(s1_in.baseAddr, maxMemByteNum) + getCheckAddrLowBits(uopOffset, maxMemByteNum) 226 val usAligned128 = (getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) === 0.U)// addr 128-bit aligned 227 val usMask = Cat(0.U(VLENB.W), s1_in.byteMask) << getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) 228 229 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) 230 231 // query mergeBuffer 232 io.toMergeBuffer.req.valid := io.out.ready && s1_valid// only can_go will get MergeBuffer entry 233 io.toMergeBuffer.req.bits.flowNum := activeNum 234 io.toMergeBuffer.req.bits.data := s1_in.data 235 io.toMergeBuffer.req.bits.uop := s1_in.uop 236 io.toMergeBuffer.req.bits.uop.vpu.nf := s1_in.rawNf 237 io.toMergeBuffer.req.bits.mask := s1_mask 238 io.toMergeBuffer.req.bits.vaddr := s1_in.baseAddr 239 io.toMergeBuffer.req.bits.vdIdx := s1_vdIdx //TODO vdIdxReg should no longer be useful, don't delete it for now 240 io.toMergeBuffer.req.bits.fof := s1_in.fof 241 io.toMergeBuffer.req.bits.vlmax := s1_in.vlmax 242// io.toMergeBuffer.req.bits.vdOffset := 243 244 //TODO vdIdxReg should no longer be useful, don't delete it for now 245// when (s1_in.uop.lastUop && s1_fire || s1_kill) { 246// vdIdxReg := 0.U 247// }.elsewhen(s1_fire) { 248// vdIdxReg := vdIdxReg + 1.U 249// XSError(vdIdxReg + 1.U === 0.U, s"Overflow! The number of vd should be less than 8\n") 250// } 251 // out connect 252 io.out.valid := s1_valid && io.toMergeBuffer.resp.valid && (activeNum =/= 0.U) // if activeNum == 0, this uop do nothing, can be killed. 253 io.out.bits := s1_in 254 io.out.bits.uopOffset := uopOffset 255 io.out.bits.stride := stride 256 io.out.bits.mBIndex := io.toMergeBuffer.resp.bits.mBIndex 257 io.out.bits.usLowBitsAddr := usLowBitsAddr 258 io.out.bits.usAligned128 := usAligned128 259 io.out.bits.usMask := usMask 260 io.out.bits.uop.vpu.nf := s1_in.rawNf 261 262 XSPerfAccumulate("split_out", io.out.fire) 263 XSPerfAccumulate("pipe_block", io.out.valid && !io.out.ready) 264 XSPerfAccumulate("mbuffer_block", s1_valid && io.out.ready && !io.toMergeBuffer.resp.valid) 265} 266 267abstract class VSplitBuffer(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 268 val io = IO(new VSplitBufferIO(isVStore)) 269 lazy val fuCfg = if(isVStore) VstuCfg else VlduCfg 270 271 val uopq = Reg(new VLSBundle(isVStore)) 272 val allocated = RegInit(false.B) 273 val needCancel = WireInit(false.B) 274 val activeIssue = Wire(Bool()) 275 val inActiveIssue = Wire(Bool()) 276 val splitFinish = WireInit(false.B) 277 278 // for split 279 val splitIdx = RegInit(0.U(flowIdxBits.W)) 280 val strideOffsetReg = RegInit(0.U(VLEN.W)) 281 282 /** 283 * Redirect 284 */ 285 val cancelEnq = io.in.bits.uop.robIdx.needFlush(io.redirect) 286 val canEnqueue = io.in.valid 287 val needEnqueue = canEnqueue && !cancelEnq 288 289 // enqueue 290 val offset = PopCount(needEnqueue) 291 val canAccept = !allocated || allocated && splitFinish && (activeIssue || inActiveIssue) // if is valid entry, need split finish and send last uop 292 io.in.ready := canAccept 293 val doEnqueue = canAccept && needEnqueue 294 295 when(doEnqueue){ 296 uopq := io.in.bits 297 } 298 299 //split uops 300 val issueValid = allocated && !needCancel 301 val issueEntry = uopq 302 val issueMbIndex = issueEntry.mBIndex 303 val issueFlowNum = issueEntry.flowNum 304 val issueBaseAddr = issueEntry.baseAddr 305 val issueUop = issueEntry.uop 306 val issueUopIdx = issueUop.vpu.vuopIdx 307 val issueInstType = issueEntry.instType 308 val issueUopOffset = issueEntry.uopOffset 309 val issueEew = issueEntry.eew 310 val issueSew = issueEntry.sew 311 val issueLmul = issueEntry.lmul 312 val issueEmul = issueEntry.emul 313 val issueAlignedType = issueEntry.alignedType 314 val issuePreIsSplit = issueEntry.preIsSplit 315 val issueByteMask = issueEntry.byteMask 316 val issueUsMask = issueEntry.usMask 317 val issueVLMAXMask = issueEntry.vlmax - 1.U 318 val issueIsWholeReg = issueEntry.usWholeReg 319 val issueVLMAXLog2 = GenVLMAXLog2(issueEntry.lmul, issueSew) 320 val issueVlMaxInVd = issueEntry.indexVlMaxInVd 321 val issueUsLowBitsAddr = issueEntry.usLowBitsAddr 322 val issueUsAligned128 = issueEntry.usAligned128 323 val elemIdx = GenElemIdx( 324 instType = issueInstType, 325 emul = issueEmul, 326 lmul = issueLmul, 327 eew = issueEew, 328 sew = issueSew, 329 uopIdx = issueUopIdx, 330 flowIdx = splitIdx 331 ) // elemIdx inside an inst, for exception 332 333 val splitIdxOffset = issueEntry.indexedSplitOffset + splitIdx 334 335 val indexFlowInnerIdx = elemIdx & issueVlMaxInVd 336 val nfIdx = Mux(issueIsWholeReg, 0.U, elemIdx >> issueVLMAXLog2) 337 val fieldOffset = nfIdx << issueAlignedType // field offset inside a segment 338 339 val indexedStride = IndexAddr( // index for indexed instruction 340 index = issueEntry.stride, 341 flow_inner_idx = indexFlowInnerIdx, 342 eew = issueEew 343 ) 344 val issueStride = Mux(isIndexed(issueInstType), indexedStride, strideOffsetReg) 345 val vaddr = issueBaseAddr + issueUopOffset + issueStride 346 val mask = genVWmask128(vaddr ,issueAlignedType) // scala maske for flow 347 val flowMask = issueEntry.flowMask 348 val vecActive = (flowMask & UIntToOH(splitIdx)).orR 349 /* 350 * Unit-Stride split to one flow or two flow. 351 * for Unit-Stride, if uop's addr is aligned with 128-bits, split it to one flow, otherwise split two 352 */ 353 val usSplitMask = genUSSplitMask(issueUsMask, splitIdx) 354 val usMaskInSingleUop = (genUSSplitMask(issueUsMask, 1.U) === 0.U) // if second splited Mask is zero, means this uop is unnecessary to split 355 val usNoSplit = (issueUsAligned128 || usMaskInSingleUop) && 356 !issuePreIsSplit && 357 (splitIdx === 0.U)// unit-stride uop don't need to split into two flow 358 val usSplitVaddr = genUSSplitAddr(vaddr, splitIdx, XLEN) 359 val regOffset = getCheckAddrLowBits(issueUsLowBitsAddr, maxMemByteNum) // offset in 256-bits vd 360 XSError((splitIdx > 1.U && usNoSplit) || (splitIdx > 1.U && !issuePreIsSplit) , "Unit-Stride addr split error!\n") 361 362 // no-unit-stride can trigger misalign 363 val addrAligned = LookupTree(issueEew, List( 364 "b00".U -> true.B, //b 365 "b01".U -> (vaddr(0) === 0.U), //h 366 "b10".U -> (vaddr(1, 0) === 0.U), //w 367 "b11".U -> (vaddr(2, 0) === 0.U) //d 368 )) || !issuePreIsSplit 369 370 // data 371 io.out.bits match { case x => 372 x.uop := issueUop 373 x.uop.imm := 0.U 374 x.uop.exceptionVec := ExceptionNO.selectByFu(issueUop.exceptionVec, fuCfg) 375 x.vaddr := Mux(!issuePreIsSplit, usSplitVaddr, vaddr) 376 x.basevaddr := issueBaseAddr 377 x.alignedType := issueAlignedType 378 x.isvec := true.B 379 x.mask := Mux(!issuePreIsSplit, usSplitMask, mask) 380 x.reg_offset := regOffset //for merge unit-stride data 381 x.vecActive := Mux(!issuePreIsSplit, true.B, vecActive) // currently, unit-stride's flow always send to pipeline 382 x.is_first_ele := DontCare 383 x.usSecondInv := usNoSplit 384 x.elemIdx := elemIdx 385 x.elemIdxInsideVd := splitIdxOffset // if is Unit-Stride, elemIdx is the index of 2 splited mem request (for merge data) 386 x.uop_unit_stride_fof := DontCare 387 x.isFirstIssue := DontCare 388 x.mBIndex := issueMbIndex 389 } 390 391 // redirect 392 needCancel := uopq.uop.robIdx.needFlush(io.redirect) && allocated 393 394 /* Execute logic */ 395 /** Issue to scala pipeline**/ 396 397 lazy val misalignedCanGo = true.B 398 val allowIssue = (addrAligned || misalignedCanGo) && io.out.ready 399 val issueCount = Mux(usNoSplit, 2.U, (PopCount(inActiveIssue) + PopCount(activeIssue))) // for dont need split unit-stride, issue two flow 400 splitFinish := splitIdx >= (issueFlowNum - issueCount) 401 402 // handshake 403 activeIssue := issueValid && allowIssue && (vecActive || !issuePreIsSplit) // active issue, current use in no unit-stride 404 inActiveIssue := issueValid && !vecActive && issuePreIsSplit 405 when (!issueEntry.uop.robIdx.needFlush(io.redirect)) { 406 when (!splitFinish) { 407 when (activeIssue || inActiveIssue) { 408 // The uop has not been entirly splited yet 409 splitIdx := splitIdx + issueCount 410 strideOffsetReg := Mux(!issuePreIsSplit, strideOffsetReg, strideOffsetReg + issueEntry.stride) // when normal unit-stride, don't use strideOffsetReg 411 } 412 }.otherwise { 413 when (activeIssue || inActiveIssue) { 414 // The uop is done spliting 415 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 416 strideOffsetReg := 0.U 417 } 418 } 419 }.otherwise { 420 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 421 strideOffsetReg := 0.U 422 } 423 // allocated 424 when(doEnqueue){ // if enqueue need to been cancelled, it will be false, so this have high priority 425 allocated := true.B 426 }.elsewhen(needCancel) { // redirect 427 allocated := false.B 428 }.elsewhen(splitFinish && (activeIssue || inActiveIssue)){ //dequeue 429 allocated := false.B 430 } 431 432 // out connect 433 io.out.valid := issueValid && (vecActive || !issuePreIsSplit) && (addrAligned || misalignedCanGo) // TODO: inactive unit-stride uop do not send to pipeline 434 435 XSPerfAccumulate("out_valid", io.out.valid) 436 XSPerfAccumulate("out_fire", io.out.fire) 437 XSPerfAccumulate("out_fire_unitstride", io.out.fire && !issuePreIsSplit) 438 XSPerfAccumulate("unitstride_vlenAlign", io.out.fire && !issuePreIsSplit && getCheckAddrLowBits(io.out.bits.vaddr, maxMemByteNum) === 0.U) 439 XSPerfAccumulate("unitstride_invalid", io.out.ready && issueValid && !issuePreIsSplit && PopCount(io.out.bits.mask).orR) 440} 441 442class VSSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = true){ 443 override lazy val misalignedCanGo = io.vstdMisalign.get.storePipeEmpty && io.vstdMisalign.get.storeMisalignBufferEmpty 444 445 // split data 446 val splitData = genVSData( 447 data = issueEntry.data.asUInt, 448 elemIdx = splitIdxOffset, 449 alignedType = issueAlignedType 450 ) 451 val flowData = genVWdata(splitData, issueAlignedType) 452 val usSplitData = genUSSplitData(issueEntry.data.asUInt, splitIdx, vaddr(3,0)) 453 454 val sqIdx = issueUop.sqIdx + splitIdx 455 io.out.bits.uop.sqIdx := sqIdx 456 io.out.bits.uop.exceptionVec(storeAddrMisaligned) := !addrAligned && !issuePreIsSplit && io.out.bits.mask.orR 457 458 // send data to sq 459 val vstd = io.vstd.get 460 vstd.valid := issueValid && (vecActive || !issuePreIsSplit) 461 vstd.bits.uop := issueUop 462 vstd.bits.uop.sqIdx := sqIdx 463 vstd.bits.uop.fuType := FuType.vstu.U 464 vstd.bits.data := Mux(!issuePreIsSplit, usSplitData, flowData) 465 vstd.bits.debug := DontCare 466 vstd.bits.vdIdx.get := DontCare 467 vstd.bits.vdIdxInField.get := DontCare 468 vstd.bits.isFromLoadUnit := DontCare 469 vstd.bits.mask.get := Mux(!issuePreIsSplit, usSplitMask, mask) 470 471} 472 473class VLSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = false){ 474 io.out.bits.uop.lqIdx := issueUop.lqIdx + splitIdx 475 io.out.bits.uop.exceptionVec(loadAddrMisaligned) := !addrAligned && !issuePreIsSplit && io.out.bits.mask.orR 476 io.out.bits.uop.fuType := FuType.vldu.U 477} 478 479class VSSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = true){ 480 override def us_whole_reg(fuOpType: UInt): Bool = fuOpType === VstuType.vsr 481 override def us_mask(fuOpType: UInt): Bool = fuOpType === VstuType.vsm 482 override def us_fof(fuOpType: UInt): Bool = false.B // dont have vector fof store 483} 484 485class VLSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = false){ 486 487 override def us_whole_reg(fuOpType: UInt): Bool = fuOpType === VlduType.vlr 488 override def us_mask(fuOpType: UInt): Bool = fuOpType === VlduType.vlm 489 override def us_fof(fuOpType: UInt): Bool = fuOpType === VlduType.vleff 490} 491 492class VLSplitImp(implicit p: Parameters) extends VLSUModule{ 493 val io = IO(new VSplitIO(isVStore=false)) 494 val splitPipeline = Module(new VLSplitPipelineImp()) 495 val splitBuffer = Module(new VLSplitBufferImp()) 496 // Split Pipeline 497 splitPipeline.io.in <> io.in 498 splitPipeline.io.redirect <> io.redirect 499 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 500 501 // skid buffer 502 skidBuffer(splitPipeline.io.out, splitBuffer.io.in, 503 Mux(splitPipeline.io.out.fire, 504 splitPipeline.io.out.bits.uop.robIdx.needFlush(io.redirect), 505 splitBuffer.io.in.bits.uop.robIdx.needFlush(io.redirect)), 506 "VSSplitSkidBuffer") 507 508 // Split Buffer 509 splitBuffer.io.redirect <> io.redirect 510 io.out <> splitBuffer.io.out 511} 512 513class VSSplitImp(implicit p: Parameters) extends VLSUModule{ 514 val io = IO(new VSplitIO(isVStore=true)) 515 val splitPipeline = Module(new VSSplitPipelineImp()) 516 val splitBuffer = Module(new VSSplitBufferImp()) 517 // Split Pipeline 518 splitPipeline.io.in <> io.in 519 splitPipeline.io.redirect <> io.redirect 520 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 521 522 // skid buffer 523 skidBuffer(splitPipeline.io.out, splitBuffer.io.in, 524 Mux(splitPipeline.io.out.fire, 525 splitPipeline.io.out.bits.uop.robIdx.needFlush(io.redirect), 526 splitBuffer.io.in.bits.uop.robIdx.needFlush(io.redirect)), 527 "VSSplitSkidBuffer") 528 529 // Split Buffer 530 splitBuffer.io.redirect <> io.redirect 531 io.out <> splitBuffer.io.out 532 io.vstd.get <> splitBuffer.io.vstd.get 533 534 io.vstdMisalign.get <> splitBuffer.io.vstdMisalign.get 535} 536 537