1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.rob.RobPtr 26import xiangshan.backend.Bundles._ 27import xiangshan.mem._ 28import xiangshan.backend.fu.vector.Bundles._ 29 30 31class VSplitPipeline(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 32 val io = IO(new VSplitPipelineIO(isVStore)) 33 // will be override later 34 def us_whole_reg(fuOpType: UInt): Bool = false.B 35 def us_mask(fuOpType: UInt): Bool = false.B 36 def us_fof(fuOpType: UInt): Bool = false.B 37 //TODO vdIdxReg should no longer be useful, don't delete it for now 38 val vdIdxReg = RegInit(0.U(3.W)) 39 40 val s1_ready = WireInit(false.B) 41 io.in.ready := s1_ready 42 43 /**----------------------------------------------------------- 44 * s0 stage 45 * decode and generate AlignedType, uop mask, preIsSplit 46 * ---------------------------------------------------------- 47 */ 48 val s0_uop = io.in.bits.uop 49 val s0_vtype = s0_uop.vpu.vtype 50 val s0_sew = s0_vtype.vsew 51 val s0_eew = s0_uop.vpu.veew 52 val s0_lmul = s0_vtype.vlmul 53 // when load whole register or unit-stride masked , emul should be 1 54 val s0_fuOpType = s0_uop.fuOpType 55 val s0_mop = s0_fuOpType(6, 5) 56 val s0_nf = Mux(us_whole_reg(s0_fuOpType), 0.U, s0_uop.vpu.nf) 57 val s0_vm = s0_uop.vpu.vm 58 val s0_emul = Mux(us_whole_reg(s0_fuOpType) ,GenUSWholeEmul(s0_uop.vpu.nf), Mux(us_mask(s0_fuOpType), 0.U(mulBits.W), EewLog2(s0_eew) - s0_sew + s0_lmul)) 59 val s0_preIsSplit = !(isUnitStride(s0_mop) && !us_fof(s0_fuOpType)) 60 val s0_nfield = s0_nf +& 1.U 61 62 val s0_valid = Wire(Bool()) 63 val s0_kill = io.in.bits.uop.robIdx.needFlush(io.redirect) 64 val s0_can_go = s1_ready 65 val s0_fire = s0_valid && s0_can_go 66 val s0_out = Wire(new VLSBundle(isVStore)) 67 68 val isUsWholeReg = isUnitStride(s0_mop) && us_whole_reg(s0_fuOpType) 69 val isMaskReg = isUnitStride(s0_mop) && us_mask(s0_fuOpType) 70 val isSegment = s0_nf =/= 0.U && !us_whole_reg(s0_fuOpType) 71 val instType = Cat(isSegment, s0_mop) 72 val uopIdx = io.in.bits.uop.vpu.vuopIdx 73 val uopIdxInField = GenUopIdxInField(instType, s0_emul, s0_lmul, uopIdx) 74 val vdIdxInField = GenVdIdxInField(instType, s0_emul, s0_lmul, uopIdxInField) 75 val lmulLog2 = Mux(s0_lmul.asSInt >= 0.S, 0.U, s0_lmul) 76 val emulLog2 = Mux(s0_emul.asSInt >= 0.S, 0.U, s0_emul) 77 val numEewLog2 = emulLog2 - EewLog2(s0_eew) 78 val numSewLog2 = lmulLog2 - s0_sew 79 val numFlowsSameVdLog2 = Mux( 80 isIndexed(instType), 81 log2Up(VLENB).U - s0_sew(1,0), 82 log2Up(VLENB).U - s0_eew(1,0) 83 ) 84 // numUops = nf * max(lmul, emul) 85 val lmulLog2Pos = Mux(s0_lmul.asSInt < 0.S, 0.U, s0_lmul) 86 val emulLog2Pos = Mux(s0_emul.asSInt < 0.S, 0.U, s0_emul) 87 val numUops = Mux( 88 isIndexed(s0_mop) && s0_lmul.asSInt > s0_emul.asSInt, 89 (s0_nf +& 1.U) << lmulLog2Pos, 90 (s0_nf +& 1.U) << emulLog2Pos 91 ) 92 93 val vvl = io.in.bits.src_vl.asTypeOf(VConfig()).vl 94 val evl = Mux(isUsWholeReg, 95 GenUSWholeRegVL(io.in.bits.uop.vpu.nf +& 1.U, s0_eew), 96 Mux(isMaskReg, 97 GenUSMaskRegVL(vvl), 98 vvl)) 99 val vvstart = io.in.bits.uop.vpu.vstart 100 val alignedType = Mux(isIndexed(instType), s0_sew(1, 0), s0_eew(1, 0)) 101 val broadenAligendType = Mux(s0_preIsSplit, Cat("b0".U, alignedType), "b100".U) // if is unit-stride, use 128-bits memory access 102 val flowsLog2 = GenRealFlowLog2(instType, s0_emul, s0_lmul, s0_eew, s0_sew) 103 val flowsPrevThisUop = (uopIdxInField << flowsLog2).asUInt // # of flows before this uop in a field 104 val flowsPrevThisVd = (vdIdxInField << numFlowsSameVdLog2).asUInt // # of flows before this vd in a field 105 val flowsIncludeThisUop = ((uopIdxInField +& 1.U) << flowsLog2).asUInt // # of flows before this uop besides this uop 106 val flowNum = io.in.bits.flowNum.get 107 108 // For vectore indexed instructions: 109 // When emul is greater than lmul, multiple uop correspond to a Vd, e.g: 110 // vsetvli t1,t0,e8,m1,ta,ma lmul = 1 111 // vluxei16.v v2,(a0),v8 emul = 2 112 // In this case, we need to ensure the flownumis right shift by flowsPrevThisUop, However, the mask passed to mergebuff is right shift by flowsPrevThisVd e.g: 113 // vl = 9 114 // srcMask = 0x1FF 115 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x00FF, toMergeBuffMask = 0x01FF 116 // uopIdxInField = 1 and vdIdxInField = 0, flowMask = 0x0001, toMergeBuffMask = 0x01FF 117 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x0000, toMergeBuffMask = 0x0000 118 // uopIdxInField = 0 and vdIdxInField = 0, flowMask = 0x0000, toMergeBuffMask = 0x0000 119 val isSpecialIndexed = isIndexed(instType) && s0_emul.asSInt > s0_lmul.asSInt 120 121 val srcMask = GenFlowMask(Mux(s0_vm, Fill(VLEN, 1.U(1.W)), io.in.bits.src_mask), vvstart, evl, true) 122 val srcMaskShiftBits = Mux(isSpecialIndexed, flowsPrevThisUop, flowsPrevThisVd) 123 124 val flowMask = ((srcMask & 125 UIntToMask(flowsIncludeThisUop.asUInt, VLEN + 1) & 126 (~UIntToMask(flowsPrevThisUop.asUInt, VLEN)).asUInt 127 ) >> srcMaskShiftBits)(VLENB - 1, 0) 128 val indexedSrcMask = (srcMask >> flowsPrevThisVd).asUInt //only for index instructions 129 130 // Used to calculate the element index. 131 // See 'splitbuffer' for 'io.out.splitIdxOffset' and 'mergebuffer' for 'merge data' 132 val indexedSplitOffset = Mux(isSpecialIndexed, flowsPrevThisUop - flowsPrevThisVd, 0.U) // only for index instructions of emul > lmul 133 val vlmax = GenVLMAX(s0_lmul, s0_sew) 134 135 // connect 136 s0_out := DontCare 137 s0_out match {case x => 138 x.uop := io.in.bits.uop 139 x.uop.vpu.vl := evl 140 x.uop.uopIdx := uopIdx 141 x.uop.numUops := numUops 142 x.uop.lastUop := (uopIdx +& 1.U) === numUops 143 x.uop.vpu.nf := s0_nf 144 x.flowMask := flowMask 145 x.indexedSrcMask := indexedSrcMask // Only vector indexed instructions uses it 146 x.indexedSplitOffset := indexedSplitOffset 147 x.byteMask := GenUopByteMask(flowMask, Cat("b0".U, alignedType))(VLENB - 1, 0) 148 x.fof := isUnitStride(s0_mop) && us_fof(s0_fuOpType) 149 x.baseAddr := io.in.bits.src_rs1 150 x.stride := io.in.bits.src_stride 151 x.flowNum := flowNum 152 x.nfields := s0_nfield 153 x.vm := s0_vm 154 x.usWholeReg := isUsWholeReg 155 x.usMaskReg := isMaskReg 156 x.eew := s0_eew 157 x.sew := s0_sew 158 x.emul := s0_emul 159 x.lmul := s0_lmul 160 x.vlmax := Mux(isUsWholeReg, evl, vlmax) 161 x.instType := instType 162 x.data := io.in.bits.src_vs3 163 x.vdIdxInField := vdIdxInField 164 x.preIsSplit := s0_preIsSplit 165 x.alignedType := broadenAligendType 166 } 167 s0_valid := io.in.valid && !s0_kill 168 /**------------------------------------- 169 * s1 stage 170 * ------------------------------------ 171 * generate UopOffset 172 */ 173 val s1_valid = RegInit(false.B) 174 val s1_kill = Wire(Bool()) 175 val s1_in = Wire(new VLSBundle(isVStore)) 176 val s1_can_go = io.out.ready && io.toMergeBuffer.resp.valid 177 val s1_fire = s1_valid && !s1_kill && s1_can_go 178 179 s1_ready := s1_kill || !s1_valid || io.out.ready && io.toMergeBuffer.resp.valid 180 181 when(s0_fire){ 182 s1_valid := true.B 183 }.elsewhen(s1_fire){ 184 s1_valid := false.B 185 }.elsewhen(s1_kill){ 186 s1_valid := false.B 187 } 188 s1_in := RegEnable(s0_out, s0_fire) 189 190 val s1_flowNum = s1_in.flowNum 191 val s1_uop = s1_in.uop 192 val s1_uopidx = s1_uop.vpu.vuopIdx 193 val s1_nf = s1_uop.vpu.nf 194 val s1_nfields = s1_in.nfields 195 val s1_eew = s1_in.eew 196 val s1_emul = s1_in.emul 197 val s1_lmul = s1_in.lmul 198 val s1_instType = s1_in.instType 199 val s1_stride = s1_in.stride 200 val s1_vmask = FillInterleaved(8, s1_in.byteMask)(VLEN-1, 0) 201 val s1_alignedType = s1_in.alignedType 202 val s1_isSpecialIndexed = isIndexed(s1_instType) && s1_emul.asSInt > s1_lmul.asSInt 203 val s1_mask = Mux(s1_isSpecialIndexed, s1_in.indexedSrcMask, s1_in.flowMask) 204 val s1_vdIdx = s1_in.vdIdxInField 205 val s1_fof = s1_in.fof 206 val s1_notIndexedStride = Mux( // stride for strided/unit-stride instruction 207 isStrided(s1_instType), 208 s1_stride(XLEN - 1, 0), // for strided load, stride = x[rs2] 209 s1_nfields << s1_eew(1, 0) // for unit-stride load, stride = eew * NFIELDS 210 ) 211 212 val stride = Mux(isIndexed(s1_instType), s1_stride, s1_notIndexedStride).asUInt // if is index instructions, get index when split 213 val uopOffset = genVUopOffset(s1_instType, s1_fof, s1_uopidx, s1_nf, s1_eew(1, 0), stride, s1_alignedType) 214 val activeNum = Mux(s1_in.preIsSplit, PopCount(s1_in.flowMask), s1_flowNum) 215 216 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) 217 218 // query mergeBuffer 219 io.toMergeBuffer.req.valid := s1_fire // only can_go will get MergeBuffer entry 220 io.toMergeBuffer.req.bits.flowNum := activeNum 221 io.toMergeBuffer.req.bits.data := s1_in.data 222 io.toMergeBuffer.req.bits.uop := s1_in.uop 223 io.toMergeBuffer.req.bits.mask := s1_mask 224 io.toMergeBuffer.req.bits.vaddr := DontCare 225 io.toMergeBuffer.req.bits.vdIdx := s1_vdIdx //TODO vdIdxReg should no longer be useful, don't delete it for now 226 io.toMergeBuffer.req.bits.fof := s1_in.fof 227 io.toMergeBuffer.req.bits.vlmax := s1_in.vlmax 228// io.toMergeBuffer.req.bits.vdOffset := 229 230 //TODO vdIdxReg should no longer be useful, don't delete it for now 231// when (s1_in.uop.lastUop && s1_fire || s1_kill) { 232// vdIdxReg := 0.U 233// }.elsewhen(s1_fire) { 234// vdIdxReg := vdIdxReg + 1.U 235// XSError(vdIdxReg + 1.U === 0.U, s"Overflow! The number of vd should be less than 8\n") 236// } 237 // out connect 238 io.out.valid := s1_valid && io.toMergeBuffer.resp.valid && (activeNum =/= 0.U) // if activeNum == 0, this uop do nothing, can be killed. 239 io.out.bits := s1_in 240 io.out.bits.uopOffset := uopOffset 241 io.out.bits.stride := stride 242 io.out.bits.mBIndex := io.toMergeBuffer.resp.bits.mBIndex 243 244 XSPerfAccumulate("split_out", io.out.fire) 245 XSPerfAccumulate("pipe_block", io.out.valid && !io.out.ready) 246 XSPerfAccumulate("mbuffer_block", s1_valid && io.out.ready && !io.toMergeBuffer.resp.valid) 247} 248 249abstract class VSplitBuffer(isVStore: Boolean = false)(implicit p: Parameters) extends VLSUModule{ 250 val io = IO(new VSplitBufferIO(isVStore)) 251 252 val uopq = Reg(new VLSBundle(isVStore)) 253 val allocated = RegInit(false.B) 254 val needCancel = WireInit(false.B) 255 val activeIssue = Wire(Bool()) 256 val inActiveIssue = Wire(Bool()) 257 val splitFinish = WireInit(false.B) 258 259 // for split 260 val splitIdx = RegInit(0.U(flowIdxBits.W)) 261 val strideOffsetReg = RegInit(0.U(VLEN.W)) 262 263 /** 264 * Redirect 265 */ 266 val cancelEnq = io.in.bits.uop.robIdx.needFlush(io.redirect) 267 val canEnqueue = io.in.valid 268 val needEnqueue = canEnqueue && !cancelEnq 269 270 // enqueue 271 val offset = PopCount(needEnqueue) 272 val canAccept = !allocated || allocated && splitFinish && (activeIssue || inActiveIssue) // if is valid entry, need split finish and send last uop 273 io.in.ready := canAccept 274 val doEnqueue = canAccept && needEnqueue 275 276 when(doEnqueue){ 277 uopq := io.in.bits 278 } 279 280 //split uops 281 val issueValid = allocated && !needCancel 282 val issueEntry = uopq 283 val issueMbIndex = issueEntry.mBIndex 284 val issueFlowNum = issueEntry.flowNum 285 val issueBaseAddr = issueEntry.baseAddr 286 val issueUop = issueEntry.uop 287 val issueUopIdx = issueUop.vpu.vuopIdx 288 val issueInstType = issueEntry.instType 289 val issueUopOffset = issueEntry.uopOffset 290 val issueEew = issueEntry.eew 291 val issueSew = issueEntry.sew 292 val issueLmul = issueEntry.lmul 293 val issueEmul = issueEntry.emul 294 val issueAlignedType = issueEntry.alignedType 295 val issuePreIsSplit = issueEntry.preIsSplit 296 val issueByteMask = issueEntry.byteMask 297 val issueVLMAXMask = issueEntry.vlmax - 1.U 298 val issueIsWholeReg = issueEntry.usWholeReg 299 val issueVLMAXLog2 = GenVLMAXLog2(issueEntry.lmul, issueSew) 300 val elemIdx = GenElemIdx( 301 instType = issueInstType, 302 emul = issueEmul, 303 lmul = issueLmul, 304 eew = issueEew, 305 sew = issueSew, 306 uopIdx = issueUopIdx, 307 flowIdx = splitIdx 308 ) // elemIdx inside an inst, for exception 309 310 val splitIdxOffset = issueEntry.indexedSplitOffset + splitIdx 311 312 val elemIdxInsideField = elemIdx & issueVLMAXMask 313 val indexFlowInnerIdx = ((elemIdxInsideField << issueEew(1, 0))(vOffsetBits - 1, 0) >> issueEew(1, 0)).asUInt 314 val nfIdx = Mux(issueIsWholeReg, 0.U, elemIdx >> issueVLMAXLog2) 315 val fieldOffset = nfIdx << issueAlignedType // field offset inside a segment 316 317 val indexedStride = IndexAddr( // index for indexed instruction 318 index = issueEntry.stride, 319 flow_inner_idx = indexFlowInnerIdx, 320 eew = issueEew 321 ) 322 val issueStride = Mux(isIndexed(issueInstType), indexedStride, strideOffsetReg) 323 val vaddr = issueBaseAddr + issueUopOffset + issueStride 324 val mask = genVWmask128(vaddr ,issueAlignedType) // scala maske for flow 325 val flowMask = issueEntry.flowMask 326 val vecActive = (flowMask & UIntToOH(splitIdx)).orR 327 /* 328 * Unit-Stride split to one flow or two flow. 329 * for Unit-Stride, if uop's addr is aligned with 128-bits, split it to one flow, otherwise split two 330 */ 331 val usLowBitsAddr = getCheckAddrLowBits(issueBaseAddr, maxMemByteNum) + getCheckAddrLowBits(issueUopOffset, maxMemByteNum) 332 val usAligned128 = (getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) === 0.U)// addr 128-bit aligned 333 val usSplitMask = genUSSplitMask(issueByteMask, splitIdx, getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum)) 334 val usNoSplit = (usAligned128 || !getOverflowBit(getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) +& PopCount(usSplitMask), maxMemByteNum)) && 335 !issuePreIsSplit && 336 (splitIdx === 0.U)// unit-stride uop don't need to split into two flow 337 val usSplitVaddr = genUSSplitAddr(vaddr, splitIdx) 338 val regOffset = getCheckAddrLowBits(usLowBitsAddr, maxMemByteNum) // offset in 256-bits vd 339 XSError((splitIdx > 1.U && usNoSplit) || (splitIdx > 1.U && !issuePreIsSplit) , "Unit-Stride addr split error!\n") 340 341 // data 342 io.out.bits match { case x => 343 x.uop := issueUop 344 x.vaddr := Mux(!issuePreIsSplit, usSplitVaddr, vaddr) 345 x.alignedType := issueAlignedType 346 x.isvec := true.B 347 x.mask := Mux(!issuePreIsSplit, usSplitMask, mask) 348 x.reg_offset := regOffset //for merge unit-stride data 349 x.vecActive := Mux(!issuePreIsSplit, true.B, vecActive) // currently, unit-stride's flow always send to pipeline 350 x.is_first_ele := DontCare 351 x.usSecondInv := usNoSplit 352 x.elemIdx := elemIdx 353 x.elemIdxInsideVd := splitIdxOffset // if is Unit-Stride, elemIdx is the index of 2 splited mem request (for merge data) 354 x.uop_unit_stride_fof := DontCare 355 x.isFirstIssue := DontCare 356 x.mBIndex := issueMbIndex 357 } 358 359 // redirect 360 needCancel := uopq.uop.robIdx.needFlush(io.redirect) && allocated 361 362 /* Execute logic */ 363 /** Issue to scala pipeline**/ 364 val allowIssue = io.out.ready 365 val issueCount = Mux(usNoSplit, 2.U, (PopCount(inActiveIssue) + PopCount(activeIssue))) // for dont need split unit-stride, issue two flow 366 splitFinish := splitIdx >= (issueFlowNum - issueCount) 367 368 // handshake 369 activeIssue := issueValid && allowIssue && (vecActive || !issuePreIsSplit) // active issue, current use in no unit-stride 370 inActiveIssue := issueValid && !vecActive && issuePreIsSplit 371 when (!issueEntry.uop.robIdx.needFlush(io.redirect)) { 372 when (!splitFinish) { 373 when (activeIssue || inActiveIssue) { 374 // The uop has not been entirly splited yet 375 splitIdx := splitIdx + issueCount 376 strideOffsetReg := Mux(!issuePreIsSplit, strideOffsetReg, strideOffsetReg + issueEntry.stride) // when normal unit-stride, don't use strideOffsetReg 377 } 378 }.otherwise { 379 when (activeIssue || inActiveIssue) { 380 // The uop is done spliting 381 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 382 strideOffsetReg := 0.U 383 } 384 } 385 }.otherwise { 386 splitIdx := 0.U(flowIdxBits.W) // initialize flowIdx 387 strideOffsetReg := 0.U 388 } 389 // allocated 390 when(doEnqueue){ // if enqueue need to been cancelled, it will be false, so this have high priority 391 allocated := true.B 392 }.elsewhen(needCancel) { // redirect 393 allocated := false.B 394 }.elsewhen(splitFinish && (activeIssue || inActiveIssue)){ //dequeue 395 allocated := false.B 396 } 397 398 // out connect 399 io.out.valid := issueValid && (vecActive || !issuePreIsSplit) // TODO: inactive unit-stride uop do not send to pipeline 400 401 XSPerfAccumulate("out_valid", io.out.valid) 402 XSPerfAccumulate("out_fire", io.out.fire) 403 XSPerfAccumulate("out_fire_unitstride", io.out.fire && !issuePreIsSplit) 404 XSPerfAccumulate("unitstride_vlenAlign", io.out.fire && !issuePreIsSplit && getCheckAddrLowBits(io.out.bits.vaddr, maxMemByteNum) === 0.U) 405 XSPerfAccumulate("unitstride_invalid", io.out.ready && issueValid && !issuePreIsSplit && PopCount(io.out.bits.mask).orR) 406} 407 408class VSSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = true){ 409 // split data 410 val splitData = genVSData( 411 data = issueEntry.data.asUInt, 412 elemIdx = splitIdxOffset, 413 alignedType = issueAlignedType 414 ) 415 val flowData = genVWdata(splitData, issueAlignedType) 416 val usSplitData = genUSSplitData(issueEntry.data.asUInt, splitIdx, vaddr(3,0)) 417 418 val sqIdx = issueUop.sqIdx + splitIdx 419 io.out.bits.uop.sqIdx := sqIdx 420 421 // send data to sq 422 val vstd = io.vstd.get 423 vstd.valid := issueValid && (vecActive || !issuePreIsSplit) 424 vstd.bits.uop := issueUop 425 vstd.bits.uop.sqIdx := sqIdx 426 vstd.bits.data := Mux(!issuePreIsSplit, usSplitData, flowData) 427 vstd.bits.debug := DontCare 428 vstd.bits.vdIdx.get := DontCare 429 vstd.bits.vdIdxInField.get := DontCare 430 vstd.bits.mask.get := Mux(!issuePreIsSplit, usSplitMask, mask) 431 432} 433 434class VLSplitBufferImp(implicit p: Parameters) extends VSplitBuffer(isVStore = false){ 435 io.out.bits.uop.lqIdx := issueUop.lqIdx + splitIdx 436} 437 438class VSSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = true){ 439 override def us_whole_reg(fuOpType: UInt): Bool = fuOpType === VstuType.vsr 440 override def us_mask(fuOpType: UInt): Bool = fuOpType === VstuType.vsm 441 override def us_fof(fuOpType: UInt): Bool = false.B // dont have vector fof store 442} 443 444class VLSplitPipelineImp(implicit p: Parameters) extends VSplitPipeline(isVStore = false){ 445 446 override def us_whole_reg(fuOpType: UInt): Bool = fuOpType === VlduType.vlr 447 override def us_mask(fuOpType: UInt): Bool = fuOpType === VlduType.vlm 448 override def us_fof(fuOpType: UInt): Bool = fuOpType === VlduType.vleff 449} 450 451class VLSplitImp(implicit p: Parameters) extends VLSUModule{ 452 val io = IO(new VSplitIO(isVStore=false)) 453 val splitPipeline = Module(new VLSplitPipelineImp()) 454 val splitBuffer = Module(new VLSplitBufferImp()) 455 // Split Pipeline 456 splitPipeline.io.in <> io.in 457 splitPipeline.io.redirect <> io.redirect 458 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 459 460 // Split Buffer 461 splitBuffer.io.in <> splitPipeline.io.out 462 splitBuffer.io.redirect <> io.redirect 463 io.out <> splitBuffer.io.out 464} 465 466class VSSplitImp(implicit p: Parameters) extends VLSUModule{ 467 val io = IO(new VSplitIO(isVStore=true)) 468 val splitPipeline = Module(new VSSplitPipelineImp()) 469 val splitBuffer = Module(new VSSplitBufferImp()) 470 // Split Pipeline 471 splitPipeline.io.in <> io.in 472 splitPipeline.io.redirect <> io.redirect 473 io.toMergeBuffer <> splitPipeline.io.toMergeBuffer 474 475 // Split Buffer 476 splitBuffer.io.in <> splitPipeline.io.out 477 splitBuffer.io.redirect <> io.redirect 478 io.out <> splitBuffer.io.out 479 io.vstd.get <> splitBuffer.io.vstd.get 480} 481 482