1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.rob.RobPtr 26import xiangshan.backend.Bundles._ 27import xiangshan.mem._ 28import xiangshan.backend.fu.FuType 29import freechips.rocketchip.diplomacy.BufferParams 30import xiangshan.cache.mmu._ 31import xiangshan.cache._ 32import xiangshan.cache.wpu.ReplayCarry 33import xiangshan.backend.fu.util.SdtrigExt 34import xiangshan.ExceptionNO._ 35import xiangshan.backend.fu.vector.Bundles.VConfig 36import xiangshan.backend.fu.vector.Utils.VecDataToMaskDataVec 37 38class VSegmentBundle(implicit p: Parameters) extends VLSUBundle 39{ 40 val baseVaddr = UInt(VAddrBits.W) 41 val uop = new DynInst 42 val paddr = UInt(PAddrBits.W) 43 val mask = UInt(VLEN.W) 44 val alignedType = UInt(alignTypeBits.W) 45 val vl = UInt(elemIdxBits.W) 46 val uopFlowNum = UInt(elemIdxBits.W) 47 val uopFlowNumMask = UInt(elemIdxBits.W) 48 // for exception 49 val vstart = UInt(elemIdxBits.W) 50 val exceptionVaddr = UInt(VAddrBits.W) 51 val exception_va = Bool() 52 val exception_pa = Bool() 53 val exceptionVstart = UInt(elemIdxBits.W) 54 val exceptionVl = UInt(elemIdxBits.W) 55 val isFof = Bool() 56} 57 58// latch each uop's VecWen, pdest, v0Wen, uopIdx 59class VSegmentUop(implicit p: Parameters) extends VLSUBundle{ 60 val uop = new DynInst 61} 62 63class VSegmentUnit (implicit p: Parameters) extends VLSUModule 64 with HasDCacheParameters 65 with MemoryOpConstants 66 with SdtrigExt 67 with HasLoadHelper 68{ 69 val io = IO(new VSegmentUnitIO) 70 71 val maxSize = VSegmentBufferSize 72 73 class VSegUPtr(implicit p: Parameters) extends CircularQueuePtr[VSegUPtr](maxSize){ 74 } 75 76 object VSegUPtr { 77 def apply(f: Bool, v: UInt)(implicit p: Parameters): VSegUPtr = { 78 val ptr = Wire(new VSegUPtr) 79 ptr.flag := f 80 ptr.value := v 81 ptr 82 } 83 } 84 85 86 /** 87 ******************************************************************************************************** 88 * Use an example to illustrate the working logic of a segmentunit: * 89 * For: * 90 * lmul=2 sew=32 emul=2 eew=32 vl=16 * 91 * Then: * 92 * Access memory in the order: * 93 * (V2,S0),(V4,S0),(V6,S0),(V8,S0), * 94 * (V2,S1),(V4,S1),(V6,S1),(V8,S1), * 95 * (V2,S2),(V4,S2),(V6,S2),(V8,S2), * 96 * (V2,S3),(V4,S3),(V6,S3),(V8,S3), * 97 * (V3,S4),(V5,S4),(V7,S4),(V9,S4), * 98 * (V3,S5),(V5,S5),(V7,S5),(V9,S5), * 99 * (V3,S6),(V5,S6),(V7,S6),(V9,S6), * 100 * (V3,S7),(V5,S7),(V7,S7),(V9,S7), * 101 * * 102 * * 103 * [[data]] saves the data generated by the access and corresponds to the register. * 104 * [[splitPtr]] controls the destination register written to. * 105 * * 106 * splitptr offset can be seen in [[splitPtrNext]] is assignment logic, * 107 * which is mainly calculated in terms of [[fieldIdx]] and [[segmentIdx]] * 108 * First access different fields of the same segment, and then visit different segments. * 109 * For the case of 'emul' greater than 1, such as the following example, * 110 * although 'v2' and 'v3' are different vd and the same field, they are still different segments, * 111 * so they should be accessed sequentially.Just like the 'Access memory in the order' above. * 112 * * 113 * [[segmentIdx]] * 114 * | * 115 * | * 116 * V * 117 * * 118 * S0 S1 S2 S3 * 119 * ---------------------------------------------------------------------------- * 120 * [[splitPtr]]--> v2 | field0 | field0 | field0 | field0 | * 121 * ---------------------------------------------------------------------------- * 122 * S4 S5 S6 S7 * 123 * ---------------------------------------------------------------------------- * 124 * v3 | field0 | field0 | field0 | field0 | * 125 * ---------------------------------------------------------------------------- * 126 * S0 S1 S2 S3 * 127 * ---------------------------------------------------------------------------- * 128 * v4 | field1 | field1 | field1 | field1 | * 129 * ---------------------------------------------------------------------------- * 130 * S4 S5 S6 S7 * 131 * ---------------------------------------------------------------------------- * 132 * v5 | field1 | field1 | field1 | field1 | * 133 * ---------------------------------------------------------------------------- * 134 * S0 S1 S2 S3 * 135 * ---------------------------------------------------------------------------- * 136 * v6 | field2 | field2 | field2 | field2 | * 137 * ---------------------------------------------------------------------------- * 138 * S4 S5 S6 S7 * 139 * ---------------------------------------------------------------------------- * 140 * v7 | field2 | field2 | field2 | field2 | * 141 * ---------------------------------------------------------------------------- * 142 * S0 S1 S2 S3 * 143 * ---------------------------------------------------------------------------- * 144 * v8 | field3 | field3 | field3 | field3 | * 145 * ---------------------------------------------------------------------------- * 146 * S4 S5 S6 S7 * 147 * ---------------------------------------------------------------------------- * 148 * v9 | field3 | field3 | field3 | field3 | * 149 * ---------------------------------------------------------------------------- * * 150 * * * 151 * * * 152 ******************************************************************************************************** 153 **/ 154 155 156 // buffer uop 157 val instMicroOp = Reg(new VSegmentBundle) 158 val instMicroOpValid = RegInit(false.B) 159 val data = Reg(Vec(maxSize, UInt(VLEN.W))) 160 val uopq = Reg(Vec(maxSize, new VSegmentUop)) 161 val stride = Reg(Vec(maxSize, UInt(VLEN.W))) 162 val allocated = RegInit(VecInit(Seq.fill(maxSize)(false.B))) 163 val enqPtr = RegInit(0.U.asTypeOf(new VSegUPtr)) 164 val deqPtr = RegInit(0.U.asTypeOf(new VSegUPtr)) 165 val stridePtr = WireInit(0.U.asTypeOf(new VSegUPtr)) // for select stride/index 166 167 val segmentIdx = RegInit(0.U(elemIdxBits.W)) 168 val fieldIdx = RegInit(0.U(fieldBits.W)) 169 val segmentOffset = RegInit(0.U(VAddrBits.W)) 170 val splitPtr = RegInit(0.U.asTypeOf(new VSegUPtr)) // for select load/store data 171 val splitPtrNext = WireInit(0.U.asTypeOf(new VSegUPtr)) 172 173 val exception_va = WireInit(false.B) 174 val exception_pa = WireInit(false.B) 175 176 val maxSegIdx = instMicroOp.vl - 1.U 177 val maxNfields = instMicroOp.uop.vpu.nf 178 val latchVaddr = RegInit(0.U(VAddrBits.W)) 179 180 XSError((segmentIdx > maxSegIdx) && instMicroOpValid, s"segmentIdx > vl, something error!\n") 181 XSError((fieldIdx > maxNfields) && instMicroOpValid, s"fieldIdx > nfields, something error!\n") 182 183 // MicroOp 184 val baseVaddr = instMicroOp.baseVaddr 185 val alignedType = instMicroOp.alignedType 186 val fuType = instMicroOp.uop.fuType 187 val mask = instMicroOp.mask 188 val exceptionVec = instMicroOp.uop.exceptionVec 189 val issueEew = instMicroOp.uop.vpu.veew 190 val issueLmul = instMicroOp.uop.vpu.vtype.vlmul 191 val issueSew = instMicroOp.uop.vpu.vtype.vsew 192 val issueEmul = EewLog2(issueEew) - issueSew + issueLmul 193 val elemIdxInVd = segmentIdx & instMicroOp.uopFlowNumMask 194 val issueInstType = Cat(true.B, instMicroOp.uop.fuOpType(6, 5)) // always segment instruction 195 val issueUopFlowNumLog2 = GenRealFlowLog2(issueInstType, issueEmul, issueLmul, issueEew, issueSew, true) // max element number log2 in vd 196 val issueVlMax = instMicroOp.uopFlowNum // max elementIdx in vd 197 val issueMaxIdxInIndex = GenVLMAX(Mux(issueEmul.asSInt > 0.S, 0.U, issueEmul), issueEew(1, 0)) // index element index in index register 198 val issueMaxIdxInIndexMask = GenVlMaxMask(issueMaxIdxInIndex, elemIdxBits) 199 val issueMaxIdxInIndexLog2 = GenVLMAXLog2(Mux(issueEmul.asSInt > 0.S, 0.U, issueEmul), issueEew(1, 0)) 200 val issueIndexIdx = segmentIdx & issueMaxIdxInIndexMask 201 val segmentActive = (mask & UIntToOH(segmentIdx)).orR 202 203 // Segment instruction's FSM 204 /* 205 * s_idle: wait request 206 * s_flush_sbuffer_req: flush sbuffer 207 * s_wait_flush_sbuffer_resp: wait sbuffer empty 208 * s_tlb_req: request tlb 209 * s_wait_tlb_resp: wait tlb resp 210 * s_pm: check pmp 211 * s_cache_req: request cache 212 * s_cache_resp: wait cache resp 213 * s_latch_and_merge_data: for read data 214 * s_send_data: for send write data 215 * s_finish: 216 * */ 217 val s_idle :: s_flush_sbuffer_req :: s_wait_flush_sbuffer_resp :: s_tlb_req :: s_wait_tlb_resp :: s_pm ::s_cache_req :: s_cache_resp :: s_latch_and_merge_data :: s_send_data :: s_finish :: Nil = Enum(11) 218 val state = RegInit(s_idle) 219 val stateNext = WireInit(s_idle) 220 val sbufferEmpty = io.flush_sbuffer.empty 221 222 /** 223 * state update 224 */ 225 state := stateNext 226 227 /** 228 * state transfer 229 */ 230 when(state === s_idle){ 231 stateNext := Mux(isAfter(enqPtr, deqPtr), s_flush_sbuffer_req, s_idle) 232 }.elsewhen(state === s_flush_sbuffer_req){ 233 stateNext := Mux(sbufferEmpty, s_tlb_req, s_wait_flush_sbuffer_resp) // if sbuffer is empty, go to query tlb 234 235 }.elsewhen(state === s_wait_flush_sbuffer_resp){ 236 stateNext := Mux(sbufferEmpty, s_tlb_req, s_wait_flush_sbuffer_resp) 237 238 }.elsewhen(state === s_tlb_req){ 239 stateNext := Mux(segmentActive, s_wait_tlb_resp, Mux(FuType.isVLoad(instMicroOp.uop.fuType), s_latch_and_merge_data, s_send_data)) 240 241 }.elsewhen(state === s_wait_tlb_resp){ 242 stateNext := Mux(io.dtlb.resp.fire, 243 Mux(!io.dtlb.resp.bits.miss, 244 s_pm, 245 s_tlb_req), 246 s_wait_tlb_resp) 247 248 }.elsewhen(state === s_pm){ 249 /* if is vStore, send data to sbuffer, so don't need query dcache */ 250 stateNext := Mux(exception_pa || exception_va, 251 s_finish, 252 Mux(FuType.isVLoad(instMicroOp.uop.fuType), s_cache_req, s_send_data)) 253 254 }.elsewhen(state === s_cache_req){ 255 stateNext := Mux(io.rdcache.req.fire, s_cache_resp, s_cache_req) 256 257 }.elsewhen(state === s_cache_resp){ 258 when(io.rdcache.resp.fire) { 259 when(io.rdcache.resp.bits.miss || io.rdcache.s2_bank_conflict) { 260 stateNext := s_cache_req 261 }.otherwise { 262 stateNext := Mux(FuType.isVLoad(instMicroOp.uop.fuType), s_latch_and_merge_data, s_send_data) 263 } 264 }.otherwise{ 265 stateNext := s_cache_resp 266 } 267 /* if segment is inactive, don't need to wait access all of the field */ 268 }.elsewhen(state === s_latch_and_merge_data) { 269 when((segmentIdx === maxSegIdx) && (fieldIdx === maxNfields) || 270 ((segmentIdx === maxSegIdx) && !segmentActive)) { 271 272 stateNext := s_finish // segment instruction finish 273 }.otherwise { 274 stateNext := s_tlb_req // need continue 275 } 276 /* if segment is inactive, don't need to wait access all of the field */ 277 }.elsewhen(state === s_send_data) { // when sbuffer accept data 278 when(!io.sbuffer.fire && segmentActive) { 279 stateNext := s_send_data 280 }.elsewhen(((segmentIdx === maxSegIdx) && (fieldIdx === maxNfields)) || 281 ((segmentIdx === maxSegIdx) && !segmentActive)) { 282 283 stateNext := s_finish // segment instruction finish 284 }.otherwise { 285 stateNext := s_tlb_req // need continue 286 } 287 }.elsewhen(state === s_finish){ // writeback uop 288 stateNext := Mux(distanceBetween(enqPtr, deqPtr) === 0.U, s_idle, s_finish) 289 290 }.otherwise{ 291 stateNext := s_idle 292 XSError(true.B, s"Unknown state!\n") 293 } 294 295 /************************************************************************* 296 * enqueue logic 297 *************************************************************************/ 298 io.in.ready := true.B 299 val fuOpType = io.in.bits.uop.fuOpType 300 val vtype = io.in.bits.uop.vpu.vtype 301 val mop = fuOpType(6, 5) 302 val instType = Cat(true.B, mop) 303 val eew = io.in.bits.uop.vpu.veew 304 val sew = vtype.vsew 305 val lmul = vtype.vlmul 306 val emul = EewLog2(eew) - sew + lmul 307 val vl = instMicroOp.vl 308 val vm = instMicroOp.uop.vpu.vm 309 val vstart = instMicroOp.uop.vpu.vstart 310 val srcMask = GenFlowMask(Mux(vm, Fill(VLEN, 1.U(1.W)), io.in.bits.src_mask), vstart, vl, true) 311 // first uop enqueue, we need to latch microOp of segment instruction 312 when(io.in.fire && !instMicroOpValid){ 313 // element number in a vd 314 // TODO Rewrite it in a more elegant way. 315 val uopFlowNum = ZeroExt(GenRealFlowNum(instType, emul, lmul, eew, sew, true), elemIdxBits) 316 instMicroOp.baseVaddr := io.in.bits.src_rs1(VAddrBits - 1, 0) 317 instMicroOpValid := true.B // if is first uop 318 instMicroOp.alignedType := Mux(isIndexed(instType), sew(1, 0), eew) 319 instMicroOp.uop := io.in.bits.uop 320 instMicroOp.mask := srcMask 321 instMicroOp.vstart := 0.U 322 instMicroOp.uopFlowNum := uopFlowNum 323 instMicroOp.uopFlowNumMask := GenVlMaxMask(uopFlowNum, elemIdxBits) // for merge data 324 instMicroOp.vl := io.in.bits.src_vl.asTypeOf(VConfig()).vl 325 segmentOffset := 0.U 326 instMicroOp.isFof := (fuOpType === VlduType.vleff) && FuType.isVLoad(fuType) 327 } 328 // latch data 329 when(io.in.fire){ 330 data(enqPtr.value) := io.in.bits.src_vs3 331 stride(enqPtr.value) := io.in.bits.src_stride 332 uopq(enqPtr.value).uop := io.in.bits.uop 333 } 334 335 // update enqptr, only 1 port 336 when(io.in.fire){ 337 enqPtr := enqPtr + 1.U 338 } 339 340 /************************************************************************* 341 * output logic 342 *************************************************************************/ 343 344 val indexStride = IndexAddr( // index for indexed instruction 345 index = stride(stridePtr.value), 346 flow_inner_idx = issueIndexIdx, 347 eew = issueEew 348 ) 349 val realSegmentOffset = Mux(isIndexed(issueInstType), 350 indexStride, 351 segmentOffset) 352 val vaddr = baseVaddr + (fieldIdx << alignedType).asUInt + realSegmentOffset 353 354 //latch vaddr 355 when(state === s_tlb_req){ 356 latchVaddr := vaddr 357 } 358 /** 359 * tlb req and tlb resq 360 */ 361 362 // query DTLB IO Assign 363 io.dtlb.req := DontCare 364 io.dtlb.resp.ready := true.B 365 io.dtlb.req.valid := state === s_tlb_req && segmentActive 366 io.dtlb.req.bits.cmd := Mux(FuType.isVLoad(fuType), TlbCmd.read, TlbCmd.write) 367 io.dtlb.req.bits.vaddr := vaddr 368 io.dtlb.req.bits.size := instMicroOp.alignedType(2,0) 369 io.dtlb.req.bits.memidx.is_ld := FuType.isVLoad(fuType) 370 io.dtlb.req.bits.memidx.is_st := FuType.isVStore(fuType) 371 io.dtlb.req.bits.debug.robIdx := instMicroOp.uop.robIdx 372 io.dtlb.req.bits.no_translate := false.B 373 io.dtlb.req.bits.debug.pc := instMicroOp.uop.pc 374 io.dtlb.req.bits.debug.isFirstIssue := DontCare 375 io.dtlb.req_kill := false.B 376 377 val canTriggerException = segmentIdx === 0.U || !instMicroOp.isFof // only elementIdx = 0 or is not fof can trigger 378 // tlb resp 379 when(io.dtlb.resp.fire && state === s_wait_tlb_resp){ 380 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp(0).pf.st && canTriggerException 381 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp(0).pf.ld && canTriggerException 382 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp(0).af.st && canTriggerException 383 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp(0).af.ld && canTriggerException 384 when(!io.dtlb.resp.bits.miss){ 385 instMicroOp.paddr := io.dtlb.resp.bits.paddr(0) 386 } 387 } 388 // pmp 389 // NOTE: only handle load/store exception here, if other exception happens, don't send here 390 val pmp = WireInit(io.pmpResp) 391 when(state === s_pm) { 392 val addr_aligned = LookupTree(Mux(isIndexed(issueInstType), issueSew(1, 0), issueEew(1, 0)), List( 393 "b00".U -> true.B, //b 394 "b01".U -> (vaddr(0) === 0.U), //h 395 "b10".U -> (vaddr(1, 0) === 0.U), //w 396 "b11".U -> (vaddr(2, 0) === 0.U) //d 397 )) 398 val missAligned = !addr_aligned 399 exceptionVec(loadAddrMisaligned) := !addr_aligned && FuType.isVLoad(fuType) && canTriggerException 400 exceptionVec(storeAddrMisaligned) := !addr_aligned && !FuType.isVLoad(fuType) && canTriggerException 401 402 exception_va := exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 403 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) || (missAligned && canTriggerException) 404 exception_pa := (pmp.st || pmp.ld || pmp.mmio) && canTriggerException 405 406 instMicroOp.exception_pa := exception_pa 407 instMicroOp.exception_va := exception_va 408 // update storeAccessFault bit. Currently, we don't support vector MMIO 409 exceptionVec(loadAccessFault) := (exceptionVec(loadAccessFault) || pmp.ld || pmp.mmio) && canTriggerException 410 exceptionVec(storeAccessFault) := (exceptionVec(storeAccessFault) || pmp.st || pmp.mmio) && canTriggerException 411 412 when(exception_va || exception_pa) { 413 when(canTriggerException) { 414 instMicroOp.exceptionVaddr := vaddr 415 instMicroOp.exceptionVl := segmentIdx // for exception 416 instMicroOp.exceptionVstart := segmentIdx // for exception 417 }.otherwise { 418 instMicroOp.exceptionVl := segmentIdx 419 } 420 } 421 } 422 423 /** 424 * flush sbuffer IO Assign 425 */ 426 io.flush_sbuffer.valid := !sbufferEmpty && (state === s_flush_sbuffer_req) 427 428 429 /** 430 * merge data for load 431 */ 432 val cacheData = LookupTree(latchVaddr(3,0), List( 433 "b0000".U -> io.rdcache.resp.bits.data_delayed(63, 0), 434 "b0001".U -> io.rdcache.resp.bits.data_delayed(63, 8), 435 "b0010".U -> io.rdcache.resp.bits.data_delayed(63, 16), 436 "b0011".U -> io.rdcache.resp.bits.data_delayed(63, 24), 437 "b0100".U -> io.rdcache.resp.bits.data_delayed(63, 32), 438 "b0101".U -> io.rdcache.resp.bits.data_delayed(63, 40), 439 "b0110".U -> io.rdcache.resp.bits.data_delayed(63, 48), 440 "b0111".U -> io.rdcache.resp.bits.data_delayed(63, 56), 441 "b1000".U -> io.rdcache.resp.bits.data_delayed(127, 64), 442 "b1001".U -> io.rdcache.resp.bits.data_delayed(127, 72), 443 "b1010".U -> io.rdcache.resp.bits.data_delayed(127, 80), 444 "b1011".U -> io.rdcache.resp.bits.data_delayed(127, 88), 445 "b1100".U -> io.rdcache.resp.bits.data_delayed(127, 96), 446 "b1101".U -> io.rdcache.resp.bits.data_delayed(127, 104), 447 "b1110".U -> io.rdcache.resp.bits.data_delayed(127, 112), 448 "b1111".U -> io.rdcache.resp.bits.data_delayed(127, 120) 449 )) 450 val pickData = rdataVecHelper(alignedType(1,0), cacheData) 451 val mergedData = mergeDataWithElemIdx( 452 oldData = data(splitPtr.value), 453 newData = Seq(pickData), 454 alignedType = alignedType(1,0), 455 elemIdx = Seq(elemIdxInVd), 456 valids = Seq(true.B) 457 ) 458 when(state === s_latch_and_merge_data && segmentActive){ 459 data(splitPtr.value) := mergedData 460 } 461 /** 462 * split data for store 463 * */ 464 val splitData = genVSData( 465 data = data(splitPtr.value), 466 elemIdx = elemIdxInVd, 467 alignedType = alignedType 468 ) 469 val flowData = genVWdata(splitData, alignedType) // TODO: connect vstd, pass vector data 470 val wmask = genVWmask(latchVaddr, alignedType(1, 0)) & Fill(VLENB, segmentActive) 471 472 /** 473 * rdcache req, write request don't need to query dcache, because we write element to sbuffer 474 */ 475 io.rdcache.req := DontCare 476 io.rdcache.req.valid := state === s_cache_req && FuType.isVLoad(fuType) 477 io.rdcache.req.bits.cmd := MemoryOpConstants.M_XRD 478 io.rdcache.req.bits.vaddr := latchVaddr 479 io.rdcache.req.bits.mask := mask 480 io.rdcache.req.bits.data := flowData 481 io.rdcache.pf_source := LOAD_SOURCE.U 482 io.rdcache.req.bits.id := DontCare 483 io.rdcache.resp.ready := true.B 484 io.rdcache.s1_paddr_dup_lsu := instMicroOp.paddr 485 io.rdcache.s1_paddr_dup_dcache := instMicroOp.paddr 486 io.rdcache.s1_kill := false.B 487 io.rdcache.s2_kill := false.B 488 if (env.FPGAPlatform){ 489 io.rdcache.s0_pc := DontCare 490 io.rdcache.s1_pc := DontCare 491 io.rdcache.s2_pc := DontCare 492 }else{ 493 io.rdcache.s0_pc := instMicroOp.uop.pc 494 io.rdcache.s1_pc := instMicroOp.uop.pc 495 io.rdcache.s2_pc := instMicroOp.uop.pc 496 } 497 io.rdcache.replacementUpdated := false.B 498 io.rdcache.is128Req := false.B 499 500 501 /** 502 * write data to sbuffer 503 * */ 504 505 io.sbuffer.bits := DontCare 506 io.sbuffer.valid := state === s_send_data && segmentActive 507 io.sbuffer.bits.vecValid := state === s_send_data && segmentActive 508 io.sbuffer.bits.mask := wmask 509 io.sbuffer.bits.data := flowData 510 io.sbuffer.bits.vaddr := latchVaddr 511 io.sbuffer.bits.cmd := MemoryOpConstants.M_XWR 512 io.sbuffer.bits.id := DontCare 513 io.sbuffer.bits.addr := instMicroOp.paddr 514 515 io.vecDifftestInfo.valid := state === s_send_data && segmentActive 516 io.vecDifftestInfo.bits := uopq(deqPtr.value).uop 517 518 /** 519 * update ptr 520 * */ 521 private val fieldActiveWirteFinish = io.sbuffer.fire && segmentActive // writedata finish and is a active segment 522 XSError(io.sbuffer.fire && !segmentActive, "Attempt write inactive segment to sbuffer, something wrong!\n") 523 524 private val segmentInactiveFinish = ((state === s_latch_and_merge_data) || (state === s_send_data)) && !segmentActive 525 526 val splitPtrOffset = Mux( 527 isIndexed(instType), 528 Mux(lmul.asSInt < 0.S, 1.U, (1.U << lmul).asUInt), 529 Mux(emul.asSInt < 0.S, 1.U, (1.U << emul).asUInt) 530 ) 531 splitPtrNext := 532 Mux(fieldIdx === maxNfields || !segmentActive, // if segment is active, need to complete this segment, otherwise jump to next segment 533 // segment finish, By shifting 'issueUopFlowNumLog2' to the right to ensure that emul != 1 can correctly generate lateral offset. 534 (deqPtr + ((segmentIdx +& 1.U) >> issueUopFlowNumLog2).asUInt), 535 // next field. 536 (splitPtr + splitPtrOffset) 537 ) 538 539 dontTouch(issueUopFlowNumLog2) 540 dontTouch(issueEmul) 541 dontTouch(splitPtrNext) 542 dontTouch(stridePtr) 543 dontTouch(segmentActive) 544 545 // update splitPtr 546 when(state === s_latch_and_merge_data || (state === s_send_data && (fieldActiveWirteFinish || !segmentActive))){ 547 splitPtr := splitPtrNext 548 }.elsewhen(io.in.fire && !instMicroOpValid){ 549 splitPtr := deqPtr // initial splitPtr 550 } 551 552 // update stridePtr, only use in index 553 val strideOffset = Mux(isIndexed(issueInstType), segmentIdx >> issueMaxIdxInIndexLog2, 0.U) 554 stridePtr := deqPtr + strideOffset 555 556 // update fieldIdx 557 when(io.in.fire && !instMicroOpValid){ // init 558 fieldIdx := 0.U 559 }.elsewhen(state === s_latch_and_merge_data && segmentActive || 560 (state === s_send_data && fieldActiveWirteFinish)){ // only if segment is active 561 562 /* next segment, only if segment complete */ 563 fieldIdx := Mux(fieldIdx === maxNfields, 0.U, fieldIdx + 1.U) 564 }.elsewhen(segmentInactiveFinish){ // segment is inactive, go to next segment 565 fieldIdx := 0.U 566 } 567 //update segmentIdx 568 when(io.in.fire && !instMicroOpValid){ 569 segmentIdx := 0.U 570 }.elsewhen(fieldIdx === maxNfields && (state === s_latch_and_merge_data || (state === s_send_data && fieldActiveWirteFinish)) && 571 segmentIdx =/= maxSegIdx){ // next segment, only if segment is active 572 573 segmentIdx := segmentIdx + 1.U 574 }.elsewhen(segmentInactiveFinish && segmentIdx =/= maxSegIdx){ // if segment is inactive, go to next segment 575 segmentIdx := segmentIdx + 1.U 576 } 577 578 //update segmentOffset 579 /* when segment is active or segment is inactive, increase segmentOffset */ 580 when((fieldIdx === maxNfields && (state === s_latch_and_merge_data || (state === s_send_data && fieldActiveWirteFinish))) || 581 segmentInactiveFinish){ 582 583 segmentOffset := segmentOffset + Mux(isUnitStride(issueInstType), (maxNfields +& 1.U) << issueEew(1, 0), stride(stridePtr.value)) 584 } 585 586 //update deqPtr 587 when(io.uopwriteback.fire){ 588 deqPtr := deqPtr + 1.U 589 } 590 591 /************************************************************************* 592 * dequeue logic 593 *************************************************************************/ 594 val vdIdxInField = GenUopIdxInField(Mux(isIndexed(instType), issueLmul, issueEmul), uopq(deqPtr.value).uop.vpu.vuopIdx) 595 /*select mask of vd, maybe remove in feature*/ 596 val realEw = Mux(isIndexed(issueInstType), issueSew(1, 0), issueEew(1, 0)) 597 val maskDataVec: Vec[UInt] = VecDataToMaskDataVec(instMicroOp.mask, realEw) 598 val maskUsed = maskDataVec(vdIdxInField) 599 600 when(stateNext === s_idle){ 601 instMicroOpValid := false.B 602 } 603 io.uopwriteback.valid := (state === s_finish) && !isEmpty(enqPtr, deqPtr) 604 io.uopwriteback.bits.uop := uopq(deqPtr.value).uop 605 io.uopwriteback.bits.uop.vpu := instMicroOp.uop.vpu 606 io.uopwriteback.bits.uop.exceptionVec := instMicroOp.uop.exceptionVec 607 io.uopwriteback.bits.mask.get := instMicroOp.mask 608 io.uopwriteback.bits.data := data(deqPtr.value) 609 io.uopwriteback.bits.vdIdx.get := vdIdxInField 610 io.uopwriteback.bits.uop.vpu.vl := instMicroOp.vl 611 io.uopwriteback.bits.uop.vpu.vstart := instMicroOp.vstart 612 io.uopwriteback.bits.uop.vpu.vmask := maskUsed 613 io.uopwriteback.bits.uop.vpu.vuopIdx := uopq(deqPtr.value).uop.vpu.vuopIdx 614 io.uopwriteback.bits.debug := DontCare 615 io.uopwriteback.bits.vdIdxInField.get := vdIdxInField 616 io.uopwriteback.bits.uop.robIdx := instMicroOp.uop.robIdx 617 io.uopwriteback.bits.uop.fuOpType := instMicroOp.uop.fuOpType 618 619 //to RS 620 io.feedback.valid := state === s_finish && !isEmpty(enqPtr, deqPtr) 621 io.feedback.bits.hit := true.B 622 io.feedback.bits.robIdx := instMicroOp.uop.robIdx 623 io.feedback.bits.sourceType := DontCare 624 io.feedback.bits.flushState := DontCare 625 io.feedback.bits.dataInvalidSqIdx := DontCare 626 io.feedback.bits.sqIdx := uopq(deqPtr.value).uop.sqIdx 627 io.feedback.bits.lqIdx := uopq(deqPtr.value).uop.lqIdx 628 629 // exception 630 io.exceptionInfo := DontCare 631 io.exceptionInfo.bits.robidx := instMicroOp.uop.robIdx 632 io.exceptionInfo.bits.uopidx := uopq(deqPtr.value).uop.vpu.vuopIdx 633 io.exceptionInfo.bits.vstart := instMicroOp.exceptionVstart 634 io.exceptionInfo.bits.vaddr := instMicroOp.exceptionVaddr 635 io.exceptionInfo.bits.vl := instMicroOp.exceptionVl 636 io.exceptionInfo.valid := (state === s_finish) && instMicroOp.uop.exceptionVec.asUInt.orR && !isEmpty(enqPtr, deqPtr) 637} 638 639