1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.rob.RobPtr 26import xiangshan.backend.Bundles._ 27import xiangshan.mem._ 28import xiangshan.backend.fu.FuType 29import freechips.rocketchip.diplomacy.BufferParams 30import xiangshan.cache.mmu._ 31import xiangshan.cache._ 32import xiangshan.cache.wpu.ReplayCarry 33import xiangshan.backend.fu.util.SdtrigExt 34import xiangshan.ExceptionNO._ 35import xiangshan.backend.fu.vector.Bundles.VConfig 36import xiangshan.backend.datapath.NewPipelineConnect 37import xiangshan.backend.fu.vector.Utils.VecDataToMaskDataVec 38 39class VSegmentBundle(implicit p: Parameters) extends VLSUBundle 40{ 41 val baseVaddr = UInt(VAddrBits.W) 42 val uop = new DynInst 43 val paddr = UInt(PAddrBits.W) 44 val mask = UInt(VLEN.W) 45 val alignedType = UInt(alignTypeBits.W) 46 val vl = UInt(elemIdxBits.W) 47 val uopFlowNum = UInt(elemIdxBits.W) 48 val uopFlowNumMask = UInt(elemIdxBits.W) 49 // for exception 50 val vstart = UInt(elemIdxBits.W) 51 val exceptionVaddr = UInt(VAddrBits.W) 52 val exception_va = Bool() 53 val exception_pa = Bool() 54 val exceptionVstart = UInt(elemIdxBits.W) 55 val exceptionVl = UInt(elemIdxBits.W) 56 val isFof = Bool() 57} 58 59// latch each uop's VecWen, pdest, v0Wen, uopIdx 60class VSegmentUop(implicit p: Parameters) extends VLSUBundle{ 61 val uop = new DynInst 62} 63 64class VSegmentUnit (implicit p: Parameters) extends VLSUModule 65 with HasDCacheParameters 66 with MemoryOpConstants 67 with SdtrigExt 68 with HasLoadHelper 69{ 70 val io = IO(new VSegmentUnitIO) 71 72 val maxSize = VSegmentBufferSize 73 74 class VSegUPtr(implicit p: Parameters) extends CircularQueuePtr[VSegUPtr](maxSize){ 75 } 76 77 object VSegUPtr { 78 def apply(f: Bool, v: UInt)(implicit p: Parameters): VSegUPtr = { 79 val ptr = Wire(new VSegUPtr) 80 ptr.flag := f 81 ptr.value := v 82 ptr 83 } 84 } 85 86 87 /** 88 ******************************************************************************************************** 89 * Use an example to illustrate the working logic of a segmentunit: * 90 * For: * 91 * lmul=2 sew=32 emul=2 eew=32 vl=16 * 92 * Then: * 93 * Access memory in the order: * 94 * (V2,S0),(V4,S0),(V6,S0),(V8,S0), * 95 * (V2,S1),(V4,S1),(V6,S1),(V8,S1), * 96 * (V2,S2),(V4,S2),(V6,S2),(V8,S2), * 97 * (V2,S3),(V4,S3),(V6,S3),(V8,S3), * 98 * (V3,S4),(V5,S4),(V7,S4),(V9,S4), * 99 * (V3,S5),(V5,S5),(V7,S5),(V9,S5), * 100 * (V3,S6),(V5,S6),(V7,S6),(V9,S6), * 101 * (V3,S7),(V5,S7),(V7,S7),(V9,S7), * 102 * * 103 * * 104 * [[data]] saves the data generated by the access and corresponds to the register. * 105 * [[splitPtr]] controls the destination register written to. * 106 * * 107 * splitptr offset can be seen in [[splitPtrNext]] is assignment logic, * 108 * which is mainly calculated in terms of [[fieldIdx]] and [[segmentIdx]] * 109 * First access different fields of the same segment, and then visit different segments. * 110 * For the case of 'emul' greater than 1, such as the following example, * 111 * although 'v2' and 'v3' are different vd and the same field, they are still different segments, * 112 * so they should be accessed sequentially.Just like the 'Access memory in the order' above. * 113 * * 114 * [[segmentIdx]] * 115 * | * 116 * | * 117 * V * 118 * * 119 * S0 S1 S2 S3 * 120 * ---------------------------------------------------------------------------- * 121 * [[splitPtr]]--> v2 | field0 | field0 | field0 | field0 | * 122 * ---------------------------------------------------------------------------- * 123 * S4 S5 S6 S7 * 124 * ---------------------------------------------------------------------------- * 125 * v3 | field0 | field0 | field0 | field0 | * 126 * ---------------------------------------------------------------------------- * 127 * S0 S1 S2 S3 * 128 * ---------------------------------------------------------------------------- * 129 * v4 | field1 | field1 | field1 | field1 | * 130 * ---------------------------------------------------------------------------- * 131 * S4 S5 S6 S7 * 132 * ---------------------------------------------------------------------------- * 133 * v5 | field1 | field1 | field1 | field1 | * 134 * ---------------------------------------------------------------------------- * 135 * S0 S1 S2 S3 * 136 * ---------------------------------------------------------------------------- * 137 * v6 | field2 | field2 | field2 | field2 | * 138 * ---------------------------------------------------------------------------- * 139 * S4 S5 S6 S7 * 140 * ---------------------------------------------------------------------------- * 141 * v7 | field2 | field2 | field2 | field2 | * 142 * ---------------------------------------------------------------------------- * 143 * S0 S1 S2 S3 * 144 * ---------------------------------------------------------------------------- * 145 * v8 | field3 | field3 | field3 | field3 | * 146 * ---------------------------------------------------------------------------- * 147 * S4 S5 S6 S7 * 148 * ---------------------------------------------------------------------------- * 149 * v9 | field3 | field3 | field3 | field3 | * 150 * ---------------------------------------------------------------------------- * * 151 * * * 152 * * * 153 ******************************************************************************************************** 154 **/ 155 156 157 // buffer uop 158 val instMicroOp = Reg(new VSegmentBundle) 159 val instMicroOpValid = RegInit(false.B) 160 val data = Reg(Vec(maxSize, UInt(VLEN.W))) 161 val uopq = Reg(Vec(maxSize, new VSegmentUop)) 162 val stride = Reg(Vec(maxSize, UInt(VLEN.W))) 163 val allocated = RegInit(VecInit(Seq.fill(maxSize)(false.B))) 164 val enqPtr = RegInit(0.U.asTypeOf(new VSegUPtr)) 165 val deqPtr = RegInit(0.U.asTypeOf(new VSegUPtr)) 166 val stridePtr = WireInit(0.U.asTypeOf(new VSegUPtr)) // for select stride/index 167 168 val segmentIdx = RegInit(0.U(elemIdxBits.W)) 169 val fieldIdx = RegInit(0.U(fieldBits.W)) 170 val segmentOffset = RegInit(0.U(VAddrBits.W)) 171 val splitPtr = RegInit(0.U.asTypeOf(new VSegUPtr)) // for select load/store data 172 val splitPtrNext = WireInit(0.U.asTypeOf(new VSegUPtr)) 173 174 val exception_va = WireInit(false.B) 175 val exception_pa = WireInit(false.B) 176 177 val maxSegIdx = instMicroOp.vl - 1.U 178 val maxNfields = instMicroOp.uop.vpu.nf 179 val latchVaddr = RegInit(0.U(VAddrBits.W)) 180 181 XSError((segmentIdx > maxSegIdx) && instMicroOpValid, s"segmentIdx > vl, something error!\n") 182 XSError((fieldIdx > maxNfields) && instMicroOpValid, s"fieldIdx > nfields, something error!\n") 183 184 // MicroOp 185 val baseVaddr = instMicroOp.baseVaddr 186 val alignedType = instMicroOp.alignedType 187 val fuType = instMicroOp.uop.fuType 188 val mask = instMicroOp.mask 189 val exceptionVec = instMicroOp.uop.exceptionVec 190 val issueEew = instMicroOp.uop.vpu.veew 191 val issueLmul = instMicroOp.uop.vpu.vtype.vlmul 192 val issueSew = instMicroOp.uop.vpu.vtype.vsew 193 val issueEmul = EewLog2(issueEew) - issueSew + issueLmul 194 val elemIdxInVd = segmentIdx & instMicroOp.uopFlowNumMask 195 val issueInstType = Cat(true.B, instMicroOp.uop.fuOpType(6, 5)) // always segment instruction 196 val issueUopFlowNumLog2 = GenRealFlowLog2(issueInstType, issueEmul, issueLmul, issueEew, issueSew, true) // max element number log2 in vd 197 val issueVlMax = instMicroOp.uopFlowNum // max elementIdx in vd 198 val issueMaxIdxInIndex = GenVLMAX(Mux(issueEmul.asSInt > 0.S, 0.U, issueEmul), issueEew(1, 0)) // index element index in index register 199 val issueMaxIdxInIndexMask = GenVlMaxMask(issueMaxIdxInIndex, elemIdxBits) 200 val issueMaxIdxInIndexLog2 = GenVLMAXLog2(Mux(issueEmul.asSInt > 0.S, 0.U, issueEmul), issueEew(1, 0)) 201 val issueIndexIdx = segmentIdx & issueMaxIdxInIndexMask 202 val segmentActive = (mask & UIntToOH(segmentIdx)).orR 203 204 // sbuffer write interface 205 val sbufferOut = Wire(Decoupled(new DCacheWordReqWithVaddrAndPfFlag)) 206 207 // Segment instruction's FSM 208 /* 209 * s_idle: wait request 210 * s_flush_sbuffer_req: flush sbuffer 211 * s_wait_flush_sbuffer_resp: wait sbuffer empty 212 * s_tlb_req: request tlb 213 * s_wait_tlb_resp: wait tlb resp 214 * s_pm: check pmp 215 * s_cache_req: request cache 216 * s_cache_resp: wait cache resp 217 * s_latch_and_merge_data: for read data 218 * s_send_data: for send write data 219 * s_finish: 220 * */ 221 val s_idle :: s_flush_sbuffer_req :: s_wait_flush_sbuffer_resp :: s_tlb_req :: s_wait_tlb_resp :: s_pm ::s_cache_req :: s_cache_resp :: s_latch_and_merge_data :: s_send_data :: s_finish :: Nil = Enum(11) 222 val state = RegInit(s_idle) 223 val stateNext = WireInit(s_idle) 224 val sbufferEmpty = io.flush_sbuffer.empty 225 226 /** 227 * state update 228 */ 229 state := stateNext 230 231 /** 232 * state transfer 233 */ 234 when(state === s_idle){ 235 stateNext := Mux(isAfter(enqPtr, deqPtr), s_flush_sbuffer_req, s_idle) 236 }.elsewhen(state === s_flush_sbuffer_req){ 237 stateNext := Mux(sbufferEmpty, s_tlb_req, s_wait_flush_sbuffer_resp) // if sbuffer is empty, go to query tlb 238 239 }.elsewhen(state === s_wait_flush_sbuffer_resp){ 240 stateNext := Mux(sbufferEmpty, s_tlb_req, s_wait_flush_sbuffer_resp) 241 242 }.elsewhen(state === s_tlb_req){ 243 stateNext := Mux(segmentActive, s_wait_tlb_resp, Mux(FuType.isVLoad(instMicroOp.uop.fuType), s_latch_and_merge_data, s_send_data)) 244 245 }.elsewhen(state === s_wait_tlb_resp){ 246 stateNext := Mux(io.dtlb.resp.fire, 247 Mux(!io.dtlb.resp.bits.miss, 248 s_pm, 249 s_tlb_req), 250 s_wait_tlb_resp) 251 252 }.elsewhen(state === s_pm){ 253 /* if is vStore, send data to sbuffer, so don't need query dcache */ 254 stateNext := Mux(exception_pa || exception_va, 255 s_finish, 256 Mux(FuType.isVLoad(instMicroOp.uop.fuType), s_cache_req, s_send_data)) 257 258 }.elsewhen(state === s_cache_req){ 259 stateNext := Mux(io.rdcache.req.fire, s_cache_resp, s_cache_req) 260 261 }.elsewhen(state === s_cache_resp){ 262 when(io.rdcache.resp.fire) { 263 when(io.rdcache.resp.bits.miss || io.rdcache.s2_bank_conflict) { 264 stateNext := s_cache_req 265 }.otherwise { 266 stateNext := Mux(FuType.isVLoad(instMicroOp.uop.fuType), s_latch_and_merge_data, s_send_data) 267 } 268 }.otherwise{ 269 stateNext := s_cache_resp 270 } 271 /* if segment is inactive, don't need to wait access all of the field */ 272 }.elsewhen(state === s_latch_and_merge_data) { 273 when((segmentIdx === maxSegIdx) && (fieldIdx === maxNfields) || 274 ((segmentIdx === maxSegIdx) && !segmentActive)) { 275 276 stateNext := s_finish // segment instruction finish 277 }.otherwise { 278 stateNext := s_tlb_req // need continue 279 } 280 /* if segment is inactive, don't need to wait access all of the field */ 281 }.elsewhen(state === s_send_data) { // when sbuffer accept data 282 when(!sbufferOut.fire && segmentActive) { 283 stateNext := s_send_data 284 }.elsewhen(((segmentIdx === maxSegIdx) && (fieldIdx === maxNfields)) || 285 ((segmentIdx === maxSegIdx) && !segmentActive)) { 286 287 stateNext := s_finish // segment instruction finish 288 }.otherwise { 289 stateNext := s_tlb_req // need continue 290 } 291 }.elsewhen(state === s_finish){ // writeback uop 292 stateNext := Mux(distanceBetween(enqPtr, deqPtr) === 0.U, s_idle, s_finish) 293 294 }.otherwise{ 295 stateNext := s_idle 296 XSError(true.B, s"Unknown state!\n") 297 } 298 299 /************************************************************************* 300 * enqueue logic 301 *************************************************************************/ 302 io.in.ready := true.B 303 val fuOpType = io.in.bits.uop.fuOpType 304 val vtype = io.in.bits.uop.vpu.vtype 305 val mop = fuOpType(6, 5) 306 val instType = Cat(true.B, mop) 307 val eew = io.in.bits.uop.vpu.veew 308 val sew = vtype.vsew 309 val lmul = vtype.vlmul 310 val emul = EewLog2(eew) - sew + lmul 311 val vl = instMicroOp.vl 312 val vm = instMicroOp.uop.vpu.vm 313 val vstart = instMicroOp.uop.vpu.vstart 314 val srcMask = GenFlowMask(Mux(vm, Fill(VLEN, 1.U(1.W)), io.in.bits.src_mask), vstart, vl, true) 315 // first uop enqueue, we need to latch microOp of segment instruction 316 when(io.in.fire && !instMicroOpValid){ 317 // element number in a vd 318 // TODO Rewrite it in a more elegant way. 319 val uopFlowNum = ZeroExt(GenRealFlowNum(instType, emul, lmul, eew, sew, true), elemIdxBits) 320 instMicroOp.baseVaddr := io.in.bits.src_rs1(VAddrBits - 1, 0) 321 instMicroOpValid := true.B // if is first uop 322 instMicroOp.alignedType := Mux(isIndexed(instType), sew(1, 0), eew) 323 instMicroOp.uop := io.in.bits.uop 324 instMicroOp.mask := srcMask 325 instMicroOp.vstart := 0.U 326 instMicroOp.uopFlowNum := uopFlowNum 327 instMicroOp.uopFlowNumMask := GenVlMaxMask(uopFlowNum, elemIdxBits) // for merge data 328 instMicroOp.vl := io.in.bits.src_vl.asTypeOf(VConfig()).vl 329 segmentOffset := 0.U 330 instMicroOp.isFof := (fuOpType === VlduType.vleff) && FuType.isVLoad(fuType) 331 } 332 // latch data 333 when(io.in.fire){ 334 data(enqPtr.value) := io.in.bits.src_vs3 335 stride(enqPtr.value) := io.in.bits.src_stride 336 uopq(enqPtr.value).uop := io.in.bits.uop 337 } 338 339 // update enqptr, only 1 port 340 when(io.in.fire){ 341 enqPtr := enqPtr + 1.U 342 } 343 344 /************************************************************************* 345 * output logic 346 *************************************************************************/ 347 348 val indexStride = IndexAddr( // index for indexed instruction 349 index = stride(stridePtr.value), 350 flow_inner_idx = issueIndexIdx, 351 eew = issueEew 352 ) 353 val realSegmentOffset = Mux(isIndexed(issueInstType), 354 indexStride, 355 segmentOffset) 356 val vaddr = baseVaddr + (fieldIdx << alignedType).asUInt + realSegmentOffset 357 358 //latch vaddr 359 when(state === s_tlb_req){ 360 latchVaddr := vaddr 361 } 362 /** 363 * tlb req and tlb resq 364 */ 365 366 // query DTLB IO Assign 367 io.dtlb.req := DontCare 368 io.dtlb.resp.ready := true.B 369 io.dtlb.req.valid := state === s_tlb_req && segmentActive 370 io.dtlb.req.bits.cmd := Mux(FuType.isVLoad(fuType), TlbCmd.read, TlbCmd.write) 371 io.dtlb.req.bits.vaddr := vaddr 372 io.dtlb.req.bits.size := instMicroOp.alignedType(2,0) 373 io.dtlb.req.bits.memidx.is_ld := FuType.isVLoad(fuType) 374 io.dtlb.req.bits.memidx.is_st := FuType.isVStore(fuType) 375 io.dtlb.req.bits.debug.robIdx := instMicroOp.uop.robIdx 376 io.dtlb.req.bits.no_translate := false.B 377 io.dtlb.req.bits.debug.pc := instMicroOp.uop.pc 378 io.dtlb.req.bits.debug.isFirstIssue := DontCare 379 io.dtlb.req_kill := false.B 380 381 val canTriggerException = segmentIdx === 0.U || !instMicroOp.isFof // only elementIdx = 0 or is not fof can trigger 382 // tlb resp 383 when(io.dtlb.resp.fire && state === s_wait_tlb_resp){ 384 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp(0).pf.st && canTriggerException 385 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp(0).pf.ld && canTriggerException 386 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp(0).af.st && canTriggerException 387 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp(0).af.ld && canTriggerException 388 when(!io.dtlb.resp.bits.miss){ 389 instMicroOp.paddr := io.dtlb.resp.bits.paddr(0) 390 } 391 } 392 // pmp 393 // NOTE: only handle load/store exception here, if other exception happens, don't send here 394 val pmp = WireInit(io.pmpResp) 395 when(state === s_pm) { 396 val addr_aligned = LookupTree(Mux(isIndexed(issueInstType), issueSew(1, 0), issueEew(1, 0)), List( 397 "b00".U -> true.B, //b 398 "b01".U -> (vaddr(0) === 0.U), //h 399 "b10".U -> (vaddr(1, 0) === 0.U), //w 400 "b11".U -> (vaddr(2, 0) === 0.U) //d 401 )) 402 val missAligned = !addr_aligned 403 exceptionVec(loadAddrMisaligned) := !addr_aligned && FuType.isVLoad(fuType) && canTriggerException 404 exceptionVec(storeAddrMisaligned) := !addr_aligned && !FuType.isVLoad(fuType) && canTriggerException 405 406 exception_va := exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 407 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) || (missAligned && canTriggerException) 408 exception_pa := (pmp.st || pmp.ld || pmp.mmio) && canTriggerException 409 410 instMicroOp.exception_pa := exception_pa 411 instMicroOp.exception_va := exception_va 412 // update storeAccessFault bit. Currently, we don't support vector MMIO 413 exceptionVec(loadAccessFault) := (exceptionVec(loadAccessFault) || pmp.ld || pmp.mmio) && canTriggerException 414 exceptionVec(storeAccessFault) := (exceptionVec(storeAccessFault) || pmp.st || pmp.mmio) && canTriggerException 415 416 when(exception_va || exception_pa) { 417 when(canTriggerException) { 418 instMicroOp.exceptionVaddr := vaddr 419 instMicroOp.exceptionVl := segmentIdx // for exception 420 instMicroOp.exceptionVstart := segmentIdx // for exception 421 }.otherwise { 422 instMicroOp.exceptionVl := segmentIdx 423 } 424 } 425 } 426 427 /** 428 * flush sbuffer IO Assign 429 */ 430 io.flush_sbuffer.valid := !sbufferEmpty && (state === s_flush_sbuffer_req) 431 432 433 /** 434 * merge data for load 435 */ 436 val cacheData = LookupTree(latchVaddr(3,0), List( 437 "b0000".U -> io.rdcache.resp.bits.data_delayed(63, 0), 438 "b0001".U -> io.rdcache.resp.bits.data_delayed(63, 8), 439 "b0010".U -> io.rdcache.resp.bits.data_delayed(63, 16), 440 "b0011".U -> io.rdcache.resp.bits.data_delayed(63, 24), 441 "b0100".U -> io.rdcache.resp.bits.data_delayed(63, 32), 442 "b0101".U -> io.rdcache.resp.bits.data_delayed(63, 40), 443 "b0110".U -> io.rdcache.resp.bits.data_delayed(63, 48), 444 "b0111".U -> io.rdcache.resp.bits.data_delayed(63, 56), 445 "b1000".U -> io.rdcache.resp.bits.data_delayed(127, 64), 446 "b1001".U -> io.rdcache.resp.bits.data_delayed(127, 72), 447 "b1010".U -> io.rdcache.resp.bits.data_delayed(127, 80), 448 "b1011".U -> io.rdcache.resp.bits.data_delayed(127, 88), 449 "b1100".U -> io.rdcache.resp.bits.data_delayed(127, 96), 450 "b1101".U -> io.rdcache.resp.bits.data_delayed(127, 104), 451 "b1110".U -> io.rdcache.resp.bits.data_delayed(127, 112), 452 "b1111".U -> io.rdcache.resp.bits.data_delayed(127, 120) 453 )) 454 val pickData = rdataVecHelper(alignedType(1,0), cacheData) 455 val mergedData = mergeDataWithElemIdx( 456 oldData = data(splitPtr.value), 457 newData = Seq(pickData), 458 alignedType = alignedType(1,0), 459 elemIdx = Seq(elemIdxInVd), 460 valids = Seq(true.B) 461 ) 462 when(state === s_latch_and_merge_data && segmentActive){ 463 data(splitPtr.value) := mergedData 464 } 465 /** 466 * split data for store 467 * */ 468 val splitData = genVSData( 469 data = data(splitPtr.value), 470 elemIdx = elemIdxInVd, 471 alignedType = alignedType 472 ) 473 val flowData = genVWdata(splitData, alignedType) // TODO: connect vstd, pass vector data 474 val wmask = genVWmask(latchVaddr, alignedType(1, 0)) & Fill(VLENB, segmentActive) 475 476 /** 477 * rdcache req, write request don't need to query dcache, because we write element to sbuffer 478 */ 479 io.rdcache.req := DontCare 480 io.rdcache.req.valid := state === s_cache_req && FuType.isVLoad(fuType) 481 io.rdcache.req.bits.cmd := MemoryOpConstants.M_XRD 482 io.rdcache.req.bits.vaddr := latchVaddr 483 io.rdcache.req.bits.mask := mask 484 io.rdcache.req.bits.data := flowData 485 io.rdcache.pf_source := LOAD_SOURCE.U 486 io.rdcache.req.bits.id := DontCare 487 io.rdcache.resp.ready := true.B 488 io.rdcache.s1_paddr_dup_lsu := instMicroOp.paddr 489 io.rdcache.s1_paddr_dup_dcache := instMicroOp.paddr 490 io.rdcache.s1_kill := false.B 491 io.rdcache.s2_kill := false.B 492 if (env.FPGAPlatform){ 493 io.rdcache.s0_pc := DontCare 494 io.rdcache.s1_pc := DontCare 495 io.rdcache.s2_pc := DontCare 496 }else{ 497 io.rdcache.s0_pc := instMicroOp.uop.pc 498 io.rdcache.s1_pc := instMicroOp.uop.pc 499 io.rdcache.s2_pc := instMicroOp.uop.pc 500 } 501 io.rdcache.replacementUpdated := false.B 502 io.rdcache.is128Req := false.B 503 504 505 /** 506 * write data to sbuffer 507 * */ 508 sbufferOut.bits := DontCare 509 sbufferOut.valid := state === s_send_data && segmentActive 510 sbufferOut.bits.vecValid := state === s_send_data && segmentActive 511 sbufferOut.bits.mask := wmask 512 sbufferOut.bits.data := flowData 513 sbufferOut.bits.vaddr := latchVaddr 514 sbufferOut.bits.cmd := MemoryOpConstants.M_XWR 515 sbufferOut.bits.id := DontCare 516 sbufferOut.bits.addr := instMicroOp.paddr 517 518 NewPipelineConnect( 519 sbufferOut, io.sbuffer, io.sbuffer.fire, 520 false.B, 521 Option(s"VSegmentUnitPipelineConnect") 522 ) 523 524 io.vecDifftestInfo.valid := state === s_send_data && segmentActive 525 io.vecDifftestInfo.bits := uopq(deqPtr.value).uop 526 527 /** 528 * update ptr 529 * */ 530 private val fieldActiveWirteFinish = sbufferOut.fire && segmentActive // writedata finish and is a active segment 531 XSError(sbufferOut.fire && !segmentActive, "Attempt write inactive segment to sbuffer, something wrong!\n") 532 533 private val segmentInactiveFinish = ((state === s_latch_and_merge_data) || (state === s_send_data)) && !segmentActive 534 535 val splitPtrOffset = Mux( 536 isIndexed(instType), 537 Mux(lmul.asSInt < 0.S, 1.U, (1.U << lmul).asUInt), 538 Mux(emul.asSInt < 0.S, 1.U, (1.U << emul).asUInt) 539 ) 540 splitPtrNext := 541 Mux(fieldIdx === maxNfields || !segmentActive, // if segment is active, need to complete this segment, otherwise jump to next segment 542 // segment finish, By shifting 'issueUopFlowNumLog2' to the right to ensure that emul != 1 can correctly generate lateral offset. 543 (deqPtr + ((segmentIdx +& 1.U) >> issueUopFlowNumLog2).asUInt), 544 // next field. 545 (splitPtr + splitPtrOffset) 546 ) 547 548 dontTouch(issueUopFlowNumLog2) 549 dontTouch(issueEmul) 550 dontTouch(splitPtrNext) 551 dontTouch(stridePtr) 552 dontTouch(segmentActive) 553 554 // update splitPtr 555 when(state === s_latch_and_merge_data || (state === s_send_data && (fieldActiveWirteFinish || !segmentActive))){ 556 splitPtr := splitPtrNext 557 }.elsewhen(io.in.fire && !instMicroOpValid){ 558 splitPtr := deqPtr // initial splitPtr 559 } 560 561 // update stridePtr, only use in index 562 val strideOffset = Mux(isIndexed(issueInstType), segmentIdx >> issueMaxIdxInIndexLog2, 0.U) 563 stridePtr := deqPtr + strideOffset 564 565 // update fieldIdx 566 when(io.in.fire && !instMicroOpValid){ // init 567 fieldIdx := 0.U 568 }.elsewhen(state === s_latch_and_merge_data && segmentActive || 569 (state === s_send_data && fieldActiveWirteFinish)){ // only if segment is active 570 571 /* next segment, only if segment complete */ 572 fieldIdx := Mux(fieldIdx === maxNfields, 0.U, fieldIdx + 1.U) 573 }.elsewhen(segmentInactiveFinish){ // segment is inactive, go to next segment 574 fieldIdx := 0.U 575 } 576 //update segmentIdx 577 when(io.in.fire && !instMicroOpValid){ 578 segmentIdx := 0.U 579 }.elsewhen(fieldIdx === maxNfields && (state === s_latch_and_merge_data || (state === s_send_data && fieldActiveWirteFinish)) && 580 segmentIdx =/= maxSegIdx){ // next segment, only if segment is active 581 582 segmentIdx := segmentIdx + 1.U 583 }.elsewhen(segmentInactiveFinish && segmentIdx =/= maxSegIdx){ // if segment is inactive, go to next segment 584 segmentIdx := segmentIdx + 1.U 585 } 586 587 //update segmentOffset 588 /* when segment is active or segment is inactive, increase segmentOffset */ 589 when((fieldIdx === maxNfields && (state === s_latch_and_merge_data || (state === s_send_data && fieldActiveWirteFinish))) || 590 segmentInactiveFinish){ 591 592 segmentOffset := segmentOffset + Mux(isUnitStride(issueInstType), (maxNfields +& 1.U) << issueEew(1, 0), stride(stridePtr.value)) 593 } 594 595 //update deqPtr 596 when(io.uopwriteback.fire){ 597 deqPtr := deqPtr + 1.U 598 } 599 600 /************************************************************************* 601 * dequeue logic 602 *************************************************************************/ 603 val vdIdxInField = GenUopIdxInField(Mux(isIndexed(instType), issueLmul, issueEmul), uopq(deqPtr.value).uop.vpu.vuopIdx) 604 /*select mask of vd, maybe remove in feature*/ 605 val realEw = Mux(isIndexed(issueInstType), issueSew(1, 0), issueEew(1, 0)) 606 val maskDataVec: Vec[UInt] = VecDataToMaskDataVec(instMicroOp.mask, realEw) 607 val maskUsed = maskDataVec(vdIdxInField) 608 609 when(stateNext === s_idle){ 610 instMicroOpValid := false.B 611 } 612 io.uopwriteback.valid := (state === s_finish) && !isEmpty(enqPtr, deqPtr) 613 io.uopwriteback.bits.uop := uopq(deqPtr.value).uop 614 io.uopwriteback.bits.uop.vpu := instMicroOp.uop.vpu 615 io.uopwriteback.bits.uop.exceptionVec := instMicroOp.uop.exceptionVec 616 io.uopwriteback.bits.mask.get := instMicroOp.mask 617 io.uopwriteback.bits.data := data(deqPtr.value) 618 io.uopwriteback.bits.vdIdx.get := vdIdxInField 619 io.uopwriteback.bits.uop.vpu.vl := instMicroOp.vl 620 io.uopwriteback.bits.uop.vpu.vstart := instMicroOp.vstart 621 io.uopwriteback.bits.uop.vpu.vmask := maskUsed 622 io.uopwriteback.bits.uop.vpu.vuopIdx := uopq(deqPtr.value).uop.vpu.vuopIdx 623 io.uopwriteback.bits.debug := DontCare 624 io.uopwriteback.bits.vdIdxInField.get := vdIdxInField 625 io.uopwriteback.bits.uop.robIdx := instMicroOp.uop.robIdx 626 io.uopwriteback.bits.uop.fuOpType := instMicroOp.uop.fuOpType 627 628 //to RS 629 io.feedback.valid := state === s_finish && !isEmpty(enqPtr, deqPtr) 630 io.feedback.bits.hit := true.B 631 io.feedback.bits.robIdx := instMicroOp.uop.robIdx 632 io.feedback.bits.sourceType := DontCare 633 io.feedback.bits.flushState := DontCare 634 io.feedback.bits.dataInvalidSqIdx := DontCare 635 io.feedback.bits.sqIdx := uopq(deqPtr.value).uop.sqIdx 636 io.feedback.bits.lqIdx := uopq(deqPtr.value).uop.lqIdx 637 638 // exception 639 io.exceptionInfo := DontCare 640 io.exceptionInfo.bits.robidx := instMicroOp.uop.robIdx 641 io.exceptionInfo.bits.uopidx := uopq(deqPtr.value).uop.vpu.vuopIdx 642 io.exceptionInfo.bits.vstart := instMicroOp.exceptionVstart 643 io.exceptionInfo.bits.vaddr := instMicroOp.exceptionVaddr 644 io.exceptionInfo.bits.vl := instMicroOp.exceptionVl 645 io.exceptionInfo.valid := (state === s_finish) && instMicroOp.uop.exceptionVec.asUInt.orR && !isEmpty(enqPtr, deqPtr) 646} 647 648