1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.ImmUnion 25import xiangshan.cache._ 26import xiangshan.cache.mmu.{TlbRequestIO, TlbReq, TlbResp, TlbCmd} 27 28// Store Pipeline Stage 0 29// Generate addr, use addr to query DCache and DTLB 30class StoreUnit_S0(implicit p: Parameters) extends XSModule { 31 val io = IO(new Bundle() { 32 val in = Flipped(Decoupled(new ExuInput)) 33 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 34 val isFirstIssue = Input(Bool()) 35 val out = Decoupled(new LsPipelineBundle) 36 val dtlbReq = DecoupledIO(new TlbReq) 37 }) 38 39 // send req to dtlb 40 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 41 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 42 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 43 val saddr_hi = Mux(saddr_lo(12), 44 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 45 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 46 ) 47 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 48 49 io.dtlbReq.bits.vaddr := saddr 50 io.dtlbReq.valid := io.in.valid 51 io.dtlbReq.bits.cmd := TlbCmd.write 52 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 53 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 54 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 55 56 io.out.bits := DontCare 57 io.out.bits.vaddr := saddr 58 59 // Now data use its own io 60 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 61 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 62 io.out.bits.uop := io.in.bits.uop 63 io.out.bits.miss := DontCare 64 io.out.bits.rsIdx := io.rsIdx 65 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 66 io.out.valid := io.in.valid 67 io.in.ready := io.out.ready 68 69 // exception check 70 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 71 "b00".U -> true.B, //b 72 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 73 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 74 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 75 )) 76 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 77 78 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 79 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 80 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 81 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 82} 83 84// Load Pipeline Stage 1 85// TLB resp (send paddr to dcache) 86class StoreUnit_S1(implicit p: Parameters) extends XSModule { 87 val io = IO(new Bundle() { 88 val in = Flipped(Decoupled(new LsPipelineBundle)) 89 val out = Decoupled(new LsPipelineBundle) 90 val lsq = ValidIO(new LsPipelineBundle) 91 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 92 val rsFeedback = ValidIO(new RSFeedback) 93 }) 94 95 val s1_paddr = io.dtlbResp.bits.paddr 96 val s1_tlb_miss = io.dtlbResp.bits.miss 97 val s1_mmio = io.dtlbResp.bits.mmio 98 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 99 100 io.in.ready := true.B 101 102 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 103 104 // Send TLB feedback to store issue queue 105 io.rsFeedback.valid := io.in.valid 106 io.rsFeedback.bits.hit := !s1_tlb_miss 107 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 108 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 109 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 110 XSDebug(io.rsFeedback.valid, 111 "S1 Store: tlbHit: %d roqIdx: %d\n", 112 io.rsFeedback.bits.hit, 113 io.rsFeedback.bits.rsIdx 114 ) 115 116 117 // get paddr from dtlb, check if rollback is needed 118 // writeback store inst to lsq 119 io.lsq.valid := io.in.valid && !s1_tlb_miss 120 io.lsq.bits := io.in.bits 121 io.lsq.bits.paddr := s1_paddr 122 io.lsq.bits.miss := false.B 123 io.lsq.bits.mmio := s1_mmio && !s1_exception 124 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 125 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 126 127 // mmio inst with exception will be writebacked immediately 128 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 129 io.out.bits := io.lsq.bits 130} 131 132class StoreUnit_S2(implicit p: Parameters) extends XSModule { 133 val io = IO(new Bundle() { 134 val in = Flipped(Decoupled(new LsPipelineBundle)) 135 val out = Decoupled(new LsPipelineBundle) 136 }) 137 138 io.in.ready := true.B 139 io.out.bits := io.in.bits 140 io.out.valid := io.in.valid 141 142} 143 144class StoreUnit_S3(implicit p: Parameters) extends XSModule { 145 val io = IO(new Bundle() { 146 val in = Flipped(Decoupled(new LsPipelineBundle)) 147 val stout = DecoupledIO(new ExuOutput) // writeback store 148 }) 149 150 io.in.ready := true.B 151 152 io.stout.valid := io.in.valid 153 io.stout.bits.uop := io.in.bits.uop 154 io.stout.bits.data := DontCare 155 io.stout.bits.redirectValid := false.B 156 io.stout.bits.redirect := DontCare 157 io.stout.bits.debug.isMMIO := io.in.bits.mmio 158 io.stout.bits.debug.paddr := DontCare 159 io.stout.bits.debug.isPerfCnt := false.B 160 io.stout.bits.fflags := DontCare 161 162} 163 164class StoreUnit(implicit p: Parameters) extends XSModule { 165 val io = IO(new Bundle() { 166 val stin = Flipped(Decoupled(new ExuInput)) 167 val redirect = Flipped(ValidIO(new Redirect)) 168 val flush = Input(Bool()) 169 val rsFeedback = ValidIO(new RSFeedback) 170 val dtlb = new TlbRequestIO() 171 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 172 val isFirstIssue = Input(Bool()) 173 val lsq = ValidIO(new LsPipelineBundle) 174 val stout = DecoupledIO(new ExuOutput) // writeback store 175 }) 176 177 val store_s0 = Module(new StoreUnit_S0) 178 val store_s1 = Module(new StoreUnit_S1) 179 val store_s2 = Module(new StoreUnit_S2) 180 val store_s3 = Module(new StoreUnit_S3) 181 182 store_s0.io.in <> io.stin 183 store_s0.io.dtlbReq <> io.dtlb.req 184 store_s0.io.rsIdx := io.rsIdx 185 store_s0.io.isFirstIssue := io.isFirstIssue 186 187 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 188 189 store_s1.io.lsq <> io.lsq // send result to sq 190 store_s1.io.dtlbResp <> io.dtlb.resp 191 store_s1.io.rsFeedback <> io.rsFeedback 192 193 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 194 195 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 196 197 store_s3.io.stout <> io.stout 198 199 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 200 XSDebug(cond, 201 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 202 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 203 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 204 p"data ${Hexadecimal(pipeline.data)} " + 205 p"mask ${Hexadecimal(pipeline.mask)}\n" 206 ) 207 } 208 209 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 210 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 211 212} 213