1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8 9// Store Pipeline Stage 0 10// Generate addr, use addr to query DCache and DTLB 11class StoreUnit_S0 extends XSModule { 12 val io = IO(new Bundle() { 13 val in = Flipped(Decoupled(new ExuInput)) 14 val out = Decoupled(new LsPipelineBundle) 15 val redirect = Flipped(ValidIO(new Redirect)) 16 val dtlbReq = DecoupledIO(new TlbReq) 17 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 18 val tlbFeedback = ValidIO(new TlbFeedback) 19 }) 20 21 // send req to dtlb 22 val saddr = io.in.bits.src1 + io.in.bits.uop.ctrl.imm 23 24 io.dtlbReq.bits.vaddr := saddr 25 io.dtlbReq.valid := io.in.valid 26 io.dtlbReq.bits.cmd := TlbCmd.write 27 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 28 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 29 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 30 31 io.out.bits := DontCare 32 io.out.bits.vaddr := saddr 33 io.out.bits.paddr := io.dtlbResp.bits.paddr 34 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 35 io.out.bits.uop := io.in.bits.uop 36 io.out.bits.miss := io.dtlbResp.bits.miss 37 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 38 io.out.valid := io.in.valid && !io.dtlbResp.bits.miss && !io.out.bits.uop.roqIdx.needFlush(io.redirect) 39 io.in.ready := io.out.ready 40 41 // exception check 42 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 43 "b00".U -> true.B, //b 44 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 45 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 46 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 47 )) 48 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 49 io.out.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 50 51 // Send TLB feedback to store issue queue 52 // TODO: should be moved to S1 53 io.tlbFeedback.valid := RegNext(io.in.valid && io.out.ready) 54 io.tlbFeedback.bits.hit := RegNext(!io.out.bits.miss) 55 io.tlbFeedback.bits.roqIdx := RegNext(io.out.bits.uop.roqIdx) 56 XSDebug(io.tlbFeedback.valid, 57 "S1 Store: tlbHit: %d roqIdx: %d\n", 58 io.tlbFeedback.bits.hit, 59 io.tlbFeedback.bits.roqIdx.asUInt 60 ) 61} 62 63// Load Pipeline Stage 1 64// TLB resp (send paddr to dcache) 65class StoreUnit_S1 extends XSModule { 66 val io = IO(new Bundle() { 67 val in = Flipped(Decoupled(new LsPipelineBundle)) 68 val out = Decoupled(new LsPipelineBundle) 69 // val fp_out = Decoupled(new LsPipelineBundle) 70 val redirect = Flipped(ValidIO(new Redirect)) 71 }) 72 73 // get paddr from dtlb, check if rollback is needed 74 // writeback store inst to lsq 75 // writeback to LSQ 76 io.in.ready := true.B 77 io.out.bits := io.in.bits 78 io.out.bits.miss := false.B 79 io.out.bits.mmio := AddressSpace.isMMIO(io.in.bits.paddr) 80 io.out.valid := io.in.fire() // TODO: && ! FP 81 82 // if fp 83 // io.fp_out.valid := ... 84 // io.fp_out.bits := ... 85 86} 87 88// class StoreUnit_S2 extends XSModule { 89// val io = IO(new Bundle() { 90// val in = Flipped(Decoupled(new LsPipelineBundle)) 91// val out = Decoupled(new LsPipelineBundle) 92// val redirect = Flipped(ValidIO(new Redirect)) 93// }) 94 95// io.in.ready := true.B 96// io.out.bits := io.in.bits 97// io.out.valid := io.in.valid && !io.out.bits.uop.roqIdx.needFlush(io.redirect) 98// } 99 100class StoreUnit extends XSModule { 101 val io = IO(new Bundle() { 102 val stin = Flipped(Decoupled(new ExuInput)) 103 val redirect = Flipped(ValidIO(new Redirect)) 104 val tlbFeedback = ValidIO(new TlbFeedback) 105 val dtlb = new TlbRequestIO() 106 val lsq = ValidIO(new LsPipelineBundle) 107 }) 108 109 val store_s0 = Module(new StoreUnit_S0) 110 val store_s1 = Module(new StoreUnit_S1) 111 // val store_s2 = Module(new StoreUnit_S2) 112 113 store_s0.io.in <> io.stin 114 store_s0.io.redirect <> io.redirect 115 store_s0.io.dtlbReq <> io.dtlb.req 116 store_s0.io.dtlbResp <> io.dtlb.resp 117 store_s0.io.tlbFeedback <> io.tlbFeedback 118 119 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, false.B) 120 // PipelineConnect(store_s1.io.fp_out, store_s2.io.in, true.B, false.B) 121 122 store_s1.io.redirect <> io.redirect 123 // send result to sq 124 io.lsq.valid := store_s1.io.out.valid 125 io.lsq.bits := store_s1.io.out.bits 126 127 store_s1.io.out.ready := true.B 128 129 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 130 XSDebug(cond, 131 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 132 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 133 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 134 p"data ${Hexadecimal(pipeline.data)} " + 135 p"mask ${Hexadecimal(pipeline.mask)}\n" 136 ) 137 } 138 139 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 140 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 141 142}