1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8 9// Store Pipeline Stage 0 10// Generate addr, use addr to query DCache and DTLB 11class StoreUnit_S0 extends XSModule { 12 val io = IO(new Bundle() { 13 val in = Flipped(Decoupled(new ExuInput)) 14 val out = Decoupled(new LsPipelineBundle) 15 val dtlbReq = DecoupledIO(new TlbReq) 16 }) 17 18 // send req to dtlb 19 val saddr = io.in.bits.src1 + io.in.bits.uop.ctrl.imm 20 21 io.dtlbReq.bits.vaddr := saddr 22 io.dtlbReq.valid := io.in.valid 23 io.dtlbReq.bits.cmd := TlbCmd.write 24 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 25 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 26 27 io.out.bits := DontCare 28 io.out.bits.vaddr := saddr 29 30 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 31 io.out.bits.uop := io.in.bits.uop 32 io.out.bits.miss := DontCare 33 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 34 io.out.valid := io.in.valid 35 io.in.ready := io.out.ready 36 37 // exception check 38 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 39 "b00".U -> true.B, //b 40 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 41 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 42 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 43 )) 44 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 45 46} 47 48// Load Pipeline Stage 1 49// TLB resp (send paddr to dcache) 50class StoreUnit_S1 extends XSModule { 51 val io = IO(new Bundle() { 52 val in = Flipped(Decoupled(new LsPipelineBundle)) 53 val out = Decoupled(new LsPipelineBundle) 54 // val fp_out = Decoupled(new LsPipelineBundle) 55 val lsq = ValidIO(new LsPipelineBundle) 56 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 57 val tlbFeedback = ValidIO(new TlbFeedback) 58 }) 59 60 val s1_paddr = io.dtlbResp.bits.paddr 61 val s1_tlb_miss = io.dtlbResp.bits.miss 62 63 io.in.ready := true.B 64 65 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 66 67 // Send TLB feedback to store issue queue 68 io.tlbFeedback.valid := io.in.valid 69 io.tlbFeedback.bits.hit := !s1_tlb_miss 70 io.tlbFeedback.bits.roqIdx := io.in.bits.uop.roqIdx 71 XSDebug(io.tlbFeedback.valid, 72 "S1 Store: tlbHit: %d roqIdx: %d\n", 73 io.tlbFeedback.bits.hit, 74 io.tlbFeedback.bits.roqIdx.asUInt 75 ) 76 77 // get paddr from dtlb, check if rollback is needed 78 // writeback store inst to lsq 79 io.lsq.valid := io.in.valid && !s1_tlb_miss// TODO: && ! FP 80 io.lsq.bits := io.in.bits 81 io.lsq.bits.paddr := s1_paddr 82 io.lsq.bits.miss := false.B 83 io.lsq.bits.mmio := AddressSpace.isMMIO(s1_paddr) 84 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 85 86 // mmio inst with exception will be writebacked immediately 87 val hasException = io.out.bits.uop.cf.exceptionVec.asUInt.orR 88 io.out.valid := io.in.valid && (!io.out.bits.mmio || hasException) && !s1_tlb_miss 89 io.out.bits := io.lsq.bits 90 91 // if fp 92 // io.fp_out.valid := ... 93 // io.fp_out.bits := ... 94 95} 96 97class StoreUnit_S2 extends XSModule { 98 val io = IO(new Bundle() { 99 val in = Flipped(Decoupled(new LsPipelineBundle)) 100 val stout = DecoupledIO(new ExuOutput) // writeback store 101 }) 102 103 io.in.ready := true.B 104 105 io.stout.valid := io.in.valid 106 io.stout.bits.uop := io.in.bits.uop 107 io.stout.bits.data := DontCare 108 io.stout.bits.redirectValid := false.B 109 io.stout.bits.redirect := DontCare 110 io.stout.bits.brUpdate := DontCare 111 io.stout.bits.debug.isMMIO := io.in.bits.mmio 112 io.stout.bits.fflags := DontCare 113 114} 115 116class StoreUnit extends XSModule { 117 val io = IO(new Bundle() { 118 val stin = Flipped(Decoupled(new ExuInput)) 119 val redirect = Flipped(ValidIO(new Redirect)) 120 val tlbFeedback = ValidIO(new TlbFeedback) 121 val dtlb = new TlbRequestIO() 122 val lsq = ValidIO(new LsPipelineBundle) 123 val stout = DecoupledIO(new ExuOutput) // writeback store 124 }) 125 126 val store_s0 = Module(new StoreUnit_S0) 127 val store_s1 = Module(new StoreUnit_S1) 128 val store_s2 = Module(new StoreUnit_S2) 129 130 store_s0.io.in <> io.stin 131 store_s0.io.dtlbReq <> io.dtlb.req 132 133 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 134 135 store_s1.io.lsq <> io.lsq // send result to sq 136 store_s1.io.dtlbResp <> io.dtlb.resp 137 store_s1.io.tlbFeedback <> io.tlbFeedback 138 139 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 140 141 store_s2.io.stout <> io.stout 142 143 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 144 XSDebug(cond, 145 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 146 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 147 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 148 p"data ${Hexadecimal(pipeline.data)} " + 149 p"mask ${Hexadecimal(pipeline.mask)}\n" 150 ) 151 } 152 153 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 154 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 155 156} 157