1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9 10// Store Pipeline Stage 0 11// Generate addr, use addr to query DCache and DTLB 12class StoreUnit_S0 extends XSModule { 13 val io = IO(new Bundle() { 14 val in = Flipped(Decoupled(new ExuInput)) 15 val out = Decoupled(new LsPipelineBundle) 16 val dtlbReq = DecoupledIO(new TlbReq) 17 }) 18 19 // send req to dtlb 20 val saddr = io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN) 21 22 io.dtlbReq.bits.vaddr := saddr 23 io.dtlbReq.valid := io.in.valid 24 io.dtlbReq.bits.cmd := TlbCmd.write 25 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 26 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 27 28 io.out.bits := DontCare 29 io.out.bits.vaddr := saddr 30 31 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 32 when(io.in.bits.uop.ctrl.src2Type === SrcType.fp){ 33 io.out.bits.data := io.in.bits.src2 34 } // not not touch fp store raw data 35 io.out.bits.uop := io.in.bits.uop 36 io.out.bits.miss := DontCare 37 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 38 io.out.valid := io.in.valid 39 io.in.ready := io.out.ready 40 41 // exception check 42 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 43 "b00".U -> true.B, //b 44 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 45 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 46 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 47 )) 48 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 49 50} 51 52// Load Pipeline Stage 1 53// TLB resp (send paddr to dcache) 54class StoreUnit_S1 extends XSModule { 55 val io = IO(new Bundle() { 56 val in = Flipped(Decoupled(new LsPipelineBundle)) 57 val out = Decoupled(new LsPipelineBundle) 58 // val fp_out = Decoupled(new LsPipelineBundle) 59 val lsq = ValidIO(new LsPipelineBundle) 60 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 61 val tlbFeedback = ValidIO(new TlbFeedback) 62 }) 63 64 val s1_paddr = io.dtlbResp.bits.paddr 65 val s1_tlb_miss = io.dtlbResp.bits.miss 66 67 io.in.ready := true.B 68 69 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 70 71 // Send TLB feedback to store issue queue 72 io.tlbFeedback.valid := io.in.valid 73 io.tlbFeedback.bits.hit := !s1_tlb_miss 74 io.tlbFeedback.bits.roqIdx := io.in.bits.uop.roqIdx 75 XSDebug(io.tlbFeedback.valid, 76 "S1 Store: tlbHit: %d roqIdx: %d\n", 77 io.tlbFeedback.bits.hit, 78 io.tlbFeedback.bits.roqIdx.asUInt 79 ) 80 81 82 // get paddr from dtlb, check if rollback is needed 83 // writeback store inst to lsq 84 io.lsq.valid := io.in.valid && !s1_tlb_miss// TODO: && ! FP 85 io.lsq.bits := io.in.bits 86 io.lsq.bits.paddr := s1_paddr 87 io.lsq.bits.miss := false.B 88 io.lsq.bits.mmio := io.dtlbResp.bits.mmio 89 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 90 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 91 92 // mmio inst with exception will be writebacked immediately 93 val hasException = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 94 io.out.valid := io.in.valid && (!io.out.bits.mmio || hasException) && !s1_tlb_miss 95 io.out.bits := io.lsq.bits 96 97 // encode data for fp store 98 when(io.in.bits.uop.ctrl.src2Type === SrcType.fp){ 99 io.lsq.bits.data := genWdata(ieee(io.in.bits.data), io.in.bits.uop.ctrl.fuOpType(1,0)) 100 } 101 102} 103 104class StoreUnit_S2 extends XSModule { 105 val io = IO(new Bundle() { 106 val in = Flipped(Decoupled(new LsPipelineBundle)) 107 val out = Decoupled(new LsPipelineBundle) 108 }) 109 110 io.in.ready := true.B 111 io.out.bits := io.in.bits 112 io.out.valid := io.in.valid 113 114} 115 116class StoreUnit_S3 extends XSModule { 117 val io = IO(new Bundle() { 118 val in = Flipped(Decoupled(new LsPipelineBundle)) 119 val stout = DecoupledIO(new ExuOutput) // writeback store 120 }) 121 122 io.in.ready := true.B 123 124 io.stout.valid := io.in.valid 125 io.stout.bits.uop := io.in.bits.uop 126 io.stout.bits.data := DontCare 127 io.stout.bits.redirectValid := false.B 128 io.stout.bits.redirect := DontCare 129 io.stout.bits.brUpdate := DontCare 130 io.stout.bits.debug.isMMIO := io.in.bits.mmio 131 io.stout.bits.debug.isPerfCnt := false.B 132 io.stout.bits.fflags := DontCare 133 134} 135 136class StoreUnit extends XSModule { 137 val io = IO(new Bundle() { 138 val stin = Flipped(Decoupled(new ExuInput)) 139 val redirect = Flipped(ValidIO(new Redirect)) 140 val tlbFeedback = ValidIO(new TlbFeedback) 141 val dtlb = new TlbRequestIO() 142 val lsq = ValidIO(new LsPipelineBundle) 143 val stout = DecoupledIO(new ExuOutput) // writeback store 144 }) 145 146 val store_s0 = Module(new StoreUnit_S0) 147 val store_s1 = Module(new StoreUnit_S1) 148 val store_s2 = Module(new StoreUnit_S2) 149 val store_s3 = Module(new StoreUnit_S3) 150 151 store_s0.io.in <> io.stin 152 store_s0.io.dtlbReq <> io.dtlb.req 153 154 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 155 156 store_s1.io.lsq <> io.lsq // send result to sq 157 store_s1.io.dtlbResp <> io.dtlb.resp 158 store_s1.io.tlbFeedback <> io.tlbFeedback 159 160 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 161 162 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 163 164 store_s3.io.stout <> io.stout 165 166 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 167 XSDebug(cond, 168 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 169 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 170 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 171 p"data ${Hexadecimal(pipeline.data)} " + 172 p"mask ${Hexadecimal(pipeline.mask)}\n" 173 ) 174 } 175 176 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 177 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 178 179} 180