1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 9import xiangshan.backend.LSUOpType 10 11class LoadToLsqIO extends XSBundle { 12 val loadIn = ValidIO(new LsPipelineBundle) 13 val ldout = Flipped(DecoupledIO(new ExuOutput)) 14 val forward = new LoadForwardQueryIO 15} 16 17// Load Pipeline Stage 0 18// Generate addr, use addr to query DCache and DTLB 19class LoadUnit_S0 extends XSModule { 20 val io = IO(new Bundle() { 21 val in = Flipped(Decoupled(new ExuInput)) 22 val out = Decoupled(new LsPipelineBundle) 23 val dtlbReq = DecoupledIO(new TlbReq) 24 val dcacheReq = DecoupledIO(new DCacheWordReq) 25 }) 26 27 val s0_uop = io.in.bits.uop 28 val s0_vaddr = io.in.bits.src1 + s0_uop.ctrl.imm 29 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 30 31 // query DTLB 32 io.dtlbReq.valid := io.in.valid 33 io.dtlbReq.bits.vaddr := s0_vaddr 34 io.dtlbReq.bits.cmd := TlbCmd.read 35 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 36 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 37 38 // query DCache 39 io.dcacheReq.valid := io.in.valid 40 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 41 io.dcacheReq.bits.addr := s0_vaddr 42 io.dcacheReq.bits.mask := s0_mask 43 io.dcacheReq.bits.data := DontCare 44 45 // TODO: update cache meta 46 io.dcacheReq.bits.meta.id := DontCare 47 io.dcacheReq.bits.meta.vaddr := s0_vaddr 48 io.dcacheReq.bits.meta.paddr := DontCare 49 io.dcacheReq.bits.meta.uop := s0_uop 50 io.dcacheReq.bits.meta.mmio := false.B 51 io.dcacheReq.bits.meta.tlb_miss := false.B 52 io.dcacheReq.bits.meta.mask := s0_mask 53 io.dcacheReq.bits.meta.replay := false.B 54 55 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 56 "b00".U -> true.B, //b 57 "b01".U -> (s0_vaddr(0) === 0.U), //h 58 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 59 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 60 )) 61 62 io.out.valid := io.in.valid && io.dcacheReq.ready 63 64 io.out.bits := DontCare 65 io.out.bits.vaddr := s0_vaddr 66 io.out.bits.mask := s0_mask 67 io.out.bits.uop := s0_uop 68 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 69 70 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 71 72 XSDebug(io.dcacheReq.fire(), 73 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 74 ) 75} 76 77 78// Load Pipeline Stage 1 79// TLB resp (send paddr to dcache) 80class LoadUnit_S1 extends XSModule { 81 val io = IO(new Bundle() { 82 val in = Flipped(Decoupled(new LsPipelineBundle)) 83 val out = Decoupled(new LsPipelineBundle) 84 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 85 val dcachePAddr = Output(UInt(PAddrBits.W)) 86 val dcacheKill = Output(Bool()) 87 val sbuffer = new LoadForwardQueryIO 88 val lsq = new LoadForwardQueryIO 89 }) 90 91 val s1_uop = io.in.bits.uop 92 val s1_paddr = io.dtlbResp.bits.paddr 93 val s1_exception = io.out.bits.uop.cf.exceptionVec.asUInt.orR 94 val s1_tlb_miss = io.dtlbResp.bits.miss 95 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) 96 val s1_mask = io.in.bits.mask 97 98 io.out.bits := io.in.bits // forwardXX field will be updated in s1 99 100 io.dtlbResp.ready := true.B 101 102 // TOOD: PMA check 103 io.dcachePAddr := s1_paddr 104 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 105 106 // load forward query datapath 107 io.sbuffer.valid := io.in.valid 108 io.sbuffer.paddr := s1_paddr 109 io.sbuffer.uop := s1_uop 110 io.sbuffer.sqIdx := s1_uop.sqIdx 111 io.sbuffer.mask := s1_mask 112 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 113 114 io.lsq.valid := io.in.valid 115 io.lsq.paddr := s1_paddr 116 io.lsq.uop := s1_uop 117 io.lsq.sqIdx := s1_uop.sqIdx 118 io.lsq.mask := s1_mask 119 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 120 121 io.out.valid := io.in.valid// && !s1_tlb_miss 122 io.out.bits.paddr := s1_paddr 123 io.out.bits.mmio := s1_mmio && !s1_exception 124 io.out.bits.tlbMiss := s1_tlb_miss 125 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 126 127 io.in.ready := !io.in.valid || io.out.ready 128 129} 130 131 132// Load Pipeline Stage 2 133// DCache resp 134class LoadUnit_S2 extends XSModule with HasLoadHelper { 135 val io = IO(new Bundle() { 136 val in = Flipped(Decoupled(new LsPipelineBundle)) 137 val out = Decoupled(new LsPipelineBundle) 138 val tlbFeedback = ValidIO(new TlbFeedback) 139 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 140 val lsq = new LoadForwardQueryIO 141 val sbuffer = new LoadForwardQueryIO 142 }) 143 144 val s2_uop = io.in.bits.uop 145 val s2_mask = io.in.bits.mask 146 val s2_paddr = io.in.bits.paddr 147 val s2_tlb_miss = io.in.bits.tlbMiss 148 val s2_mmio = io.in.bits.mmio 149 val s2_exception = io.in.bits.uop.cf.exceptionVec.asUInt.orR 150 val s2_cache_miss = io.dcacheResp.bits.miss 151 val s2_cache_replay = io.dcacheResp.bits.replay 152 153 io.dcacheResp.ready := true.B 154 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 155 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 156 157 // feedback tlb result to RS 158 io.tlbFeedback.valid := io.in.valid 159 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 160 io.tlbFeedback.bits.roqIdx := s2_uop.roqIdx 161 162 val forwardMask = io.out.bits.forwardMask 163 val forwardData = io.out.bits.forwardData 164 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 165 166 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 167 s2_uop.cf.pc, 168 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 169 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 170 ) 171 172 // data merge 173 val rdata = VecInit((0 until XLEN / 8).map(j => 174 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 175 val rdataSel = LookupTree(s2_paddr(2, 0), List( 176 "b000".U -> rdata(63, 0), 177 "b001".U -> rdata(63, 8), 178 "b010".U -> rdata(63, 16), 179 "b011".U -> rdata(63, 24), 180 "b100".U -> rdata(63, 32), 181 "b101".U -> rdata(63, 40), 182 "b110".U -> rdata(63, 48), 183 "b111".U -> rdata(63, 56) 184 )) 185 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 186 187 // TODO: ECC check 188 189 io.out.valid := io.in.valid && !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 190 // Inst will be canceled in store queue / lsq, 191 // so we do not need to care about flush in load / store unit's out.valid 192 io.out.bits := io.in.bits 193 io.out.bits.data := rdataPartialLoad 194 io.out.bits.miss := s2_cache_miss && !fullForward 195 io.out.bits.mmio := s2_mmio 196 197 io.in.ready := io.out.ready || !io.in.valid 198 199 // merge forward result 200 // lsq has higher priority than sbuffer 201 io.lsq := DontCare 202 io.sbuffer := DontCare 203 // generate XLEN/8 Muxs 204 for (i <- 0 until XLEN / 8) { 205 when (io.sbuffer.forwardMask(i)) { 206 io.out.bits.forwardMask(i) := true.B 207 io.out.bits.forwardData(i) := io.sbuffer.forwardData(i) 208 } 209 when (io.lsq.forwardMask(i)) { 210 io.out.bits.forwardMask(i) := true.B 211 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 212 } 213 } 214 215 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 216 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 217 io.out.bits.forwardData.asUInt, io.out.bits.forwardMask.asUInt 218 ) 219} 220 221class LoadUnit extends XSModule with HasLoadHelper { 222 val io = IO(new Bundle() { 223 val ldin = Flipped(Decoupled(new ExuInput)) 224 val ldout = Decoupled(new ExuOutput) 225 val fpout = Decoupled(new ExuOutput) 226 val redirect = Flipped(ValidIO(new Redirect)) 227 val tlbFeedback = ValidIO(new TlbFeedback) 228 val dcache = new DCacheLoadIO 229 val dtlb = new TlbRequestIO() 230 val sbuffer = new LoadForwardQueryIO 231 val lsq = new LoadToLsqIO 232 }) 233 234 val load_s0 = Module(new LoadUnit_S0) 235 val load_s1 = Module(new LoadUnit_S1) 236 val load_s2 = Module(new LoadUnit_S2) 237 238 load_s0.io.in <> io.ldin 239 load_s0.io.dtlbReq <> io.dtlb.req 240 load_s0.io.dcacheReq <> io.dcache.req 241 242 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 243 244 load_s1.io.dtlbResp <> io.dtlb.resp 245 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 246 io.dcache.s1_kill <> load_s1.io.dcacheKill 247 load_s1.io.sbuffer <> io.sbuffer 248 load_s1.io.lsq <> io.lsq.forward 249 250 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 251 252 load_s2.io.tlbFeedback <> io.tlbFeedback 253 load_s2.io.dcacheResp <> io.dcache.resp 254 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 255 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 256 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 257 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 258 259 XSDebug(load_s0.io.out.valid, 260 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 261 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 262 XSDebug(load_s1.io.out.valid, 263 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 264 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 265 266 // writeback to LSQ 267 // Current dcache use MSHR 268 // Load queue will be updated at s2 for both hit/miss int/fp load 269 io.lsq.loadIn.valid := load_s2.io.out.valid 270 io.lsq.loadIn.bits := load_s2.io.out.bits 271 val s2Valid = load_s2.io.out.valid && (!load_s2.io.out.bits.miss || load_s2.io.out.bits.uop.cf.exceptionVec.asUInt.orR) 272 val refillFpLoad = io.lsq.ldout.bits.uop.ctrl.fpWen 273 274 // Int load, if hit, will be writebacked at s2 275 val intHitLoadOut = Wire(Valid(new ExuOutput)) 276 intHitLoadOut.valid := s2Valid && !load_s2.io.out.bits.uop.ctrl.fpWen 277 intHitLoadOut.bits.uop := load_s2.io.out.bits.uop 278 intHitLoadOut.bits.data := load_s2.io.out.bits.data 279 intHitLoadOut.bits.redirectValid := false.B 280 intHitLoadOut.bits.redirect := DontCare 281 intHitLoadOut.bits.brUpdate := DontCare 282 intHitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 283 intHitLoadOut.bits.fflags := DontCare 284 285 load_s2.io.out.ready := true.B 286 287 io.ldout.bits := Mux(intHitLoadOut.valid, intHitLoadOut.bits, io.lsq.ldout.bits) 288 io.ldout.valid := intHitLoadOut.valid || io.lsq.ldout.valid && !refillFpLoad 289 290 // Fp load, if hit, will be send to recoder at s2, then it will be recoded & writebacked at s3 291 val fpHitLoadOut = Wire(Valid(new ExuOutput)) 292 fpHitLoadOut.valid := s2Valid && load_s2.io.out.bits.uop.ctrl.fpWen 293 fpHitLoadOut.bits := intHitLoadOut.bits 294 295 val fpLoadOut = Wire(Valid(new ExuOutput)) 296 fpLoadOut.bits := Mux(fpHitLoadOut.valid, fpHitLoadOut.bits, io.lsq.ldout.bits) 297 fpLoadOut.valid := fpHitLoadOut.valid || io.lsq.ldout.valid && refillFpLoad 298 299 val fpLoadOutReg = RegNext(fpLoadOut) 300 io.fpout.bits := fpLoadOutReg.bits 301 io.fpout.bits.data := fpRdataHelper(fpLoadOutReg.bits.uop, fpLoadOutReg.bits.data) // recode 302 io.fpout.valid := RegNext(fpLoadOut.valid && !load_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 303 304 io.lsq.ldout.ready := Mux(refillFpLoad, !fpHitLoadOut.valid, !intHitLoadOut.valid) 305 306 when(io.ldout.fire()){ 307 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 308 } 309 310 when(io.fpout.fire()){ 311 XSDebug("fpout %x\n", io.fpout.bits.uop.cf.pc) 312 } 313} 314