1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 10import xiangshan.backend.LSUOpType 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val forward = new LoadForwardQueryIO 16} 17 18// Load Pipeline Stage 0 19// Generate addr, use addr to query DCache and DTLB 20class LoadUnit_S0 extends XSModule { 21 val io = IO(new Bundle() { 22 val in = Flipped(Decoupled(new ExuInput)) 23 val out = Decoupled(new LsPipelineBundle) 24 val dtlbReq = DecoupledIO(new TlbReq) 25 val dcacheReq = DecoupledIO(new DCacheWordReq) 26 }) 27 28 val s0_uop = io.in.bits.uop 29 val s0_vaddr = io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN) 30 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 31 32 // query DTLB 33 io.dtlbReq.valid := io.in.valid 34 io.dtlbReq.bits.vaddr := s0_vaddr 35 io.dtlbReq.bits.cmd := TlbCmd.read 36 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 37 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 38 39 // query DCache 40 io.dcacheReq.valid := io.in.valid 41 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 42 io.dcacheReq.bits.addr := s0_vaddr 43 io.dcacheReq.bits.mask := s0_mask 44 io.dcacheReq.bits.data := DontCare 45 46 // TODO: update cache meta 47 io.dcacheReq.bits.id := DontCare 48 49 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 50 "b00".U -> true.B, //b 51 "b01".U -> (s0_vaddr(0) === 0.U), //h 52 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 53 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 54 )) 55 56 io.out.valid := io.in.valid && io.dcacheReq.ready 57 58 io.out.bits := DontCare 59 io.out.bits.vaddr := s0_vaddr 60 io.out.bits.mask := s0_mask 61 io.out.bits.uop := s0_uop 62 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 63 64 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 65 66 XSDebug(io.dcacheReq.fire(), 67 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 68 ) 69} 70 71 72// Load Pipeline Stage 1 73// TLB resp (send paddr to dcache) 74class LoadUnit_S1 extends XSModule { 75 val io = IO(new Bundle() { 76 val in = Flipped(Decoupled(new LsPipelineBundle)) 77 val out = Decoupled(new LsPipelineBundle) 78 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 79 val dcachePAddr = Output(UInt(PAddrBits.W)) 80 val dcacheKill = Output(Bool()) 81 val sbuffer = new LoadForwardQueryIO 82 val lsq = new LoadForwardQueryIO 83 }) 84 85 val s1_uop = io.in.bits.uop 86 val s1_paddr = io.dtlbResp.bits.paddr 87 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 88 val s1_tlb_miss = io.dtlbResp.bits.miss 89 val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 90 val s1_mask = io.in.bits.mask 91 92 io.out.bits := io.in.bits // forwardXX field will be updated in s1 93 94 io.dtlbResp.ready := true.B 95 96 // TOOD: PMA check 97 io.dcachePAddr := s1_paddr 98 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 99 100 // load forward query datapath 101 io.sbuffer.valid := io.in.valid 102 io.sbuffer.paddr := s1_paddr 103 io.sbuffer.uop := s1_uop 104 io.sbuffer.sqIdx := s1_uop.sqIdx 105 io.sbuffer.mask := s1_mask 106 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 107 108 io.lsq.valid := io.in.valid 109 io.lsq.paddr := s1_paddr 110 io.lsq.uop := s1_uop 111 io.lsq.sqIdx := s1_uop.sqIdx 112 io.lsq.mask := s1_mask 113 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 114 115 io.out.valid := io.in.valid// && !s1_tlb_miss 116 io.out.bits.paddr := s1_paddr 117 io.out.bits.mmio := s1_mmio && !s1_exception 118 io.out.bits.tlbMiss := s1_tlb_miss 119 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 120 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 121 122 io.in.ready := !io.in.valid || io.out.ready 123 124} 125 126 127// Load Pipeline Stage 2 128// DCache resp 129class LoadUnit_S2 extends XSModule with HasLoadHelper { 130 val io = IO(new Bundle() { 131 val in = Flipped(Decoupled(new LsPipelineBundle)) 132 val out = Decoupled(new LsPipelineBundle) 133 val tlbFeedback = ValidIO(new TlbFeedback) 134 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 135 val lsq = new LoadForwardQueryIO 136 val sbuffer = new LoadForwardQueryIO 137 }) 138 139 val s2_uop = io.in.bits.uop 140 val s2_mask = io.in.bits.mask 141 val s2_paddr = io.in.bits.paddr 142 val s2_tlb_miss = io.in.bits.tlbMiss 143 val s2_mmio = io.in.bits.mmio 144 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 145 val s2_cache_miss = io.dcacheResp.bits.miss 146 val s2_cache_replay = io.dcacheResp.bits.replay 147 148 io.dcacheResp.ready := true.B 149 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 150 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 151 152 // feedback tlb result to RS 153 io.tlbFeedback.valid := io.in.valid 154 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 155 io.tlbFeedback.bits.roqIdx := s2_uop.roqIdx 156 157 val forwardMask = io.out.bits.forwardMask 158 val forwardData = io.out.bits.forwardData 159 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 160 161 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 162 s2_uop.cf.pc, 163 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 164 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 165 ) 166 167 // data merge 168 val rdata = VecInit((0 until XLEN / 8).map(j => 169 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 170 val rdataSel = LookupTree(s2_paddr(2, 0), List( 171 "b000".U -> rdata(63, 0), 172 "b001".U -> rdata(63, 8), 173 "b010".U -> rdata(63, 16), 174 "b011".U -> rdata(63, 24), 175 "b100".U -> rdata(63, 32), 176 "b101".U -> rdata(63, 40), 177 "b110".U -> rdata(63, 48), 178 "b111".U -> rdata(63, 56) 179 )) 180 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 181 182 // TODO: ECC check 183 184 io.out.valid := io.in.valid && !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 185 // Inst will be canceled in store queue / lsq, 186 // so we do not need to care about flush in load / store unit's out.valid 187 io.out.bits := io.in.bits 188 io.out.bits.data := rdataPartialLoad 189 // when exception occurs, set it to not miss and let it write back to roq (via int port) 190 io.out.bits.miss := s2_cache_miss && !fullForward && !s2_exception 191 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 192 io.out.bits.mmio := s2_mmio 193 194 io.in.ready := io.out.ready || !io.in.valid 195 196 // merge forward result 197 // lsq has higher priority than sbuffer 198 io.lsq := DontCare 199 io.sbuffer := DontCare 200 // generate XLEN/8 Muxs 201 for (i <- 0 until XLEN / 8) { 202 when (io.sbuffer.forwardMask(i)) { 203 io.out.bits.forwardMask(i) := true.B 204 io.out.bits.forwardData(i) := io.sbuffer.forwardData(i) 205 } 206 when (io.lsq.forwardMask(i)) { 207 io.out.bits.forwardMask(i) := true.B 208 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 209 } 210 } 211 212 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 213 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 214 io.out.bits.forwardData.asUInt, io.out.bits.forwardMask.asUInt 215 ) 216} 217 218class LoadUnit extends XSModule with HasLoadHelper { 219 val io = IO(new Bundle() { 220 val ldin = Flipped(Decoupled(new ExuInput)) 221 val ldout = Decoupled(new ExuOutput) 222 val fpout = Decoupled(new ExuOutput) 223 val redirect = Flipped(ValidIO(new Redirect)) 224 val tlbFeedback = ValidIO(new TlbFeedback) 225 val dcache = new DCacheLoadIO 226 val dtlb = new TlbRequestIO() 227 val sbuffer = new LoadForwardQueryIO 228 val lsq = new LoadToLsqIO 229 }) 230 231 val load_s0 = Module(new LoadUnit_S0) 232 val load_s1 = Module(new LoadUnit_S1) 233 val load_s2 = Module(new LoadUnit_S2) 234 235 load_s0.io.in <> io.ldin 236 load_s0.io.dtlbReq <> io.dtlb.req 237 load_s0.io.dcacheReq <> io.dcache.req 238 239 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 240 241 load_s1.io.dtlbResp <> io.dtlb.resp 242 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 243 io.dcache.s1_kill <> load_s1.io.dcacheKill 244 load_s1.io.sbuffer <> io.sbuffer 245 load_s1.io.lsq <> io.lsq.forward 246 247 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 248 249 load_s2.io.tlbFeedback <> io.tlbFeedback 250 load_s2.io.dcacheResp <> io.dcache.resp 251 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 252 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 253 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 254 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 255 256 XSDebug(load_s0.io.out.valid, 257 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 258 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 259 XSDebug(load_s1.io.out.valid, 260 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 261 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 262 263 // writeback to LSQ 264 // Current dcache use MSHR 265 // Load queue will be updated at s2 for both hit/miss int/fp load 266 io.lsq.loadIn.valid := load_s2.io.out.valid 267 io.lsq.loadIn.bits := load_s2.io.out.bits 268 269 // write to rob and writeback bus 270 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss 271 val refillFpLoad = io.lsq.ldout.bits.uop.ctrl.fpWen 272 273 // Int load, if hit, will be writebacked at s2 274 val intHitLoadOut = Wire(Valid(new ExuOutput)) 275 intHitLoadOut.valid := s2_wb_valid && !load_s2.io.out.bits.uop.ctrl.fpWen 276 intHitLoadOut.bits.uop := load_s2.io.out.bits.uop 277 intHitLoadOut.bits.data := load_s2.io.out.bits.data 278 intHitLoadOut.bits.redirectValid := false.B 279 intHitLoadOut.bits.redirect := DontCare 280 intHitLoadOut.bits.brUpdate := DontCare 281 intHitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 282 intHitLoadOut.bits.debug.isPerfCnt := false.B 283 intHitLoadOut.bits.fflags := DontCare 284 285 load_s2.io.out.ready := true.B 286 287 io.ldout.bits := Mux(intHitLoadOut.valid, intHitLoadOut.bits, io.lsq.ldout.bits) 288 io.ldout.valid := intHitLoadOut.valid || io.lsq.ldout.valid && !refillFpLoad 289 290 // Fp load, if hit, will be send to recoder at s2, then it will be recoded & writebacked at s3 291 val fpHitLoadOut = Wire(Valid(new ExuOutput)) 292 fpHitLoadOut.valid := s2_wb_valid && load_s2.io.out.bits.uop.ctrl.fpWen 293 fpHitLoadOut.bits := intHitLoadOut.bits 294 295 val fpLoadOut = Wire(Valid(new ExuOutput)) 296 fpLoadOut.bits := Mux(fpHitLoadOut.valid, fpHitLoadOut.bits, io.lsq.ldout.bits) 297 fpLoadOut.valid := fpHitLoadOut.valid || io.lsq.ldout.valid && refillFpLoad 298 299 val fpLoadOutReg = RegNext(fpLoadOut) 300 io.fpout.bits := fpLoadOutReg.bits 301 io.fpout.bits.data := fpRdataHelper(fpLoadOutReg.bits.uop, fpLoadOutReg.bits.data) // recode 302 io.fpout.valid := RegNext(fpLoadOut.valid) 303 304 io.lsq.ldout.ready := Mux(refillFpLoad, !fpHitLoadOut.valid, !intHitLoadOut.valid) 305 306 when(io.ldout.fire()){ 307 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 308 } 309 310 when(io.fpout.fire()){ 311 XSDebug("fpout %x\n", io.fpout.bits.uop.cf.pc) 312 } 313} 314