1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants} 8import xiangshan.backend.LSUOpType 9 10class AtomicsUnit extends XSModule with MemoryOpConstants{ 11 val io = IO(new Bundle() { 12 val in = Flipped(Decoupled(new ExuInput)) 13 val out = Decoupled(new ExuOutput) 14 val dcache = new DCacheWordIO 15 val dtlb = new TlbRequestIO 16 val flush_sbuffer = new SbufferFlushBundle 17 val tlbFeedback = ValidIO(new TlbFeedback) 18 val redirect = Flipped(ValidIO(new Redirect)) 19 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 20 }) 21 22 //------------------------------------------------------- 23 // Atomics Memory Accsess FSM 24 //------------------------------------------------------- 25 val s_invalid :: s_tlb :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(7) 26 val state = RegInit(s_invalid) 27 val in = Reg(new ExuInput()) 28 val atom_override_xtval = RegInit(false.B) 29 // paddr after translation 30 val paddr = Reg(UInt()) 31 val is_mmio = Reg(Bool()) 32 // dcache response data 33 val resp_data = Reg(UInt()) 34 val is_lrsc_valid = Reg(Bool()) 35 36 io.exceptionAddr.valid := atom_override_xtval 37 io.exceptionAddr.bits := in.src1 38 39 // assign default value to output signals 40 io.in.ready := false.B 41 io.out.valid := false.B 42 io.out.bits := DontCare 43 44 io.dcache.req.valid := false.B 45 io.dcache.req.bits := DontCare 46 io.dcache.resp.ready := false.B 47 48 io.dtlb.req.valid := false.B 49 io.dtlb.req.bits := DontCare 50 io.dtlb.resp.ready := false.B 51 52 io.flush_sbuffer.valid := false.B 53 54 XSDebug("state: %d\n", state) 55 56 when (state === s_invalid) { 57 io.in.ready := true.B 58 when (io.in.fire()) { 59 in := io.in.bits 60 state := s_tlb 61 } 62 } 63 64 // Send TLB feedback to store issue queue 65 // we send feedback right after we receives request 66 // also, we always treat amo as tlb hit 67 // since we will continue polling tlb all by ourself 68 io.tlbFeedback.valid := RegNext(RegNext(io.in.valid)) 69 io.tlbFeedback.bits.hit := true.B 70 io.tlbFeedback.bits.roqIdx := in.uop.roqIdx 71 72 // tlb translation, manipulating signals && deal with exception 73 when (state === s_tlb) { 74 // send req to dtlb 75 // keep firing until tlb hit 76 io.dtlb.req.valid := true.B 77 io.dtlb.req.bits.vaddr := in.src1 78 io.dtlb.req.bits.roqIdx := in.uop.roqIdx 79 io.dtlb.resp.ready := true.B 80 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 81 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 82 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 83 84 when(io.dtlb.resp.fire && !io.dtlb.resp.bits.miss){ 85 // exception handling 86 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 87 "b00".U -> true.B, //b 88 "b01".U -> (in.src1(0) === 0.U), //h 89 "b10".U -> (in.src1(1,0) === 0.U), //w 90 "b11".U -> (in.src1(2,0) === 0.U) //d 91 )) 92 in.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 93 in.uop.cf.exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 94 in.uop.cf.exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 95 in.uop.cf.exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 96 in.uop.cf.exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 97 val exception = !addrAligned || 98 io.dtlb.resp.bits.excp.pf.st || 99 io.dtlb.resp.bits.excp.pf.ld || 100 io.dtlb.resp.bits.excp.af.st || 101 io.dtlb.resp.bits.excp.af.ld 102 is_mmio := io.dtlb.resp.bits.mmio 103 when (exception) { 104 // check for exceptions 105 // if there are exceptions, no need to execute it 106 state := s_finish 107 atom_override_xtval := true.B 108 } .otherwise { 109 paddr := io.dtlb.resp.bits.paddr 110 state := s_flush_sbuffer_req 111 } 112 } 113 } 114 115 116 when (state === s_flush_sbuffer_req) { 117 io.flush_sbuffer.valid := true.B 118 state := s_flush_sbuffer_resp 119 } 120 121 when (state === s_flush_sbuffer_resp) { 122 when (io.flush_sbuffer.empty) { 123 state := s_cache_req 124 } 125 } 126 127 when (state === s_cache_req) { 128 io.dcache.req.valid := true.B 129 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 130 LSUOpType.lr_w -> M_XLR, 131 LSUOpType.sc_w -> M_XSC, 132 LSUOpType.amoswap_w -> M_XA_SWAP, 133 LSUOpType.amoadd_w -> M_XA_ADD, 134 LSUOpType.amoxor_w -> M_XA_XOR, 135 LSUOpType.amoand_w -> M_XA_AND, 136 LSUOpType.amoor_w -> M_XA_OR, 137 LSUOpType.amomin_w -> M_XA_MIN, 138 LSUOpType.amomax_w -> M_XA_MAX, 139 LSUOpType.amominu_w -> M_XA_MINU, 140 LSUOpType.amomaxu_w -> M_XA_MAXU, 141 142 LSUOpType.lr_d -> M_XLR, 143 LSUOpType.sc_d -> M_XSC, 144 LSUOpType.amoswap_d -> M_XA_SWAP, 145 LSUOpType.amoadd_d -> M_XA_ADD, 146 LSUOpType.amoxor_d -> M_XA_XOR, 147 LSUOpType.amoand_d -> M_XA_AND, 148 LSUOpType.amoor_d -> M_XA_OR, 149 LSUOpType.amomin_d -> M_XA_MIN, 150 LSUOpType.amomax_d -> M_XA_MAX, 151 LSUOpType.amominu_d -> M_XA_MINU, 152 LSUOpType.amomaxu_d -> M_XA_MAXU 153 )) 154 155 io.dcache.req.bits.addr := paddr 156 io.dcache.req.bits.data := genWdata(in.src2, in.uop.ctrl.fuOpType(1,0)) 157 // TODO: atomics do need mask: fix mask 158 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 159 io.dcache.req.bits.meta.id := DontCare 160 io.dcache.req.bits.meta.paddr := paddr 161 io.dcache.req.bits.meta.tlb_miss := false.B 162 io.dcache.req.bits.meta.replay := false.B 163 164 when(io.dcache.req.fire()){ 165 state := s_cache_resp 166 } 167 } 168 169 when (state === s_cache_resp) { 170 io.dcache.resp.ready := true.B 171 when(io.dcache.resp.fire()) { 172 is_lrsc_valid := io.dcache.resp.bits.meta.id 173 val rdata = io.dcache.resp.bits.data 174 val rdataSel = LookupTree(paddr(2, 0), List( 175 "b000".U -> rdata(63, 0), 176 "b001".U -> rdata(63, 8), 177 "b010".U -> rdata(63, 16), 178 "b011".U -> rdata(63, 24), 179 "b100".U -> rdata(63, 32), 180 "b101".U -> rdata(63, 40), 181 "b110".U -> rdata(63, 48), 182 "b111".U -> rdata(63, 56) 183 )) 184 185 resp_data := LookupTree(in.uop.ctrl.fuOpType, List( 186 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 187 LSUOpType.sc_w -> rdata, 188 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 189 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 190 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 191 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 192 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 193 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 194 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 195 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 196 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 197 198 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 199 LSUOpType.sc_d -> rdata, 200 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 201 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 202 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 203 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 204 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 205 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 206 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 207 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 208 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 209 )) 210 211 state := s_finish 212 } 213 } 214 215 when (state === s_finish) { 216 io.out.valid := true.B 217 io.out.bits.uop := in.uop 218 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 219 io.out.bits.data := resp_data 220 io.out.bits.redirectValid := false.B 221 io.out.bits.redirect := DontCare 222 io.out.bits.brUpdate := DontCare 223 io.out.bits.debug.isMMIO := is_mmio 224 when (io.out.fire()) { 225 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 226 state := s_invalid 227 } 228 } 229 230 when(io.redirect.valid){ 231 atom_override_xtval := false.B 232 } 233}