1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache.{DCacheWordIOWithVaddr, MemoryOpConstants} 25import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 26import difftest._ 27import xiangshan.backend.fu.PMPRespBundle 28 29class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants{ 30 val io = IO(new Bundle() { 31 val hartId = Input(UInt(8.W)) 32 val in = Flipped(Decoupled(new ExuInput)) 33 val storeDataIn = Flipped(Valid(new StoreDataBundle)) // src2 from rs 34 val out = Decoupled(new ExuOutput) 35 val dcache = new DCacheWordIOWithVaddr 36 val dtlb = new TlbRequestIO 37 val pmpResp = Flipped(new PMPRespBundle()) 38 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 39 val flush_sbuffer = new SbufferFlushBundle 40 val feedbackSlow = ValidIO(new RSFeedback) 41 val redirect = Flipped(ValidIO(new Redirect)) 42 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 43 }) 44 45 //------------------------------------------------------- 46 // Atomics Memory Accsess FSM 47 //------------------------------------------------------- 48 val s_invalid :: s_tlb :: s_pm :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(8) 49 val state = RegInit(s_invalid) 50 val data_valid = RegInit(false.B) 51 val in = Reg(new ExuInput()) 52 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 53 val atom_override_xtval = RegInit(false.B) 54 // paddr after translation 55 val paddr = Reg(UInt()) 56 val is_mmio = Reg(Bool()) 57 // dcache response data 58 val resp_data = Reg(UInt()) 59 val resp_data_wire = WireInit(0.U) 60 val is_lrsc_valid = Reg(Bool()) 61 62 // Difftest signals 63 val paddr_reg = Reg(UInt(64.W)) 64 val data_reg = Reg(UInt(64.W)) 65 val mask_reg = Reg(UInt(8.W)) 66 val fuop_reg = Reg(UInt(8.W)) 67 68 io.exceptionAddr.valid := atom_override_xtval 69 io.exceptionAddr.bits := in.src(0) 70 71 // assign default value to output signals 72 io.in.ready := false.B 73 io.out.valid := false.B 74 io.out.bits := DontCare 75 76 io.dcache.req.valid := false.B 77 io.dcache.req.bits := DontCare 78 io.dcache.resp.ready := false.B 79 80 io.dtlb.req.valid := false.B 81 io.dtlb.req.bits := DontCare 82 io.dtlb.resp.ready := false.B 83 84 io.flush_sbuffer.valid := false.B 85 86 XSDebug("state: %d\n", state) 87 88 when (state === s_invalid) { 89 io.in.ready := true.B 90 when (io.in.fire()) { 91 in := io.in.bits 92 in.src(1) := in.src(1) // leave src2 unchanged 93 state := s_tlb 94 } 95 } 96 97 when (io.storeDataIn.fire()) { 98 in.src(1) := io.storeDataIn.bits.data 99 data_valid := true.B 100 } 101 102 assert(!(io.storeDataIn.fire() && data_valid), "atomic unit re-receive data") 103 104 // Send TLB feedback to store issue queue 105 // we send feedback right after we receives request 106 // also, we always treat amo as tlb hit 107 // since we will continue polling tlb all by ourself 108 io.feedbackSlow.valid := RegNext(RegNext(io.in.valid)) 109 io.feedbackSlow.bits.hit := true.B 110 io.feedbackSlow.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 111 io.feedbackSlow.bits.flushState := DontCare 112 io.feedbackSlow.bits.sourceType := DontCare 113 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 114 115 // tlb translation, manipulating signals && deal with exception 116 when (state === s_tlb) { 117 // send req to dtlb 118 // keep firing until tlb hit 119 io.dtlb.req.valid := true.B 120 io.dtlb.req.bits.vaddr := in.src(0) 121 io.dtlb.req.bits.robIdx := in.uop.robIdx 122 io.dtlb.resp.ready := true.B 123 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 124 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 125 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 126 io.dtlb.req.bits.debug.isFirstIssue := false.B 127 128 when(io.dtlb.resp.fire){ 129 paddr := io.dtlb.resp.bits.paddr 130 // exception handling 131 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 132 "b00".U -> true.B, //b 133 "b01".U -> (in.src(0)(0) === 0.U), //h 134 "b10".U -> (in.src(0)(1,0) === 0.U), //w 135 "b11".U -> (in.src(0)(2,0) === 0.U) //d 136 )) 137 exceptionVec(storeAddrMisaligned) := !addrAligned 138 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 139 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 140 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 141 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 142 143 when (!io.dtlb.resp.bits.miss) { 144 when (!addrAligned) { 145 // NOTE: when addrAligned, do not need to wait tlb actually 146 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 147 // if there are exceptions, no need to execute it 148 state := s_finish 149 atom_override_xtval := true.B 150 } .otherwise { 151 state := s_pm 152 } 153 } 154 } 155 } 156 157 when (state === s_pm) { 158 is_mmio := io.pmpResp.mmio 159 // NOTE: only handle load/store exception here, if other exception happens, don't send here 160 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 161 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 162 val exception_pa = io.pmpResp.st 163 when (exception_va || exception_pa) { 164 state := s_finish 165 atom_override_xtval := true.B 166 }.otherwise { 167 state := s_flush_sbuffer_req 168 } 169 } 170 171 when (state === s_flush_sbuffer_req) { 172 io.flush_sbuffer.valid := true.B 173 state := s_flush_sbuffer_resp 174 } 175 176 when (state === s_flush_sbuffer_resp) { 177 when (io.flush_sbuffer.empty) { 178 state := s_cache_req 179 } 180 } 181 182 when (state === s_cache_req) { 183 io.dcache.req.valid := true.B 184 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 185 LSUOpType.lr_w -> M_XLR, 186 LSUOpType.sc_w -> M_XSC, 187 LSUOpType.amoswap_w -> M_XA_SWAP, 188 LSUOpType.amoadd_w -> M_XA_ADD, 189 LSUOpType.amoxor_w -> M_XA_XOR, 190 LSUOpType.amoand_w -> M_XA_AND, 191 LSUOpType.amoor_w -> M_XA_OR, 192 LSUOpType.amomin_w -> M_XA_MIN, 193 LSUOpType.amomax_w -> M_XA_MAX, 194 LSUOpType.amominu_w -> M_XA_MINU, 195 LSUOpType.amomaxu_w -> M_XA_MAXU, 196 197 LSUOpType.lr_d -> M_XLR, 198 LSUOpType.sc_d -> M_XSC, 199 LSUOpType.amoswap_d -> M_XA_SWAP, 200 LSUOpType.amoadd_d -> M_XA_ADD, 201 LSUOpType.amoxor_d -> M_XA_XOR, 202 LSUOpType.amoand_d -> M_XA_AND, 203 LSUOpType.amoor_d -> M_XA_OR, 204 LSUOpType.amomin_d -> M_XA_MIN, 205 LSUOpType.amomax_d -> M_XA_MAX, 206 LSUOpType.amominu_d -> M_XA_MINU, 207 LSUOpType.amomaxu_d -> M_XA_MAXU 208 )) 209 210 io.dcache.req.bits.addr := paddr 211 io.dcache.req.bits.vaddr := in.src(0) // vaddr 212 io.dcache.req.bits.data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 213 // TODO: atomics do need mask: fix mask 214 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 215 io.dcache.req.bits.id := DontCare 216 217 when(io.dcache.req.fire()){ 218 state := s_cache_resp 219 paddr_reg := io.dcache.req.bits.addr 220 data_reg := io.dcache.req.bits.data 221 mask_reg := io.dcache.req.bits.mask 222 fuop_reg := in.uop.ctrl.fuOpType 223 } 224 } 225 226 when (state === s_cache_resp) { 227 io.dcache.resp.ready := data_valid 228 when(io.dcache.resp.fire()) { 229 is_lrsc_valid := io.dcache.resp.bits.id 230 val rdata = io.dcache.resp.bits.data 231 val rdataSel = LookupTree(paddr(2, 0), List( 232 "b000".U -> rdata(63, 0), 233 "b001".U -> rdata(63, 8), 234 "b010".U -> rdata(63, 16), 235 "b011".U -> rdata(63, 24), 236 "b100".U -> rdata(63, 32), 237 "b101".U -> rdata(63, 40), 238 "b110".U -> rdata(63, 48), 239 "b111".U -> rdata(63, 56) 240 )) 241 242 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 243 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 244 LSUOpType.sc_w -> rdata, 245 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 246 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 247 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 248 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 249 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 250 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 251 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 252 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 253 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 254 255 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 256 LSUOpType.sc_d -> rdata, 257 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 258 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 259 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 260 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 261 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 262 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 263 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 264 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 265 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 266 )) 267 268 resp_data := resp_data_wire 269 state := s_finish 270 } 271 } 272 273 when (state === s_finish) { 274 io.out.valid := true.B 275 io.out.bits.uop := in.uop 276 io.out.bits.uop.cf.exceptionVec := exceptionVec 277 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 278 io.out.bits.data := resp_data 279 io.out.bits.redirectValid := false.B 280 io.out.bits.redirect := DontCare 281 io.out.bits.debug.isMMIO := is_mmio 282 io.out.bits.debug.paddr := paddr 283 when (io.out.fire()) { 284 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 285 state := s_invalid 286 } 287 data_valid := false.B 288 } 289 290 when (io.redirect.valid) { 291 atom_override_xtval := false.B 292 } 293 294 if (env.EnableDifftest) { 295 val difftest = Module(new DifftestAtomicEvent) 296 difftest.io.clock := clock 297 difftest.io.coreid := io.hartId 298 difftest.io.atomicResp := io.dcache.resp.fire() 299 difftest.io.atomicAddr := paddr_reg 300 difftest.io.atomicData := data_reg 301 difftest.io.atomicMask := mask_reg 302 difftest.io.atomicFuop := fuop_reg 303 difftest.io.atomicOut := resp_data_wire 304 } 305} 306