1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants} 8import xiangshan.backend.LSUOpType 9 10class AtomicsUnit extends XSModule with MemoryOpConstants{ 11 val io = IO(new Bundle() { 12 val in = Flipped(Decoupled(new ExuInput)) 13 val out = Decoupled(new ExuOutput) 14 val dcache = new DCacheWordIO 15 val dtlb = new TlbRequestIO 16 val flush_sbuffer = new SbufferFlushBundle 17 val tlbFeedback = ValidIO(new TlbFeedback) 18 val redirect = Flipped(ValidIO(new Redirect)) 19 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 20 }) 21 22 //------------------------------------------------------- 23 // Atomics Memory Accsess FSM 24 //------------------------------------------------------- 25 val s_invalid :: s_tlb :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(7) 26 val state = RegInit(s_invalid) 27 val in = Reg(new ExuInput()) 28 val atom_override_xtval = RegInit(false.B) 29 // paddr after translation 30 val paddr = Reg(UInt()) 31 // dcache response data 32 val resp_data = Reg(UInt()) 33 val is_lrsc_valid = Reg(Bool()) 34 35 io.exceptionAddr.valid := atom_override_xtval 36 io.exceptionAddr.bits := in.src1 37 38 // assign default value to output signals 39 io.in.ready := false.B 40 io.out.valid := false.B 41 io.out.bits := DontCare 42 43 io.dcache.req.valid := false.B 44 io.dcache.req.bits := DontCare 45 io.dcache.resp.ready := false.B 46 47 io.dtlb.req.valid := false.B 48 io.dtlb.req.bits := DontCare 49 io.dtlb.resp.ready := false.B 50 51 io.flush_sbuffer.valid := false.B 52 53 XSDebug("state: %d\n", state) 54 55 when (state === s_invalid) { 56 io.in.ready := true.B 57 when (io.in.fire()) { 58 in := io.in.bits 59 state := s_tlb 60 } 61 } 62 63 // Send TLB feedback to store issue queue 64 // we send feedback right after we receives request 65 // also, we always treat amo as tlb hit 66 // since we will continue polling tlb all by ourself 67 io.tlbFeedback.valid := RegNext(RegNext(io.in.valid)) 68 io.tlbFeedback.bits.hit := true.B 69 io.tlbFeedback.bits.roqIdx := in.uop.roqIdx 70 71 72 // tlb translation, manipulating signals && deal with exception 73 when (state === s_tlb) { 74 // send req to dtlb 75 // keep firing until tlb hit 76 io.dtlb.req.valid := true.B 77 io.dtlb.req.bits.vaddr := in.src1 78 io.dtlb.req.bits.roqIdx := in.uop.roqIdx 79 io.dtlb.resp.ready := true.B 80 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 81 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.read, TlbCmd.write) 82 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 83 84 when(io.dtlb.resp.fire && !io.dtlb.resp.bits.miss){ 85 // exception handling 86 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 87 "b00".U -> true.B, //b 88 "b01".U -> (in.src1(0) === 0.U), //h 89 "b10".U -> (in.src1(1,0) === 0.U), //w 90 "b11".U -> (in.src1(2,0) === 0.U) //d 91 )) 92 in.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 93 in.uop.cf.exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 94 in.uop.cf.exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 95 val exception = !addrAligned || io.dtlb.resp.bits.excp.pf.st || io.dtlb.resp.bits.excp.pf.ld 96 when (exception) { 97 // check for exceptions 98 // if there are exceptions, no need to execute it 99 state := s_finish 100 atom_override_xtval := true.B 101 } .otherwise { 102 paddr := io.dtlb.resp.bits.paddr 103 state := s_flush_sbuffer_req 104 } 105 } 106 } 107 108 109 when (state === s_flush_sbuffer_req) { 110 io.flush_sbuffer.valid := true.B 111 state := s_flush_sbuffer_resp 112 } 113 114 when (state === s_flush_sbuffer_resp) { 115 when (io.flush_sbuffer.empty) { 116 state := s_cache_req 117 } 118 } 119 120 when (state === s_cache_req) { 121 io.dcache.req.valid := true.B 122 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 123 LSUOpType.lr_w -> M_XLR, 124 LSUOpType.sc_w -> M_XSC, 125 LSUOpType.amoswap_w -> M_XA_SWAP, 126 LSUOpType.amoadd_w -> M_XA_ADD, 127 LSUOpType.amoxor_w -> M_XA_XOR, 128 LSUOpType.amoand_w -> M_XA_AND, 129 LSUOpType.amoor_w -> M_XA_OR, 130 LSUOpType.amomin_w -> M_XA_MIN, 131 LSUOpType.amomax_w -> M_XA_MAX, 132 LSUOpType.amominu_w -> M_XA_MINU, 133 LSUOpType.amomaxu_w -> M_XA_MAXU, 134 135 LSUOpType.lr_d -> M_XLR, 136 LSUOpType.sc_d -> M_XSC, 137 LSUOpType.amoswap_d -> M_XA_SWAP, 138 LSUOpType.amoadd_d -> M_XA_ADD, 139 LSUOpType.amoxor_d -> M_XA_XOR, 140 LSUOpType.amoand_d -> M_XA_AND, 141 LSUOpType.amoor_d -> M_XA_OR, 142 LSUOpType.amomin_d -> M_XA_MIN, 143 LSUOpType.amomax_d -> M_XA_MAX, 144 LSUOpType.amominu_d -> M_XA_MINU, 145 LSUOpType.amomaxu_d -> M_XA_MAXU 146 )) 147 148 io.dcache.req.bits.addr := paddr 149 io.dcache.req.bits.data := genWdata(in.src2, in.uop.ctrl.fuOpType(1,0)) 150 // TODO: atomics do need mask: fix mask 151 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 152 io.dcache.req.bits.meta.id := DontCare 153 io.dcache.req.bits.meta.paddr := paddr 154 io.dcache.req.bits.meta.tlb_miss := false.B 155 io.dcache.req.bits.meta.replay := false.B 156 157 when(io.dcache.req.fire()){ 158 state := s_cache_resp 159 } 160 } 161 162 when (state === s_cache_resp) { 163 io.dcache.resp.ready := true.B 164 when(io.dcache.resp.fire()) { 165 is_lrsc_valid := io.dcache.resp.bits.meta.id 166 val rdata = io.dcache.resp.bits.data 167 val rdataSel = LookupTree(paddr(2, 0), List( 168 "b000".U -> rdata(63, 0), 169 "b001".U -> rdata(63, 8), 170 "b010".U -> rdata(63, 16), 171 "b011".U -> rdata(63, 24), 172 "b100".U -> rdata(63, 32), 173 "b101".U -> rdata(63, 40), 174 "b110".U -> rdata(63, 48), 175 "b111".U -> rdata(63, 56) 176 )) 177 178 resp_data := LookupTree(in.uop.ctrl.fuOpType, List( 179 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 180 LSUOpType.sc_w -> rdata, 181 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 182 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 183 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 184 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 185 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 186 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 187 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 188 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 189 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 190 191 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 192 LSUOpType.sc_d -> rdata, 193 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 194 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 195 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 196 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 197 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 198 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 199 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 200 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 201 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 202 )) 203 204 state := s_finish 205 } 206 } 207 208 when (state === s_finish) { 209 io.out.valid := true.B 210 io.out.bits.uop := in.uop 211 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 212 io.out.bits.data := resp_data 213 io.out.bits.redirectValid := false.B 214 io.out.bits.redirect := DontCare 215 io.out.bits.brUpdate := DontCare 216 io.out.bits.debug.isMMIO := AddressSpace.isMMIO(paddr) 217 when (io.out.fire()) { 218 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 219 state := s_invalid 220 } 221 } 222 223 when(io.redirect.valid){ 224 atom_override_xtval := false.B 225 } 226}