1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants} 8import xiangshan.backend.LSUOpType 9 10class AtomicsUnit extends XSModule with MemoryOpConstants{ 11 val io = IO(new Bundle() { 12 val in = Flipped(Decoupled(new ExuInput)) 13 val out = Decoupled(new ExuOutput) 14 val dcache = new DCacheWordIO 15 val dtlb = new TlbRequestIO 16 val flush_sbuffer = new SbufferFlushBundle 17 val tlbFeedback = ValidIO(new TlbFeedback) 18 val redirect = Flipped(ValidIO(new Redirect)) 19 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 20 }) 21 22 //------------------------------------------------------- 23 // Atomics Memory Accsess FSM 24 //------------------------------------------------------- 25 val s_invalid :: s_tlb :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(7) 26 val state = RegInit(s_invalid) 27 val in = Reg(new ExuInput()) 28 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 29 val atom_override_xtval = RegInit(false.B) 30 // paddr after translation 31 val paddr = Reg(UInt()) 32 val is_mmio = Reg(Bool()) 33 // dcache response data 34 val resp_data = Reg(UInt()) 35 val is_lrsc_valid = Reg(Bool()) 36 37 io.exceptionAddr.valid := atom_override_xtval 38 io.exceptionAddr.bits := in.src1 39 40 // assign default value to output signals 41 io.in.ready := false.B 42 io.out.valid := false.B 43 io.out.bits := DontCare 44 45 io.dcache.req.valid := false.B 46 io.dcache.req.bits := DontCare 47 io.dcache.resp.ready := false.B 48 49 io.dtlb.req.valid := false.B 50 io.dtlb.req.bits := DontCare 51 io.dtlb.resp.ready := false.B 52 53 io.flush_sbuffer.valid := false.B 54 55 XSDebug("state: %d\n", state) 56 57 when (state === s_invalid) { 58 io.in.ready := true.B 59 when (io.in.fire()) { 60 in := io.in.bits 61 state := s_tlb 62 } 63 } 64 65 // Send TLB feedback to store issue queue 66 // we send feedback right after we receives request 67 // also, we always treat amo as tlb hit 68 // since we will continue polling tlb all by ourself 69 io.tlbFeedback.valid := RegNext(RegNext(io.in.valid)) 70 io.tlbFeedback.bits.hit := true.B 71 io.tlbFeedback.bits.roqIdx := in.uop.roqIdx 72 73 // tlb translation, manipulating signals && deal with exception 74 when (state === s_tlb) { 75 // send req to dtlb 76 // keep firing until tlb hit 77 io.dtlb.req.valid := true.B 78 io.dtlb.req.bits.vaddr := in.src1 79 io.dtlb.req.bits.roqIdx := in.uop.roqIdx 80 io.dtlb.resp.ready := true.B 81 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 82 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 83 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 84 85 when(io.dtlb.resp.fire && !io.dtlb.resp.bits.miss){ 86 // exception handling 87 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 88 "b00".U -> true.B, //b 89 "b01".U -> (in.src1(0) === 0.U), //h 90 "b10".U -> (in.src1(1,0) === 0.U), //w 91 "b11".U -> (in.src1(2,0) === 0.U) //d 92 )) 93 exceptionVec(storeAddrMisaligned) := !addrAligned 94 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 95 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 96 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 97 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 98 val exception = !addrAligned || 99 io.dtlb.resp.bits.excp.pf.st || 100 io.dtlb.resp.bits.excp.pf.ld || 101 io.dtlb.resp.bits.excp.af.st || 102 io.dtlb.resp.bits.excp.af.ld 103 is_mmio := io.dtlb.resp.bits.mmio 104 when (exception) { 105 // check for exceptions 106 // if there are exceptions, no need to execute it 107 state := s_finish 108 atom_override_xtval := true.B 109 } .otherwise { 110 paddr := io.dtlb.resp.bits.paddr 111 state := s_flush_sbuffer_req 112 } 113 } 114 } 115 116 117 when (state === s_flush_sbuffer_req) { 118 io.flush_sbuffer.valid := true.B 119 state := s_flush_sbuffer_resp 120 } 121 122 when (state === s_flush_sbuffer_resp) { 123 when (io.flush_sbuffer.empty) { 124 state := s_cache_req 125 } 126 } 127 128 when (state === s_cache_req) { 129 io.dcache.req.valid := true.B 130 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 131 LSUOpType.lr_w -> M_XLR, 132 LSUOpType.sc_w -> M_XSC, 133 LSUOpType.amoswap_w -> M_XA_SWAP, 134 LSUOpType.amoadd_w -> M_XA_ADD, 135 LSUOpType.amoxor_w -> M_XA_XOR, 136 LSUOpType.amoand_w -> M_XA_AND, 137 LSUOpType.amoor_w -> M_XA_OR, 138 LSUOpType.amomin_w -> M_XA_MIN, 139 LSUOpType.amomax_w -> M_XA_MAX, 140 LSUOpType.amominu_w -> M_XA_MINU, 141 LSUOpType.amomaxu_w -> M_XA_MAXU, 142 143 LSUOpType.lr_d -> M_XLR, 144 LSUOpType.sc_d -> M_XSC, 145 LSUOpType.amoswap_d -> M_XA_SWAP, 146 LSUOpType.amoadd_d -> M_XA_ADD, 147 LSUOpType.amoxor_d -> M_XA_XOR, 148 LSUOpType.amoand_d -> M_XA_AND, 149 LSUOpType.amoor_d -> M_XA_OR, 150 LSUOpType.amomin_d -> M_XA_MIN, 151 LSUOpType.amomax_d -> M_XA_MAX, 152 LSUOpType.amominu_d -> M_XA_MINU, 153 LSUOpType.amomaxu_d -> M_XA_MAXU 154 )) 155 156 io.dcache.req.bits.addr := paddr 157 io.dcache.req.bits.data := genWdata(in.src2, in.uop.ctrl.fuOpType(1,0)) 158 // TODO: atomics do need mask: fix mask 159 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 160 io.dcache.req.bits.id := DontCare 161 162 when(io.dcache.req.fire()){ 163 state := s_cache_resp 164 } 165 } 166 167 when (state === s_cache_resp) { 168 io.dcache.resp.ready := true.B 169 when(io.dcache.resp.fire()) { 170 is_lrsc_valid := io.dcache.resp.bits.id 171 val rdata = io.dcache.resp.bits.data 172 val rdataSel = LookupTree(paddr(2, 0), List( 173 "b000".U -> rdata(63, 0), 174 "b001".U -> rdata(63, 8), 175 "b010".U -> rdata(63, 16), 176 "b011".U -> rdata(63, 24), 177 "b100".U -> rdata(63, 32), 178 "b101".U -> rdata(63, 40), 179 "b110".U -> rdata(63, 48), 180 "b111".U -> rdata(63, 56) 181 )) 182 183 resp_data := LookupTree(in.uop.ctrl.fuOpType, List( 184 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 185 LSUOpType.sc_w -> rdata, 186 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 187 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 188 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 189 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 190 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 191 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 192 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 193 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 194 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 195 196 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 197 LSUOpType.sc_d -> rdata, 198 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 199 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 200 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 201 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 202 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 203 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 204 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 205 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 206 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 207 )) 208 209 state := s_finish 210 } 211 } 212 213 when (state === s_finish) { 214 io.out.valid := true.B 215 io.out.bits.uop := in.uop 216 io.out.bits.uop.cf.exceptionVec := exceptionVec 217 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 218 io.out.bits.data := resp_data 219 io.out.bits.redirectValid := false.B 220 io.out.bits.redirect := DontCare 221 io.out.bits.brUpdate := DontCare 222 io.out.bits.debug.isMMIO := is_mmio 223 when (io.out.fire()) { 224 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 225 state := s_invalid 226 } 227 } 228 229 when(io.redirect.valid){ 230 atom_override_xtval := false.B 231 } 232} 233