1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache.{DCacheWordIOWithVaddr, MemoryOpConstants} 25import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 26import difftest._ 27import xiangshan.backend.fu.PMPRespBundle 28 29class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants{ 30 val io = IO(new Bundle() { 31 val in = Flipped(Decoupled(new ExuInput)) 32 val storeDataIn = Flipped(Valid(new StoreDataBundle)) // src2 from rs 33 val out = Decoupled(new ExuOutput) 34 val dcache = new DCacheWordIOWithVaddr 35 val dtlb = new TlbRequestIO 36 val pmpResp = Flipped(new PMPRespBundle()) 37 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 38 val flush_sbuffer = new SbufferFlushBundle 39 val feedbackSlow = ValidIO(new RSFeedback) 40 val redirect = Flipped(ValidIO(new Redirect)) 41 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 42 }) 43 44 //------------------------------------------------------- 45 // Atomics Memory Accsess FSM 46 //------------------------------------------------------- 47 val s_invalid :: s_tlb :: s_pm :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(8) 48 val state = RegInit(s_invalid) 49 val data_valid = RegInit(false.B) 50 val in = Reg(new ExuInput()) 51 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 52 val atom_override_xtval = RegInit(false.B) 53 // paddr after translation 54 val paddr = Reg(UInt()) 55 val is_mmio = Reg(Bool()) 56 // dcache response data 57 val resp_data = Reg(UInt()) 58 val resp_data_wire = WireInit(0.U) 59 val is_lrsc_valid = Reg(Bool()) 60 61 // Difftest signals 62 val paddr_reg = Reg(UInt(64.W)) 63 val data_reg = Reg(UInt(64.W)) 64 val mask_reg = Reg(UInt(8.W)) 65 val fuop_reg = Reg(UInt(8.W)) 66 67 io.exceptionAddr.valid := atom_override_xtval 68 io.exceptionAddr.bits := in.src(0) 69 70 // assign default value to output signals 71 io.in.ready := false.B 72 io.out.valid := false.B 73 io.out.bits := DontCare 74 75 io.dcache.req.valid := false.B 76 io.dcache.req.bits := DontCare 77 io.dcache.resp.ready := false.B 78 79 io.dtlb.req.valid := false.B 80 io.dtlb.req.bits := DontCare 81 io.dtlb.resp.ready := false.B 82 83 io.flush_sbuffer.valid := false.B 84 85 XSDebug("state: %d\n", state) 86 87 when (state === s_invalid) { 88 io.in.ready := true.B 89 when (io.in.fire()) { 90 in := io.in.bits 91 in.src(1) := in.src(1) // leave src2 unchanged 92 state := s_tlb 93 } 94 } 95 96 when (io.storeDataIn.fire()) { 97 in.src(1) := io.storeDataIn.bits.data 98 data_valid := true.B 99 } 100 101 assert(!(io.storeDataIn.fire() && data_valid), "atomic unit re-receive data") 102 103 // Send TLB feedback to store issue queue 104 // we send feedback right after we receives request 105 // also, we always treat amo as tlb hit 106 // since we will continue polling tlb all by ourself 107 io.feedbackSlow.valid := RegNext(RegNext(io.in.valid)) 108 io.feedbackSlow.bits.hit := true.B 109 io.feedbackSlow.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 110 io.feedbackSlow.bits.flushState := DontCare 111 io.feedbackSlow.bits.sourceType := DontCare 112 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 113 114 // tlb translation, manipulating signals && deal with exception 115 when (state === s_tlb) { 116 // send req to dtlb 117 // keep firing until tlb hit 118 io.dtlb.req.valid := true.B 119 io.dtlb.req.bits.vaddr := in.src(0) 120 io.dtlb.req.bits.robIdx := in.uop.robIdx 121 io.dtlb.resp.ready := true.B 122 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 123 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 124 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 125 io.dtlb.req.bits.debug.isFirstIssue := false.B 126 127 when(io.dtlb.resp.fire){ 128 paddr := io.dtlb.resp.bits.paddr 129 // exception handling 130 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 131 "b00".U -> true.B, //b 132 "b01".U -> (in.src(0)(0) === 0.U), //h 133 "b10".U -> (in.src(0)(1,0) === 0.U), //w 134 "b11".U -> (in.src(0)(2,0) === 0.U) //d 135 )) 136 exceptionVec(storeAddrMisaligned) := !addrAligned 137 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 138 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 139 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 140 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 141 142 when (!io.dtlb.resp.bits.miss) { 143 when (!addrAligned) { 144 // NOTE: when addrAligned, do not need to wait tlb actually 145 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 146 // if there are exceptions, no need to execute it 147 state := s_finish 148 atom_override_xtval := true.B 149 } .otherwise { 150 state := s_pm 151 } 152 } 153 } 154 } 155 156 when (state === s_pm) { 157 is_mmio := io.pmpResp.mmio 158 // NOTE: only handle load/store exception here, if other exception happens, don't send here 159 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 160 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 161 val exception_pa = io.pmpResp.st 162 when (exception_va || exception_pa) { 163 state := s_finish 164 atom_override_xtval := true.B 165 }.otherwise { 166 state := s_flush_sbuffer_req 167 } 168 } 169 170 when (state === s_flush_sbuffer_req) { 171 io.flush_sbuffer.valid := true.B 172 state := s_flush_sbuffer_resp 173 } 174 175 when (state === s_flush_sbuffer_resp) { 176 when (io.flush_sbuffer.empty) { 177 state := s_cache_req 178 } 179 } 180 181 when (state === s_cache_req) { 182 io.dcache.req.valid := true.B 183 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 184 LSUOpType.lr_w -> M_XLR, 185 LSUOpType.sc_w -> M_XSC, 186 LSUOpType.amoswap_w -> M_XA_SWAP, 187 LSUOpType.amoadd_w -> M_XA_ADD, 188 LSUOpType.amoxor_w -> M_XA_XOR, 189 LSUOpType.amoand_w -> M_XA_AND, 190 LSUOpType.amoor_w -> M_XA_OR, 191 LSUOpType.amomin_w -> M_XA_MIN, 192 LSUOpType.amomax_w -> M_XA_MAX, 193 LSUOpType.amominu_w -> M_XA_MINU, 194 LSUOpType.amomaxu_w -> M_XA_MAXU, 195 196 LSUOpType.lr_d -> M_XLR, 197 LSUOpType.sc_d -> M_XSC, 198 LSUOpType.amoswap_d -> M_XA_SWAP, 199 LSUOpType.amoadd_d -> M_XA_ADD, 200 LSUOpType.amoxor_d -> M_XA_XOR, 201 LSUOpType.amoand_d -> M_XA_AND, 202 LSUOpType.amoor_d -> M_XA_OR, 203 LSUOpType.amomin_d -> M_XA_MIN, 204 LSUOpType.amomax_d -> M_XA_MAX, 205 LSUOpType.amominu_d -> M_XA_MINU, 206 LSUOpType.amomaxu_d -> M_XA_MAXU 207 )) 208 209 io.dcache.req.bits.addr := paddr 210 io.dcache.req.bits.vaddr := in.src(0) // vaddr 211 io.dcache.req.bits.data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 212 // TODO: atomics do need mask: fix mask 213 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 214 io.dcache.req.bits.id := DontCare 215 216 when(io.dcache.req.fire()){ 217 state := s_cache_resp 218 paddr_reg := io.dcache.req.bits.addr 219 data_reg := io.dcache.req.bits.data 220 mask_reg := io.dcache.req.bits.mask 221 fuop_reg := in.uop.ctrl.fuOpType 222 } 223 } 224 225 when (state === s_cache_resp) { 226 io.dcache.resp.ready := data_valid 227 when(io.dcache.resp.fire()) { 228 is_lrsc_valid := io.dcache.resp.bits.id 229 val rdata = io.dcache.resp.bits.data 230 val rdataSel = LookupTree(paddr(2, 0), List( 231 "b000".U -> rdata(63, 0), 232 "b001".U -> rdata(63, 8), 233 "b010".U -> rdata(63, 16), 234 "b011".U -> rdata(63, 24), 235 "b100".U -> rdata(63, 32), 236 "b101".U -> rdata(63, 40), 237 "b110".U -> rdata(63, 48), 238 "b111".U -> rdata(63, 56) 239 )) 240 241 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 242 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 243 LSUOpType.sc_w -> rdata, 244 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 245 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 246 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 247 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 248 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 249 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 250 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 251 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 252 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 253 254 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 255 LSUOpType.sc_d -> rdata, 256 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 257 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 258 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 259 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 260 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 261 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 262 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 263 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 264 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 265 )) 266 267 resp_data := resp_data_wire 268 state := s_finish 269 } 270 } 271 272 when (state === s_finish) { 273 io.out.valid := true.B 274 io.out.bits.uop := in.uop 275 io.out.bits.uop.cf.exceptionVec := exceptionVec 276 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 277 io.out.bits.data := resp_data 278 io.out.bits.redirectValid := false.B 279 io.out.bits.redirect := DontCare 280 io.out.bits.debug.isMMIO := is_mmio 281 io.out.bits.debug.paddr := paddr 282 when (io.out.fire()) { 283 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 284 state := s_invalid 285 } 286 data_valid := false.B 287 } 288 289 when (io.redirect.valid) { 290 atom_override_xtval := false.B 291 } 292 293 if (env.EnableDifftest) { 294 val difftest = Module(new DifftestAtomicEvent) 295 difftest.io.clock := clock 296 difftest.io.coreid := hardId.U 297 difftest.io.atomicResp := io.dcache.resp.fire() 298 difftest.io.atomicAddr := paddr_reg 299 difftest.io.atomicData := data_reg 300 difftest.io.atomicMask := mask_reg 301 difftest.io.atomicFuop := fuop_reg 302 difftest.io.atomicOut := resp_data_wire 303 } 304} 305