1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8import xiangshan.cache.{DCacheWordIO, DCacheLineIO, TlbRequestIO, MemoryOpConstants} 9import xiangshan.backend.LSUOpType 10import xiangshan.mem._ 11import xiangshan.backend.roq.RoqPtr 12import xiangshan.backend.fu.fpu.boxF32ToF64 13 14 15class LqPtr extends CircularQueuePtr(LqPtr.LoadQueueSize) { } 16 17object LqPtr extends HasXSParameter { 18 def apply(f: Bool, v: UInt): LqPtr = { 19 val ptr = Wire(new LqPtr) 20 ptr.flag := f 21 ptr.value := v 22 ptr 23 } 24} 25 26class LqEnqIO extends XSBundle { 27 val canAccept = Output(Bool()) 28 val sqCanAccept = Input(Bool()) 29 val needAlloc = Vec(RenameWidth, Input(Bool())) 30 val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp))) 31 val resp = Vec(RenameWidth, Output(new LqPtr)) 32} 33 34// Load Queue 35class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueuePtrHelper { 36 val io = IO(new Bundle() { 37 val enq = new LqEnqIO 38 val brqRedirect = Input(Valid(new Redirect)) 39 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 40 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // FIXME: Valid() only 41 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback load 42 val load_s1 = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO)) 43 val commits = Flipped(new RoqCommitIO) 44 val rollback = Output(Valid(new Redirect)) // replay now starts from load instead of store 45 val dcache = new DCacheLineIO 46 val uncache = new DCacheWordIO 47 val roqDeqPtr = Input(new RoqPtr) 48 val exceptionAddr = new ExceptionAddrIO 49 }) 50 51 val uop = Reg(Vec(LoadQueueSize, new MicroOp)) 52 // val data = Reg(Vec(LoadQueueSize, new LsRoqEntry)) 53 val dataModule = Module(new LSQueueData(LoadQueueSize, LoadPipelineWidth)) 54 dataModule.io := DontCare 55 val allocated = RegInit(VecInit(List.fill(LoadQueueSize)(false.B))) // lq entry has been allocated 56 val datavalid = RegInit(VecInit(List.fill(LoadQueueSize)(false.B))) // data is valid 57 val writebacked = RegInit(VecInit(List.fill(LoadQueueSize)(false.B))) // inst has been writebacked to CDB 58 val commited = Reg(Vec(LoadQueueSize, Bool())) // inst has been writebacked to CDB 59 val miss = Reg(Vec(LoadQueueSize, Bool())) // load inst missed, waiting for miss queue to accept miss request 60 val listening = Reg(Vec(LoadQueueSize, Bool())) // waiting for refill result 61 val pending = Reg(Vec(LoadQueueSize, Bool())) // mmio pending: inst is an mmio inst, it will not be executed until it reachs the end of roq 62 63 val enqPtrExt = RegInit(VecInit((0 until RenameWidth).map(_.U.asTypeOf(new LqPtr)))) 64 val deqPtrExt = RegInit(0.U.asTypeOf(new LqPtr)) 65 val enqPtr = enqPtrExt(0).value 66 val deqPtr = deqPtrExt.value 67 val sameFlag = enqPtrExt(0).flag === deqPtrExt.flag 68 val isEmpty = enqPtr === deqPtr && sameFlag 69 val isFull = enqPtr === deqPtr && !sameFlag 70 val allowIn = !isFull 71 72 val loadCommit = (0 until CommitWidth).map(i => io.commits.valid(i) && !io.commits.isWalk && io.commits.info(i).commitType === CommitType.LOAD) 73 val mcommitIdx = (0 until CommitWidth).map(i => io.commits.info(i).lqIdx.value) 74 75 val deqMask = UIntToMask(deqPtr, LoadQueueSize) 76 val enqMask = UIntToMask(enqPtr, LoadQueueSize) 77 78 /** 79 * Enqueue at dispatch 80 * 81 * Currently, LoadQueue only allows enqueue when #emptyEntries > RenameWidth(EnqWidth) 82 */ 83 val validEntries = distanceBetween(enqPtrExt(0), deqPtrExt) 84 val firedDispatch = io.enq.req.map(_.valid) 85 io.enq.canAccept := validEntries <= (LoadQueueSize - RenameWidth).U 86 XSDebug(p"(ready, valid): ${io.enq.canAccept}, ${Binary(Cat(firedDispatch))}\n") 87 for (i <- 0 until RenameWidth) { 88 val offset = if (i == 0) 0.U else PopCount(io.enq.needAlloc.take(i)) 89 val lqIdx = enqPtrExt(offset) 90 val index = lqIdx.value 91 when (io.enq.req(i).valid && io.enq.canAccept && io.enq.sqCanAccept && !io.brqRedirect.valid) { 92 uop(index) := io.enq.req(i).bits 93 allocated(index) := true.B 94 datavalid(index) := false.B 95 writebacked(index) := false.B 96 commited(index) := false.B 97 miss(index) := false.B 98 listening(index) := false.B 99 pending(index) := false.B 100 } 101 io.enq.resp(i) := lqIdx 102 } 103 104 // when io.brqRedirect.valid, we don't allow eneuque even though it may fire. 105 when (Cat(firedDispatch).orR && io.enq.canAccept && io.enq.sqCanAccept && !io.brqRedirect.valid) { 106 val enqNumber = PopCount(firedDispatch) 107 enqPtrExt := VecInit(enqPtrExt.map(_ + enqNumber)) 108 XSInfo("dispatched %d insts to lq\n", enqNumber) 109 } 110 111 /** 112 * Writeback load from load units 113 * 114 * Most load instructions writeback to regfile at the same time. 115 * However, 116 * (1) For an mmio instruction with exceptions, it writes back to ROB immediately. 117 * (2) For an mmio instruction without exceptions, it does not write back. 118 * The mmio instruction will be sent to lower level when it reaches ROB's head. 119 * After uncache response, it will write back through arbiter with loadUnit. 120 * (3) For cache misses, it is marked miss and sent to dcache later. 121 * After cache refills, it will write back through arbiter with loadUnit. 122 */ 123 for (i <- 0 until LoadPipelineWidth) { 124 dataModule.io.wb(i).wen := false.B 125 when(io.loadIn(i).fire()) { 126 when(io.loadIn(i).bits.miss) { 127 XSInfo(io.loadIn(i).valid, "load miss write to lq idx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x exc %x\n", 128 io.loadIn(i).bits.uop.lqIdx.asUInt, 129 io.loadIn(i).bits.uop.cf.pc, 130 io.loadIn(i).bits.vaddr, 131 io.loadIn(i).bits.paddr, 132 io.loadIn(i).bits.data, 133 io.loadIn(i).bits.mask, 134 io.loadIn(i).bits.forwardData.asUInt, 135 io.loadIn(i).bits.forwardMask.asUInt, 136 io.loadIn(i).bits.mmio, 137 io.loadIn(i).bits.rollback, 138 io.loadIn(i).bits.uop.cf.exceptionVec.asUInt 139 ) 140 }.otherwise { 141 XSInfo(io.loadIn(i).valid, "load hit write to cbd lqidx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x exc %x\n", 142 io.loadIn(i).bits.uop.lqIdx.asUInt, 143 io.loadIn(i).bits.uop.cf.pc, 144 io.loadIn(i).bits.vaddr, 145 io.loadIn(i).bits.paddr, 146 io.loadIn(i).bits.data, 147 io.loadIn(i).bits.mask, 148 io.loadIn(i).bits.forwardData.asUInt, 149 io.loadIn(i).bits.forwardMask.asUInt, 150 io.loadIn(i).bits.mmio, 151 io.loadIn(i).bits.rollback, 152 io.loadIn(i).bits.uop.cf.exceptionVec.asUInt 153 ) 154 } 155 val loadWbIndex = io.loadIn(i).bits.uop.lqIdx.value 156 datavalid(loadWbIndex) := !io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio 157 writebacked(loadWbIndex) := !io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio 158 159 val loadWbData = Wire(new LsqEntry) 160 loadWbData.paddr := io.loadIn(i).bits.paddr 161 loadWbData.vaddr := io.loadIn(i).bits.vaddr 162 loadWbData.mask := io.loadIn(i).bits.mask 163 loadWbData.data := io.loadIn(i).bits.data // for mmio / misc / debug 164 loadWbData.mmio := io.loadIn(i).bits.mmio 165 loadWbData.fwdMask := io.loadIn(i).bits.forwardMask 166 loadWbData.fwdData := io.loadIn(i).bits.forwardData 167 loadWbData.exception := io.loadIn(i).bits.uop.cf.exceptionVec.asUInt 168 dataModule.io.wbWrite(i, loadWbIndex, loadWbData) 169 dataModule.io.wb(i).wen := true.B 170 171 val dcacheMissed = io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio 172 miss(loadWbIndex) := dcacheMissed && !io.loadIn(i).bits.uop.cf.exceptionVec.asUInt.orR 173 listening(loadWbIndex) := dcacheMissed 174 pending(loadWbIndex) := io.loadIn(i).bits.mmio && !io.loadIn(i).bits.uop.cf.exceptionVec.asUInt.orR 175 } 176 } 177 178 /** 179 * Cache miss request 180 * 181 * (1) writeback: miss 182 * (2) send to dcache: listing 183 * (3) dcache response: datavalid 184 * (4) writeback to ROB: writeback 185 */ 186 val inflightReqs = RegInit(VecInit(Seq.fill(cfg.nLoadMissEntries)(0.U.asTypeOf(new InflightBlockInfo)))) 187 val inflightReqFull = inflightReqs.map(req => req.valid).reduce(_&&_) 188 val reqBlockIndex = PriorityEncoder(~VecInit(inflightReqs.map(req => req.valid)).asUInt) 189 190 val missRefillSelVec = VecInit( 191 (0 until LoadQueueSize).map{ i => 192 val inflight = inflightReqs.map(req => req.valid && req.block_addr === get_block_addr(dataModule.io.rdata(i).paddr)).reduce(_||_) 193 allocated(i) && miss(i) && !inflight 194 }) 195 196 val missRefillSel = getFirstOne(missRefillSelVec, deqMask) 197 val missRefillBlockAddr = get_block_addr(dataModule.io.rdata(missRefillSel).paddr) 198 io.dcache.req.valid := missRefillSelVec.asUInt.orR 199 io.dcache.req.bits.cmd := MemoryOpConstants.M_XRD 200 io.dcache.req.bits.addr := missRefillBlockAddr 201 io.dcache.req.bits.data := DontCare 202 io.dcache.req.bits.mask := DontCare 203 204 io.dcache.req.bits.meta.id := DontCare 205 io.dcache.req.bits.meta.vaddr := DontCare // dataModule.io.rdata(missRefillSel).vaddr 206 io.dcache.req.bits.meta.paddr := missRefillBlockAddr 207 io.dcache.req.bits.meta.uop := uop(missRefillSel) 208 io.dcache.req.bits.meta.mmio := false.B // dataModule.io.rdata(missRefillSel).mmio 209 io.dcache.req.bits.meta.tlb_miss := false.B 210 io.dcache.req.bits.meta.mask := DontCare 211 io.dcache.req.bits.meta.replay := false.B 212 213 io.dcache.resp.ready := true.B 214 215 assert(!(dataModule.io.rdata(missRefillSel).mmio && io.dcache.req.valid)) 216 217 when(io.dcache.req.fire()) { 218 miss(missRefillSel) := false.B 219 listening(missRefillSel) := true.B 220 221 // mark this block as inflight 222 inflightReqs(reqBlockIndex).valid := true.B 223 inflightReqs(reqBlockIndex).block_addr := missRefillBlockAddr 224 assert(!inflightReqs(reqBlockIndex).valid) 225 } 226 227 when(io.dcache.resp.fire()) { 228 val inflight = inflightReqs.map(req => req.valid && req.block_addr === get_block_addr(io.dcache.resp.bits.meta.paddr)).reduce(_||_) 229 assert(inflight) 230 for (i <- 0 until cfg.nLoadMissEntries) { 231 when (inflightReqs(i).valid && inflightReqs(i).block_addr === get_block_addr(io.dcache.resp.bits.meta.paddr)) { 232 inflightReqs(i).valid := false.B 233 } 234 } 235 } 236 237 238 when(io.dcache.req.fire()){ 239 XSDebug("miss req: pc:0x%x roqIdx:%d lqIdx:%d (p)addr:0x%x vaddr:0x%x\n", 240 io.dcache.req.bits.meta.uop.cf.pc, io.dcache.req.bits.meta.uop.roqIdx.asUInt, io.dcache.req.bits.meta.uop.lqIdx.asUInt, 241 io.dcache.req.bits.addr, io.dcache.req.bits.meta.vaddr 242 ) 243 } 244 245 when(io.dcache.resp.fire()){ 246 XSDebug("miss resp: pc:0x%x roqIdx:%d lqIdx:%d (p)addr:0x%x data %x\n", 247 io.dcache.resp.bits.meta.uop.cf.pc, io.dcache.resp.bits.meta.uop.roqIdx.asUInt, io.dcache.resp.bits.meta.uop.lqIdx.asUInt, 248 io.dcache.resp.bits.meta.paddr, io.dcache.resp.bits.data 249 ) 250 } 251 252 // Refill 64 bit in a cycle 253 // Refill data comes back from io.dcache.resp 254 dataModule.io.refill.dcache := io.dcache.resp.bits 255 256 (0 until LoadQueueSize).map(i => { 257 val blockMatch = get_block_addr(dataModule.io.rdata(i).paddr) === io.dcache.resp.bits.meta.paddr 258 dataModule.io.refill.wen(i) := false.B 259 when(allocated(i) && listening(i) && blockMatch && io.dcache.resp.fire()) { 260 dataModule.io.refill.wen(i) := true.B 261 datavalid(i) := true.B 262 listening(i) := false.B 263 } 264 }) 265 266 // writeback up to 2 missed load insts to CDB 267 // just randomly pick 2 missed load (data refilled), write them back to cdb 268 val loadWbSelVec = VecInit((0 until LoadQueueSize).map(i => { 269 allocated(i) && datavalid(i) && !writebacked(i) 270 })).asUInt() // use uint instead vec to reduce verilog lines 271 val loadWbSel = Wire(Vec(StorePipelineWidth, UInt(log2Up(LoadQueueSize).W))) 272 val loadWbSelV= Wire(Vec(StorePipelineWidth, Bool())) 273 val lselvec0 = PriorityEncoderOH(loadWbSelVec) 274 val lselvec1 = PriorityEncoderOH(loadWbSelVec & (~lselvec0).asUInt) 275 loadWbSel(0) := OHToUInt(lselvec0) 276 loadWbSelV(0):= lselvec0.orR 277 loadWbSel(1) := OHToUInt(lselvec1) 278 loadWbSelV(1) := lselvec1.orR 279 (0 until StorePipelineWidth).map(i => { 280 // data select 281 val rdata = dataModule.io.rdata(loadWbSel(i)).data 282 val func = uop(loadWbSel(i)).ctrl.fuOpType 283 val raddr = dataModule.io.rdata(loadWbSel(i)).paddr 284 val rdataSel = LookupTree(raddr(2, 0), List( 285 "b000".U -> rdata(63, 0), 286 "b001".U -> rdata(63, 8), 287 "b010".U -> rdata(63, 16), 288 "b011".U -> rdata(63, 24), 289 "b100".U -> rdata(63, 32), 290 "b101".U -> rdata(63, 40), 291 "b110".U -> rdata(63, 48), 292 "b111".U -> rdata(63, 56) 293 )) 294 val rdataPartialLoad = LookupTree(func, List( 295 LSUOpType.lb -> SignExt(rdataSel(7, 0) , XLEN), 296 LSUOpType.lh -> SignExt(rdataSel(15, 0), XLEN), 297 LSUOpType.lw -> SignExt(rdataSel(31, 0), XLEN), 298 LSUOpType.ld -> SignExt(rdataSel(63, 0), XLEN), 299 LSUOpType.lbu -> ZeroExt(rdataSel(7, 0) , XLEN), 300 LSUOpType.lhu -> ZeroExt(rdataSel(15, 0), XLEN), 301 LSUOpType.lwu -> ZeroExt(rdataSel(31, 0), XLEN), 302 LSUOpType.flw -> boxF32ToF64(rdataSel(31, 0)) 303 )) 304 io.ldout(i).bits.uop := uop(loadWbSel(i)) 305 io.ldout(i).bits.uop.cf.exceptionVec := dataModule.io.rdata(loadWbSel(i)).exception.asBools 306 io.ldout(i).bits.uop.lqIdx := loadWbSel(i).asTypeOf(new LqPtr) 307 io.ldout(i).bits.data := rdataPartialLoad 308 io.ldout(i).bits.redirectValid := false.B 309 io.ldout(i).bits.redirect := DontCare 310 io.ldout(i).bits.brUpdate := DontCare 311 io.ldout(i).bits.debug.isMMIO := dataModule.io.rdata(loadWbSel(i)).mmio 312 io.ldout(i).bits.fflags := DontCare 313 io.ldout(i).valid := loadWbSelVec(loadWbSel(i)) && loadWbSelV(i) 314 when(io.ldout(i).fire()) { 315 writebacked(loadWbSel(i)) := true.B 316 XSInfo("load miss write to cbd roqidx %d lqidx %d pc 0x%x paddr %x data %x mmio %x\n", 317 io.ldout(i).bits.uop.roqIdx.asUInt, 318 io.ldout(i).bits.uop.lqIdx.asUInt, 319 io.ldout(i).bits.uop.cf.pc, 320 dataModule.io.rdata(loadWbSel(i)).paddr, 321 dataModule.io.rdata(loadWbSel(i)).data, 322 dataModule.io.rdata(loadWbSel(i)).mmio 323 ) 324 } 325 }) 326 327 /** 328 * Load commits 329 * 330 * When load commited, mark it as !allocated and move deqPtrExt forward. 331 */ 332 (0 until CommitWidth).map(i => { 333 when(loadCommit(i)) { 334 allocated(mcommitIdx(i)) := false.B 335 XSDebug("load commit %d: idx %d %x\n", i.U, mcommitIdx(i), uop(mcommitIdx(i)).cf.pc) 336 } 337 }) 338 deqPtrExt := deqPtrExt + PopCount(loadCommit) 339 340 def getFirstOne(mask: Vec[Bool], startMask: UInt) = { 341 val length = mask.length 342 val highBits = (0 until length).map(i => mask(i) & ~startMask(i)) 343 val highBitsUint = Cat(highBits.reverse) 344 PriorityEncoder(Mux(highBitsUint.orR(), highBitsUint, mask.asUInt)) 345 } 346 347 def getOldestInTwo(valid: Seq[Bool], uop: Seq[MicroOp]) = { 348 assert(valid.length == uop.length) 349 assert(valid.length == 2) 350 Mux(valid(0) && valid(1), 351 Mux(isAfter(uop(0).roqIdx, uop(1).roqIdx), uop(1), uop(0)), 352 Mux(valid(0) && !valid(1), uop(0), uop(1))) 353 } 354 355 def getAfterMask(valid: Seq[Bool], uop: Seq[MicroOp]) = { 356 assert(valid.length == uop.length) 357 val length = valid.length 358 (0 until length).map(i => { 359 (0 until length).map(j => { 360 Mux(valid(i) && valid(j), 361 isAfter(uop(i).roqIdx, uop(j).roqIdx), 362 Mux(!valid(i), true.B, false.B)) 363 }) 364 }) 365 } 366 367 /** 368 * Memory violation detection 369 * 370 * When store writes back, it searches LoadQueue for younger load instructions 371 * with the same load physical address. They loaded wrong data and need re-execution. 372 * 373 * Cycle 0: Store Writeback 374 * Generate match vector for store address with rangeMask(stPtr, enqPtr). 375 * Besides, load instructions in LoadUnit_S1 and S2 are also checked. 376 * Cycle 1: Redirect Generation 377 * There're three possible types of violations. Choose the oldest load. 378 * Set io.redirect according to the detected violation. 379 */ 380 io.load_s1 := DontCare 381 def detectRollback(i: Int) = { 382 val startIndex = io.storeIn(i).bits.uop.lqIdx.value 383 val lqIdxMask = UIntToMask(startIndex, LoadQueueSize) 384 val xorMask = lqIdxMask ^ enqMask 385 val sameFlag = io.storeIn(i).bits.uop.lqIdx.flag === enqPtrExt(0).flag 386 val toEnqPtrMask = Mux(sameFlag, xorMask, ~xorMask) 387 388 // check if load already in lq needs to be rolledback 389 val lqViolationVec = RegNext(VecInit((0 until LoadQueueSize).map(j => { 390 val addrMatch = allocated(j) && 391 io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === dataModule.io.rdata(j).paddr(PAddrBits - 1, 3) 392 val entryNeedCheck = toEnqPtrMask(j) && addrMatch && (datavalid(j) || listening(j) || miss(j)) 393 // TODO: update refilled data 394 val violationVec = (0 until 8).map(k => dataModule.io.rdata(j).mask(k) && io.storeIn(i).bits.mask(k)) 395 Cat(violationVec).orR() && entryNeedCheck 396 }))) 397 val lqViolation = lqViolationVec.asUInt().orR() 398 val lqViolationIndex = getFirstOne(lqViolationVec, RegNext(lqIdxMask)) 399 val lqViolationUop = uop(lqViolationIndex) 400 // lqViolationUop.lqIdx.flag := deqMask(lqViolationIndex) ^ deqPtrExt.flag 401 // lqViolationUop.lqIdx.value := lqViolationIndex 402 XSDebug(lqViolation, p"${Binary(Cat(lqViolationVec))}, $startIndex, $lqViolationIndex\n") 403 404 // when l/s writeback to roq together, check if rollback is needed 405 val wbViolationVec = RegNext(VecInit((0 until LoadPipelineWidth).map(j => { 406 io.loadIn(j).valid && 407 isAfter(io.loadIn(j).bits.uop.roqIdx, io.storeIn(i).bits.uop.roqIdx) && 408 io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === io.loadIn(j).bits.paddr(PAddrBits - 1, 3) && 409 (io.storeIn(i).bits.mask & io.loadIn(j).bits.mask).orR 410 }))) 411 val wbViolation = wbViolationVec.asUInt().orR() 412 val wbViolationUop = getOldestInTwo(wbViolationVec, RegNext(VecInit(io.loadIn.map(_.bits.uop)))) 413 XSDebug(wbViolation, p"${Binary(Cat(wbViolationVec))}, $wbViolationUop\n") 414 415 // check if rollback is needed for load in l1 416 val l1ViolationVec = RegNext(VecInit((0 until LoadPipelineWidth).map(j => { 417 io.load_s1(j).valid && // L1 valid 418 isAfter(io.load_s1(j).uop.roqIdx, io.storeIn(i).bits.uop.roqIdx) && 419 io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === io.load_s1(j).paddr(PAddrBits - 1, 3) && 420 (io.storeIn(i).bits.mask & io.load_s1(j).mask).orR 421 }))) 422 val l1Violation = l1ViolationVec.asUInt().orR() 423 val l1ViolationUop = getOldestInTwo(l1ViolationVec, RegNext(VecInit(io.load_s1.map(_.uop)))) 424 XSDebug(l1Violation, p"${Binary(Cat(l1ViolationVec))}, $l1ViolationUop\n") 425 426 val rollbackValidVec = Seq(lqViolation, wbViolation, l1Violation) 427 val rollbackUopVec = Seq(lqViolationUop, wbViolationUop, l1ViolationUop) 428 429 val mask = getAfterMask(rollbackValidVec, rollbackUopVec) 430 val oneAfterZero = mask(1)(0) 431 val rollbackUop = Mux(oneAfterZero && mask(2)(0), 432 rollbackUopVec(0), 433 Mux(!oneAfterZero && mask(2)(1), rollbackUopVec(1), rollbackUopVec(2))) 434 435 XSDebug( 436 l1Violation, 437 "need rollback (l4 load) pc %x roqidx %d target %x\n", 438 io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, l1ViolationUop.roqIdx.asUInt 439 ) 440 XSDebug( 441 lqViolation, 442 "need rollback (ld wb before store) pc %x roqidx %d target %x\n", 443 io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, lqViolationUop.roqIdx.asUInt 444 ) 445 XSDebug( 446 wbViolation, 447 "need rollback (ld/st wb together) pc %x roqidx %d target %x\n", 448 io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, wbViolationUop.roqIdx.asUInt 449 ) 450 451 (RegNext(io.storeIn(i).valid) && Cat(rollbackValidVec).orR, rollbackUop) 452 } 453 454 // rollback check 455 val rollback = Wire(Vec(StorePipelineWidth, Valid(new MicroOp))) 456 for (i <- 0 until StorePipelineWidth) { 457 val detectedRollback = detectRollback(i) 458 rollback(i).valid := detectedRollback._1 459 rollback(i).bits := detectedRollback._2 460 } 461 462 def rollbackSel(a: Valid[MicroOp], b: Valid[MicroOp]): ValidIO[MicroOp] = { 463 Mux( 464 a.valid, 465 Mux( 466 b.valid, 467 Mux(isAfter(a.bits.roqIdx, b.bits.roqIdx), b, a), // a,b both valid, sel oldest 468 a // sel a 469 ), 470 b // sel b 471 ) 472 } 473 474 val rollbackSelected = ParallelOperation(rollback, rollbackSel) 475 val lastCycleRedirect = RegNext(io.brqRedirect) 476 477 // Note that we use roqIdx - 1.U to flush the load instruction itself. 478 // Thus, here if last cycle's roqIdx equals to this cycle's roqIdx, it still triggers the redirect. 479 io.rollback.valid := rollbackSelected.valid && 480 (!lastCycleRedirect.valid || !isAfter(rollbackSelected.bits.roqIdx, lastCycleRedirect.bits.roqIdx)) && 481 !(lastCycleRedirect.valid && (lastCycleRedirect.bits.isFlushPipe || lastCycleRedirect.bits.isException)) 482 483 io.rollback.bits.roqIdx := rollbackSelected.bits.roqIdx - 1.U 484 io.rollback.bits.isReplay := true.B 485 io.rollback.bits.isMisPred := false.B 486 io.rollback.bits.isException := false.B 487 io.rollback.bits.isFlushPipe := false.B 488 io.rollback.bits.pc := DontCare 489 io.rollback.bits.target := rollbackSelected.bits.cf.pc 490 io.rollback.bits.brTag := rollbackSelected.bits.brTag 491 492 when(io.rollback.valid) { 493 XSDebug("Mem rollback: pc %x roqidx %d\n", io.rollback.bits.pc, io.rollback.bits.roqIdx.asUInt) 494 } 495 496 /** 497 * Memory mapped IO / other uncached operations 498 * 499 */ 500 io.uncache.req.valid := pending(deqPtr) && allocated(deqPtr) && 501 io.commits.info(0).commitType === CommitType.LOAD && 502 io.roqDeqPtr === uop(deqPtr).roqIdx && 503 !io.commits.isWalk 504 505 io.uncache.req.bits.cmd := MemoryOpConstants.M_XRD 506 io.uncache.req.bits.addr := dataModule.io.rdata(deqPtr).paddr 507 io.uncache.req.bits.data := dataModule.io.rdata(deqPtr).data 508 io.uncache.req.bits.mask := dataModule.io.rdata(deqPtr).mask 509 510 io.uncache.req.bits.meta.id := DontCare 511 io.uncache.req.bits.meta.vaddr := DontCare 512 io.uncache.req.bits.meta.paddr := dataModule.io.rdata(deqPtr).paddr 513 io.uncache.req.bits.meta.uop := uop(deqPtr) 514 io.uncache.req.bits.meta.mmio := true.B 515 io.uncache.req.bits.meta.tlb_miss := false.B 516 io.uncache.req.bits.meta.mask := dataModule.io.rdata(deqPtr).mask 517 io.uncache.req.bits.meta.replay := false.B 518 519 io.uncache.resp.ready := true.B 520 521 when (io.uncache.req.fire()) { 522 pending(deqPtr) := false.B 523 524 XSDebug("uncache req: pc %x addr %x data %x op %x mask %x\n", 525 uop(deqPtr).cf.pc, 526 io.uncache.req.bits.addr, 527 io.uncache.req.bits.data, 528 io.uncache.req.bits.cmd, 529 io.uncache.req.bits.mask 530 ) 531 } 532 533 dataModule.io.uncache.wen := false.B 534 when(io.uncache.resp.fire()){ 535 datavalid(deqPtr) := true.B 536 dataModule.io.uncacheWrite(deqPtr, io.uncache.resp.bits.data(XLEN-1, 0)) 537 dataModule.io.uncache.wen := true.B 538 539 XSDebug("uncache resp: data %x\n", io.dcache.resp.bits.data) 540 } 541 542 // Read vaddr for mem exception 543 io.exceptionAddr.vaddr := dataModule.io.rdata(io.exceptionAddr.lsIdx.lqIdx.value).vaddr 544 545 // misprediction recovery / exception redirect 546 // invalidate lq term using robIdx 547 val needCancel = Wire(Vec(LoadQueueSize, Bool())) 548 for (i <- 0 until LoadQueueSize) { 549 needCancel(i) := uop(i).roqIdx.needFlush(io.brqRedirect) && allocated(i) && !commited(i) 550 when (needCancel(i)) { 551 allocated(i) := false.B 552 } 553 } 554 // we recover the pointers in the next cycle after redirect 555 val needCancelReg = RegNext(needCancel) 556 when (lastCycleRedirect.valid) { 557 val cancelCount = PopCount(needCancelReg) 558 enqPtrExt := VecInit(enqPtrExt.map(_ - cancelCount)) 559 } 560 561 // debug info 562 XSDebug("enqPtrExt %d:%d deqPtrExt %d:%d\n", enqPtrExt(0).flag, enqPtr, deqPtrExt.flag, deqPtr) 563 564 def PrintFlag(flag: Bool, name: String): Unit = { 565 when(flag) { 566 XSDebug(false, true.B, name) 567 }.otherwise { 568 XSDebug(false, true.B, " ") 569 } 570 } 571 572 for (i <- 0 until LoadQueueSize) { 573 if (i % 4 == 0) XSDebug("") 574 XSDebug(false, true.B, "%x [%x] ", uop(i).cf.pc, dataModule.io.rdata(i).paddr) 575 PrintFlag(allocated(i), "a") 576 PrintFlag(allocated(i) && datavalid(i), "v") 577 PrintFlag(allocated(i) && writebacked(i), "w") 578 PrintFlag(allocated(i) && commited(i), "c") 579 PrintFlag(allocated(i) && miss(i), "m") 580 PrintFlag(allocated(i) && listening(i), "l") 581 PrintFlag(allocated(i) && pending(i), "p") 582 XSDebug(false, true.B, " ") 583 if (i % 4 == 3 || i == LoadQueueSize - 1) XSDebug(false, true.B, "\n") 584 } 585 586} 587