1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.fu.FuConfig._ 26import xiangshan.backend.fu.fpu.FPU 27import xiangshan.backend.rob.RobLsqIO 28import xiangshan.cache._ 29import xiangshan.frontend.FtqPtr 30import xiangshan.ExceptionNO._ 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.backend.rob.RobPtr 33import xiangshan.backend.Bundles.{MemExuOutput, DynInst} 34 35class LoadMisalignBuffer(implicit p: Parameters) extends XSModule 36 with HasCircularQueuePtrHelper 37 with HasLoadHelper 38{ 39 private val enqPortNum = LoadPipelineWidth 40 private val maxSplitNum = 2 41 42 require(maxSplitNum == 2) 43 44 private val LB = "b00".U(2.W) 45 private val LH = "b01".U(2.W) 46 private val LW = "b10".U(2.W) 47 private val LD = "b11".U(2.W) 48 49 // encode of how many bytes to shift or truncate 50 private val BYTE0 = "b000".U(3.W) 51 private val BYTE1 = "b001".U(3.W) 52 private val BYTE2 = "b010".U(3.W) 53 private val BYTE3 = "b011".U(3.W) 54 private val BYTE4 = "b100".U(3.W) 55 private val BYTE5 = "b101".U(3.W) 56 private val BYTE6 = "b110".U(3.W) 57 private val BYTE7 = "b111".U(3.W) 58 59 def getMask(sizeEncode: UInt) = LookupTree(sizeEncode, List( 60 LB -> 0x1.U, // lb 61 LH -> 0x3.U, // lh 62 LW -> 0xf.U, // lw 63 LD -> 0xff.U // ld 64 )) 65 66 def getShiftAndTruncateData(shiftEncode: UInt, truncateEncode: UInt, data: UInt) = { 67 val shiftData = LookupTree(shiftEncode, List( 68 BYTE0 -> data(63, 0), 69 BYTE1 -> data(63, 8), 70 BYTE2 -> data(63, 16), 71 BYTE3 -> data(63, 24), 72 BYTE4 -> data(63, 32), 73 BYTE5 -> data(63, 40), 74 BYTE6 -> data(63, 48), 75 BYTE7 -> data(63, 56) 76 )) 77 val truncateData = LookupTree(truncateEncode, List( 78 BYTE0 -> 0.U(XLEN.W), // can not truncate with 0 byte width 79 BYTE1 -> shiftData(7, 0), 80 BYTE2 -> shiftData(15, 0), 81 BYTE3 -> shiftData(23, 0), 82 BYTE4 -> shiftData(31, 0), 83 BYTE5 -> shiftData(39, 0), 84 BYTE6 -> shiftData(47, 0), 85 BYTE7 -> shiftData(55, 0) 86 )) 87 truncateData(XLEN - 1, 0) 88 } 89 90 def selectOldest[T <: LqWriteBundle](valid: Seq[Bool], bits: Seq[T]): (Seq[Bool], Seq[T]) = { 91 assert(valid.length == bits.length) 92 if (valid.length == 0 || valid.length == 1) { 93 (valid, bits) 94 } else if (valid.length == 2) { 95 val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0))))) 96 for (i <- res.indices) { 97 res(i).valid := valid(i) 98 res(i).bits := bits(i) 99 } 100 val oldest = Mux(valid(0) && valid(1), 101 Mux(isAfter(bits(0).uop.robIdx, bits(1).uop.robIdx) || 102 (isNotBefore(bits(0).uop.robIdx, bits(1).uop.robIdx) && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)), 103 Mux(valid(0) && !valid(1), res(0), res(1))) 104 (Seq(oldest.valid), Seq(oldest.bits)) 105 } else { 106 val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2)) 107 val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2))) 108 selectOldest(left._1 ++ right._1, left._2 ++ right._2) 109 } 110 } 111 112 val io = IO(new Bundle() { 113 val redirect = Flipped(Valid(new Redirect)) 114 val req = Vec(enqPortNum, Flipped(Valid(new LqWriteBundle))) 115 val rob = Flipped(new RobLsqIO) 116 val splitLoadReq = Decoupled(new LsPipelineBundle) 117 val splitLoadResp = Flipped(Valid(new LqWriteBundle)) 118 val writeBack = Decoupled(new MemExuOutput) 119 val overwriteExpBuf = Output(new XSBundle { 120 val valid = Bool() 121 val vaddr = UInt(VAddrBits.W) 122 }) 123 val flushLdExpBuff = Output(Bool()) 124 }) 125 126 io.rob.mmio := 0.U.asTypeOf(Vec(LoadPipelineWidth, Bool())) 127 io.rob.uop := 0.U.asTypeOf(Vec(LoadPipelineWidth, new DynInst)) 128 129 val req_valid = RegInit(false.B) 130 val req = Reg(new LqWriteBundle) 131 132 // enqueue 133 // s1: 134 val s1_req = VecInit(io.req.map(_.bits)) 135 val s1_valid = VecInit(io.req.map(x => x.valid)) 136 137 // s2: delay 1 cycle 138 val s2_req = RegNext(s1_req) 139 val s2_valid = (0 until enqPortNum).map(i => 140 RegNext(s1_valid(i)) && 141 !s2_req(i).uop.robIdx.needFlush(RegNext(io.redirect)) && 142 !s2_req(i).uop.robIdx.needFlush(io.redirect) 143 ) 144 val s2_miss_aligned = s2_req.map(x => 145 x.uop.exceptionVec(loadAddrMisaligned) && !x.uop.exceptionVec(breakPoint) && !TriggerAction.isDmode(x.uop.trigger) 146 ) 147 148 val s2_enqueue = Wire(Vec(enqPortNum, Bool())) 149 for (w <- 0 until enqPortNum) { 150 s2_enqueue(w) := s2_valid(w) && s2_miss_aligned(w) 151 } 152 153 when (req_valid && req.uop.robIdx.needFlush(io.redirect)) { 154 req_valid := s2_enqueue.asUInt.orR 155 } .elsewhen (s2_enqueue.asUInt.orR) { 156 req_valid := req_valid || true.B 157 } 158 159 val reqSel = selectOldest(s2_enqueue, s2_req) 160 161 when (req_valid) { 162 req := Mux( 163 reqSel._1(0) && (isAfter(req.uop.robIdx, reqSel._2(0).uop.robIdx) || (isNotBefore(req.uop.robIdx, reqSel._2(0).uop.robIdx) && req.uop.uopIdx > reqSel._2(0).uop.uopIdx)), 164 reqSel._2(0), 165 req) 166 } .elsewhen (s2_enqueue.asUInt.orR) { 167 req := reqSel._2(0) 168 } 169 170 val robMatch = req_valid && io.rob.pendingld && (io.rob.pendingPtr === req.uop.robIdx) 171 172 // buffer control: 173 // - split miss-aligned load into aligned loads 174 // - send split load to ldu and get result from ldu 175 // - merge them and write back to rob 176 val s_idle :: s_split :: s_req :: s_resp :: s_comb :: s_wb :: s_wait :: Nil = Enum(7) 177 val bufferState = RegInit(s_idle) 178 val splitLoadReqs = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LsPipelineBundle)))) 179 val splitLoadResp = RegInit(VecInit(List.fill(maxSplitNum)(0.U.asTypeOf(new LqWriteBundle)))) 180 val unSentLoads = RegInit(0.U(maxSplitNum.W)) 181 val curPtr = RegInit(0.U(log2Ceil(maxSplitNum).W)) 182 183 // if there is exception or mmio in split load 184 val globalException = RegInit(false.B) 185 val globalMMIO = RegInit(false.B) 186 187 val hasException = ExceptionNO.selectByFu(io.splitLoadResp.bits.uop.exceptionVec, LduCfg).asUInt.orR 188 val isMMIO = io.splitLoadResp.bits.mmio 189 190 switch(bufferState) { 191 is (s_idle) { 192 when (robMatch) { 193 bufferState := s_split 194 } 195 } 196 197 is (s_split) { 198 bufferState := s_req 199 } 200 201 is (s_req) { 202 when (io.splitLoadReq.fire) { 203 bufferState := s_resp 204 } 205 } 206 207 is (s_resp) { 208 when (io.splitLoadResp.valid) { 209 val clearOh = UIntToOH(curPtr) 210 when (hasException || isMMIO) { 211 // commit directly when exception ocurs 212 // if any split load reaches mmio space, delegate to software loadAddrMisaligned exception 213 bufferState := s_wb 214 globalException := hasException 215 globalMMIO := isMMIO 216 } .elsewhen(io.splitLoadResp.bits.rep_info.need_rep || (unSentLoads & ~clearOh).orR) { 217 // need replay or still has unsent requests 218 bufferState := s_req 219 } .otherwise { 220 // merge the split load results 221 bufferState := s_comb 222 } 223 } 224 } 225 226 is (s_comb) { 227 bufferState := s_wb 228 } 229 230 is (s_wb) { 231 when(io.writeBack.fire) { 232 bufferState := s_wait 233 } 234 } 235 236 is (s_wait) { 237 when(io.rob.lcommit =/= 0.U || req.uop.robIdx.needFlush(io.redirect)) { 238 // rob commits the unaligned load or handled the exception, reset all state 239 bufferState := s_idle 240 req_valid := false.B 241 curPtr := 0.U 242 unSentLoads := 0.U 243 globalException := false.B 244 globalMMIO := false.B 245 } 246 } 247 } 248 249 val highAddress = LookupTree(req.uop.fuOpType(1, 0), List( 250 LB -> 0.U, 251 LH -> 1.U, 252 LW -> 3.U, 253 LD -> 7.U 254 )) + req.vaddr(4, 0) 255 // to see if (vaddr + opSize - 1) and vaddr are in the same 16 bytes region 256 val cross16BytesBoundary = req_valid && (highAddress(4) =/= req.vaddr(4)) 257 val aligned16BytesAddr = (req.vaddr >> 4) << 4// req.vaddr & ~("b1111".U) 258 val aligned16BytesSel = req.vaddr(3, 0) 259 260 // meta of 128 bit load 261 val new128Load = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 262 // meta of split loads 263 val lowAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 264 val highAddrLoad = WireInit(0.U.asTypeOf(new LsPipelineBundle)) 265 val lowResultShift = RegInit(0.U(3.W)) // how many bytes should we shift right when got result 266 val lowResultWidth = RegInit(0.U(3.W)) // how many bytes should we take from result 267 val highResultShift = RegInit(0.U(3.W)) 268 val highResultWidth = RegInit(0.U(3.W)) 269 270 when (bufferState === s_split) { 271 when (!cross16BytesBoundary) { 272 // change this unaligned load into a 128 bits load 273 unSentLoads := 1.U 274 curPtr := 0.U 275 new128Load.vaddr := aligned16BytesAddr 276 // new128Load.mask := (getMask(req.uop.fuOpType(1, 0)) << aligned16BytesSel).asUInt 277 new128Load.mask := 0xffff.U 278 new128Load.uop := req.uop 279 new128Load.uop.exceptionVec(loadAddrMisaligned) := false.B 280 new128Load.is128bit := true.B 281 splitLoadReqs(0) := new128Load 282 } .otherwise { 283 // split this unaligned load into `maxSplitNum` aligned loads 284 unSentLoads := Fill(maxSplitNum, 1.U(1.W)) 285 curPtr := 0.U 286 lowAddrLoad.uop := req.uop 287 lowAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 288 highAddrLoad.uop := req.uop 289 highAddrLoad.uop.exceptionVec(loadAddrMisaligned) := false.B 290 291 switch (req.uop.fuOpType(1, 0)) { 292 is (LB) { 293 assert(false.B, "lb should not trigger miss align") 294 } 295 296 is (LH) { 297 lowAddrLoad.uop.fuOpType := LB 298 lowAddrLoad.vaddr := req.vaddr 299 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 300 lowResultShift := BYTE0 301 lowResultWidth := BYTE1 302 303 highAddrLoad.uop.fuOpType := LB 304 highAddrLoad.vaddr := req.vaddr + 1.U 305 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 306 highResultShift := BYTE0 307 highResultWidth := BYTE1 308 } 309 310 is (LW) { 311 switch (req.vaddr(1, 0)) { 312 is ("b00".U) { 313 assert(false.B, "should not trigger miss align") 314 } 315 316 is ("b01".U) { 317 lowAddrLoad.uop.fuOpType := LW 318 lowAddrLoad.vaddr := req.vaddr - 1.U 319 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 320 lowResultShift := BYTE1 321 lowResultWidth := BYTE3 322 323 highAddrLoad.uop.fuOpType := LB 324 highAddrLoad.vaddr := req.vaddr + 3.U 325 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 326 highResultShift := BYTE0 327 highResultWidth := BYTE1 328 } 329 330 is ("b10".U) { 331 lowAddrLoad.uop.fuOpType := LH 332 lowAddrLoad.vaddr := req.vaddr 333 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 334 lowResultShift := BYTE0 335 lowResultWidth := BYTE2 336 337 highAddrLoad.uop.fuOpType := LH 338 highAddrLoad.vaddr := req.vaddr + 2.U 339 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 340 highResultShift := BYTE0 341 highResultWidth := BYTE2 342 } 343 344 is ("b11".U) { 345 lowAddrLoad.uop.fuOpType := LB 346 lowAddrLoad.vaddr := req.vaddr 347 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 348 lowResultShift := BYTE0 349 lowResultWidth := BYTE1 350 351 highAddrLoad.uop.fuOpType := LW 352 highAddrLoad.vaddr := req.vaddr + 1.U 353 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 354 highResultShift := BYTE0 355 highResultWidth := BYTE3 356 } 357 } 358 } 359 360 is (LD) { 361 switch (req.vaddr(2, 0)) { 362 is ("b000".U) { 363 assert(false.B, "should not trigger miss align") 364 } 365 366 is ("b001".U) { 367 lowAddrLoad.uop.fuOpType := LD 368 lowAddrLoad.vaddr := req.vaddr - 1.U 369 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 370 lowResultShift := BYTE1 371 lowResultWidth := BYTE7 372 373 highAddrLoad.uop.fuOpType := LB 374 highAddrLoad.vaddr := req.vaddr + 7.U 375 highAddrLoad.mask := 0x1.U << highAddrLoad.vaddr(3, 0) 376 highResultShift := BYTE0 377 highResultWidth := BYTE1 378 } 379 380 is ("b010".U) { 381 lowAddrLoad.uop.fuOpType := LD 382 lowAddrLoad.vaddr := req.vaddr - 2.U 383 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 384 lowResultShift := BYTE2 385 lowResultWidth := BYTE6 386 387 highAddrLoad.uop.fuOpType := LH 388 highAddrLoad.vaddr := req.vaddr + 6.U 389 highAddrLoad.mask := 0x3.U << highAddrLoad.vaddr(3, 0) 390 highResultShift := BYTE0 391 highResultWidth := BYTE2 392 } 393 394 is ("b011".U) { 395 lowAddrLoad.uop.fuOpType := LD 396 lowAddrLoad.vaddr := req.vaddr - 3.U 397 lowAddrLoad.mask := 0xff.U << lowAddrLoad.vaddr(3, 0) 398 lowResultShift := BYTE3 399 lowResultWidth := BYTE5 400 401 highAddrLoad.uop.fuOpType := LW 402 highAddrLoad.vaddr := req.vaddr + 5.U 403 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 404 highResultShift := BYTE0 405 highResultWidth := BYTE3 406 } 407 408 is ("b100".U) { 409 lowAddrLoad.uop.fuOpType := LW 410 lowAddrLoad.vaddr := req.vaddr 411 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 412 lowResultShift := BYTE0 413 lowResultWidth := BYTE4 414 415 highAddrLoad.uop.fuOpType := LW 416 highAddrLoad.vaddr := req.vaddr + 4.U 417 highAddrLoad.mask := 0xf.U << highAddrLoad.vaddr(3, 0) 418 highResultShift := BYTE0 419 highResultWidth := BYTE4 420 } 421 422 is ("b101".U) { 423 lowAddrLoad.uop.fuOpType := LW 424 lowAddrLoad.vaddr := req.vaddr - 1.U 425 lowAddrLoad.mask := 0xf.U << lowAddrLoad.vaddr(3, 0) 426 lowResultShift := BYTE1 427 lowResultWidth := BYTE3 428 429 highAddrLoad.uop.fuOpType := LD 430 highAddrLoad.vaddr := req.vaddr + 3.U 431 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 432 highResultShift := BYTE0 433 highResultWidth := BYTE5 434 } 435 436 is ("b110".U) { 437 lowAddrLoad.uop.fuOpType := LH 438 lowAddrLoad.vaddr := req.vaddr 439 lowAddrLoad.mask := 0x3.U << lowAddrLoad.vaddr(3, 0) 440 lowResultShift := BYTE0 441 lowResultWidth := BYTE2 442 443 highAddrLoad.uop.fuOpType := LD 444 highAddrLoad.vaddr := req.vaddr + 2.U 445 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 446 highResultShift := BYTE0 447 highResultWidth := BYTE6 448 } 449 450 is ("b111".U) { 451 lowAddrLoad.uop.fuOpType := LB 452 lowAddrLoad.vaddr := req.vaddr 453 lowAddrLoad.mask := 0x1.U << lowAddrLoad.vaddr(3, 0) 454 lowResultShift := BYTE0 455 lowResultWidth := BYTE1 456 457 highAddrLoad.uop.fuOpType := LD 458 highAddrLoad.vaddr := req.vaddr + 1.U 459 highAddrLoad.mask := 0xff.U << highAddrLoad.vaddr(3, 0) 460 highResultShift := BYTE0 461 highResultWidth := BYTE7 462 } 463 } 464 } 465 } 466 467 splitLoadReqs(0) := lowAddrLoad 468 splitLoadReqs(1) := highAddrLoad 469 } 470 } 471 472 io.splitLoadReq.valid := req_valid && (bufferState === s_req) 473 io.splitLoadReq.bits := splitLoadReqs(curPtr) 474 475 when (io.splitLoadResp.valid) { 476 splitLoadResp(curPtr) := io.splitLoadResp.bits 477 when (isMMIO) { 478 unSentLoads := 0.U 479 splitLoadResp(curPtr).uop.exceptionVec := 0.U.asTypeOf(ExceptionVec()) 480 // delegate to software 481 splitLoadResp(curPtr).uop.exceptionVec(loadAddrMisaligned) := true.B 482 } .elsewhen (hasException) { 483 unSentLoads := 0.U 484 } .elsewhen (!io.splitLoadResp.bits.rep_info.need_rep) { 485 unSentLoads := unSentLoads & ~UIntToOH(curPtr) 486 curPtr := curPtr + 1.U 487 } 488 } 489 490 val combinedData = RegInit(0.U(XLEN.W)) 491 492 when (bufferState === s_comb) { 493 when (!cross16BytesBoundary) { 494 val shiftData = LookupTree(aligned16BytesSel, List( 495 "b0000".U -> splitLoadResp(0).data(63, 0), 496 "b0001".U -> splitLoadResp(0).data(71, 8), 497 "b0010".U -> splitLoadResp(0).data(79, 16), 498 "b0011".U -> splitLoadResp(0).data(87, 24), 499 "b0100".U -> splitLoadResp(0).data(95, 32), 500 "b0101".U -> splitLoadResp(0).data(103, 40), 501 "b0110".U -> splitLoadResp(0).data(111, 48), 502 "b0111".U -> splitLoadResp(0).data(119, 56), 503 "b1000".U -> splitLoadResp(0).data(127, 64), 504 "b1001".U -> splitLoadResp(0).data(127, 72), 505 "b1010".U -> splitLoadResp(0).data(127, 80), 506 "b1011".U -> splitLoadResp(0).data(127, 88), 507 "b1100".U -> splitLoadResp(0).data(127, 96), 508 "b1101".U -> splitLoadResp(0).data(127, 104), 509 "b1110".U -> splitLoadResp(0).data(127, 112), 510 "b1111".U -> splitLoadResp(0).data(127, 120) 511 )) 512 val truncateData = LookupTree(req.uop.fuOpType(1, 0), List( 513 LB -> shiftData(7, 0), // lb 514 LH -> shiftData(15, 0), // lh 515 LW -> shiftData(31, 0), // lw 516 LD -> shiftData(63, 0) // ld 517 )) 518 combinedData := rdataHelper(req.uop, truncateData(XLEN - 1, 0)) 519 } .otherwise { 520 val lowAddrResult = getShiftAndTruncateData(lowResultShift, lowResultWidth, splitLoadResp(0).data) 521 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 522 val highAddrResult = getShiftAndTruncateData(highResultShift, highResultWidth, splitLoadResp(1).data) 523 .asTypeOf(Vec(XLEN / 8, UInt(8.W))) 524 val catResult = Wire(Vec(XLEN / 8, UInt(8.W))) 525 (0 until XLEN / 8) .map { 526 case i => { 527 when (i.U < lowResultWidth) { 528 catResult(i) := lowAddrResult(i) 529 } .otherwise { 530 catResult(i) := highAddrResult(i.U - lowResultWidth) 531 } 532 } 533 } 534 combinedData := rdataHelper(req.uop, (catResult.asUInt)(XLEN - 1, 0)) 535 } 536 } 537 538 io.writeBack.valid := req_valid && (bufferState === s_wb) 539 io.writeBack.bits.uop := req.uop 540 io.writeBack.bits.uop.exceptionVec := Mux( 541 globalMMIO || globalException, 542 splitLoadResp(curPtr).uop.exceptionVec, 543 0.U.asTypeOf(ExceptionVec()) // TODO: is this ok? 544 ) 545 io.writeBack.bits.uop.flushPipe := Mux(globalMMIO || globalException, false.B, true.B) 546 io.writeBack.bits.uop.replayInst := false.B 547 io.writeBack.bits.data := combinedData 548 io.writeBack.bits.debug.isMMIO := globalMMIO 549 io.writeBack.bits.debug.isPerfCnt := false.B 550 io.writeBack.bits.debug.paddr := req.paddr 551 io.writeBack.bits.debug.vaddr := req.vaddr 552 553 val flush = req_valid && req.uop.robIdx.needFlush(io.redirect) 554 555 when (flush && (bufferState =/= s_idle)) { 556 bufferState := s_idle 557 req_valid := false.B 558 curPtr := 0.U 559 unSentLoads := 0.U 560 globalException := false.B 561 globalMMIO := false.B 562 } 563 564 // NOTE: spectial case (unaligned load cross page, page fault happens in next page) 565 // if exception happens in the higher page address part, overwrite the loadExceptionBuffer vaddr 566 val overwriteExpBuf = GatedValidRegNext(req_valid && cross16BytesBoundary && globalException && (curPtr === 1.U)) 567 val overwriteAddr = GatedRegNext(splitLoadResp(curPtr).vaddr) 568 569 io.overwriteExpBuf.valid := overwriteExpBuf 570 io.overwriteExpBuf.vaddr := overwriteAddr 571 572 // when no exception or mmio, flush loadExceptionBuffer at s_wb 573 val flushLdExpBuff = GatedValidRegNext(req_valid && (bufferState === s_wb) && !(globalMMIO || globalException)) 574 io.flushLdExpBuff := flushLdExpBuff 575 576 XSPerfAccumulate("alloc", RegNext(!req_valid) && req_valid) 577 XSPerfAccumulate("flush", flush) 578 XSPerfAccumulate("flush_idle", flush && (bufferState === s_idle)) 579 XSPerfAccumulate("flush_non_idle", flush && (bufferState =/= s_idle)) 580}