1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache._ 25import xiangshan.cache.{DCacheWordIO, DCacheLineIO, MemoryOpConstants} 26import xiangshan.cache.mmu.{TlbRequestIO} 27import xiangshan.mem._ 28import xiangshan.backend.roq.RoqLsqIO 29 30class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 31 val lsIdx = Input(new LSIdx) 32 val isStore = Input(Bool()) 33 val vaddr = Output(UInt(VAddrBits.W)) 34} 35 36class FwdEntry extends Bundle { 37 val valid = Bool() 38 val data = UInt(8.W) 39} 40 41// inflight miss block reqs 42class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 43 val block_addr = UInt(PAddrBits.W) 44 val valid = Bool() 45} 46 47class LsqEnqIO(implicit p: Parameters) extends XSBundle { 48 val canAccept = Output(Bool()) 49 val needAlloc = Vec(RenameWidth, Input(UInt(2.W))) 50 val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp))) 51 val resp = Vec(RenameWidth, Output(new LSIdx)) 52} 53 54// Load / Store Queue Wrapper for XiangShan Out of Order LSU 55class LsqWrappper(implicit p: Parameters) extends XSModule with HasDCacheParameters { 56 val io = IO(new Bundle() { 57 val enq = new LsqEnqIO 58 val brqRedirect = Flipped(ValidIO(new Redirect)) 59 val flush = Input(Bool()) 60 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 61 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) 62 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreDataBundle))) // store data, send to sq from rs 63 val loadDataForwarded = Vec(LoadPipelineWidth, Input(Bool())) 64 val needReplayFromRS = Vec(LoadPipelineWidth, Input(Bool())) 65 val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReq)) 66 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback int load 67 val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store 68 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 69 val roq = Flipped(new RoqLsqIO) 70 val rollback = Output(Valid(new Redirect)) 71 val dcache = Flipped(ValidIO(new Refill)) 72 val uncache = new DCacheWordIO 73 val exceptionAddr = new ExceptionAddrIO 74 val sqempty = Output(Bool()) 75 val issuePtrExt = Output(new SqPtr) 76 val storeIssue = Vec(StorePipelineWidth, Flipped(Valid(new ExuInput))) 77 val sqFull = Output(Bool()) 78 val lqFull = Output(Bool()) 79 }) 80 81 val loadQueue = Module(new LoadQueue) 82 val storeQueue = Module(new StoreQueue) 83 84 // io.enq logic 85 // LSQ: send out canAccept when both load queue and store queue are ready 86 // Dispatch: send instructions to LSQ only when they are ready 87 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 88 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 89 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 90 for (i <- 0 until RenameWidth) { 91 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 92 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 93 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 94 95 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 96 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 97 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 98 99 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 100 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 101 } 102 103 // load queue wiring 104 loadQueue.io.brqRedirect <> io.brqRedirect 105 loadQueue.io.flush <> io.flush 106 loadQueue.io.loadIn <> io.loadIn 107 loadQueue.io.storeIn <> io.storeIn 108 loadQueue.io.loadDataForwarded <> io.loadDataForwarded 109 loadQueue.io.needReplayFromRS <> io.needReplayFromRS 110 loadQueue.io.ldout <> io.ldout 111 loadQueue.io.roq <> io.roq 112 loadQueue.io.rollback <> io.rollback 113 loadQueue.io.dcache <> io.dcache 114 loadQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 115 loadQueue.io.exceptionAddr.isStore := DontCare 116 117 // store queue wiring 118 // storeQueue.io <> DontCare 119 storeQueue.io.brqRedirect <> io.brqRedirect 120 storeQueue.io.flush <> io.flush 121 storeQueue.io.storeIn <> io.storeIn 122 storeQueue.io.storeDataIn <> io.storeDataIn 123 storeQueue.io.sbuffer <> io.sbuffer 124 storeQueue.io.mmioStout <> io.mmioStout 125 storeQueue.io.roq <> io.roq 126 storeQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 127 storeQueue.io.exceptionAddr.isStore := DontCare 128 storeQueue.io.issuePtrExt <> io.issuePtrExt 129 storeQueue.io.storeIssue <> io.storeIssue 130 131 loadQueue.io.load_s1 <> io.forward 132 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 133 134 storeQueue.io.sqempty <> io.sqempty 135 136 io.exceptionAddr.vaddr := Mux(io.exceptionAddr.isStore, storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 137 138 // naive uncache arbiter 139 val s_idle :: s_load :: s_store :: Nil = Enum(3) 140 val pendingstate = RegInit(s_idle) 141 142 switch(pendingstate){ 143 is(s_idle){ 144 when(io.uncache.req.fire()){ 145 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, s_store) 146 } 147 } 148 is(s_load){ 149 when(io.uncache.resp.fire()){ 150 pendingstate := s_idle 151 } 152 } 153 is(s_store){ 154 when(io.uncache.resp.fire()){ 155 pendingstate := s_idle 156 } 157 } 158 } 159 160 loadQueue.io.uncache := DontCare 161 storeQueue.io.uncache := DontCare 162 loadQueue.io.uncache.resp.valid := false.B 163 storeQueue.io.uncache.resp.valid := false.B 164 when(loadQueue.io.uncache.req.valid){ 165 io.uncache.req <> loadQueue.io.uncache.req 166 }.otherwise{ 167 io.uncache.req <> storeQueue.io.uncache.req 168 } 169 when(pendingstate === s_load){ 170 io.uncache.resp <> loadQueue.io.uncache.resp 171 }.otherwise{ 172 io.uncache.resp <> storeQueue.io.uncache.resp 173 } 174 175 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 176 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 177 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 178 179 io.lqFull := loadQueue.io.lqFull 180 io.sqFull := storeQueue.io.sqFull 181} 182