1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache._ 25import xiangshan.cache.{DCacheWordIO, DCacheLineIO, MemoryOpConstants} 26import xiangshan.cache.mmu.{TlbRequestIO} 27import xiangshan.mem._ 28import xiangshan.backend.rob.RobLsqIO 29 30class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 31 val lsIdx = Input(new LSIdx) 32 val isStore = Input(Bool()) 33 val vaddr = Output(UInt(VAddrBits.W)) 34} 35 36class FwdEntry extends Bundle { 37 val validFast = Bool() // validFast is generated the same cycle with query 38 val valid = Bool() // valid is generated 1 cycle after query request 39 val data = UInt(8.W) // data is generated 1 cycle after query request 40} 41 42// inflight miss block reqs 43class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 44 val block_addr = UInt(PAddrBits.W) 45 val valid = Bool() 46} 47 48class LsqEnqIO(implicit p: Parameters) extends XSBundle { 49 val canAccept = Output(Bool()) 50 val needAlloc = Vec(exuParameters.LsExuCnt, Input(UInt(2.W))) 51 val req = Vec(exuParameters.LsExuCnt, Flipped(ValidIO(new MicroOp))) 52 val resp = Vec(exuParameters.LsExuCnt, Output(new LSIdx)) 53} 54 55// Load / Store Queue Wrapper for XiangShan Out of Order LSU 56class LsqWrappper(implicit p: Parameters) extends XSModule with HasDCacheParameters { 57 val io = IO(new Bundle() { 58 val hartId = Input(UInt(8.W)) 59 val enq = new LsqEnqIO 60 val brqRedirect = Flipped(ValidIO(new Redirect)) 61 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 62 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) 63 val storeInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) 64 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreDataBundle))) // store data, send to sq from rs 65 val loadDataForwarded = Vec(LoadPipelineWidth, Input(Bool())) 66 val needReplayFromRS = Vec(LoadPipelineWidth, Input(Bool())) 67 val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReqWithVaddr)) 68 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback int load 69 val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store 70 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 71 val loadViolationQuery = Vec(LoadPipelineWidth, Flipped(new LoadViolationQueryIO)) 72 val rob = Flipped(new RobLsqIO) 73 val rollback = Output(Valid(new Redirect)) 74 val dcache = Flipped(ValidIO(new Refill)) 75 val release = Flipped(ValidIO(new Release)) 76 val uncache = new DCacheWordIO 77 val exceptionAddr = new ExceptionAddrIO 78 val sqempty = Output(Bool()) 79 val issuePtrExt = Output(new SqPtr) 80 val sqFull = Output(Bool()) 81 val lqFull = Output(Bool()) 82 }) 83 84 val loadQueue = Module(new LoadQueue) 85 val storeQueue = Module(new StoreQueue) 86 87 storeQueue.io.hartId := io.hartId 88 89 // io.enq logic 90 // LSQ: send out canAccept when both load queue and store queue are ready 91 // Dispatch: send instructions to LSQ only when they are ready 92 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 93 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 94 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 95 for (i <- io.enq.req.indices) { 96 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 97 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 98 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 99 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 100 101 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 102 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 103 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 104 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 105 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 106 107 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 108 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 109 } 110 111 // load queue wiring 112 loadQueue.io.brqRedirect <> io.brqRedirect 113 loadQueue.io.loadIn <> io.loadIn 114 loadQueue.io.storeIn <> io.storeIn 115 loadQueue.io.loadDataForwarded <> io.loadDataForwarded 116 loadQueue.io.needReplayFromRS <> io.needReplayFromRS 117 loadQueue.io.ldout <> io.ldout 118 loadQueue.io.rob <> io.rob 119 loadQueue.io.rollback <> io.rollback 120 loadQueue.io.dcache <> io.dcache 121 loadQueue.io.release <> io.release 122 loadQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 123 loadQueue.io.exceptionAddr.isStore := DontCare 124 125 // store queue wiring 126 // storeQueue.io <> DontCare 127 storeQueue.io.brqRedirect <> io.brqRedirect 128 storeQueue.io.storeIn <> io.storeIn 129 storeQueue.io.storeInRe <> io.storeInRe 130 storeQueue.io.storeDataIn <> io.storeDataIn 131 storeQueue.io.sbuffer <> io.sbuffer 132 storeQueue.io.mmioStout <> io.mmioStout 133 storeQueue.io.rob <> io.rob 134 storeQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 135 storeQueue.io.exceptionAddr.isStore := DontCare 136 storeQueue.io.issuePtrExt <> io.issuePtrExt 137 138 loadQueue.io.load_s1 <> io.forward 139 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 140 141 loadQueue.io.loadViolationQuery <> io.loadViolationQuery 142 143 storeQueue.io.sqempty <> io.sqempty 144 145 io.exceptionAddr.vaddr := Mux(io.exceptionAddr.isStore, storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 146 147 // naive uncache arbiter 148 val s_idle :: s_load :: s_store :: Nil = Enum(3) 149 val pendingstate = RegInit(s_idle) 150 151 switch(pendingstate){ 152 is(s_idle){ 153 when(io.uncache.req.fire()){ 154 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, s_store) 155 } 156 } 157 is(s_load){ 158 when(io.uncache.resp.fire()){ 159 pendingstate := s_idle 160 } 161 } 162 is(s_store){ 163 when(io.uncache.resp.fire()){ 164 pendingstate := s_idle 165 } 166 } 167 } 168 169 loadQueue.io.uncache := DontCare 170 storeQueue.io.uncache := DontCare 171 loadQueue.io.uncache.resp.valid := false.B 172 storeQueue.io.uncache.resp.valid := false.B 173 when(loadQueue.io.uncache.req.valid){ 174 io.uncache.req <> loadQueue.io.uncache.req 175 }.otherwise{ 176 io.uncache.req <> storeQueue.io.uncache.req 177 } 178 when(pendingstate === s_load){ 179 io.uncache.resp <> loadQueue.io.uncache.resp 180 }.otherwise{ 181 io.uncache.resp <> storeQueue.io.uncache.resp 182 } 183 184 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 185 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 186 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 187 188 io.lqFull := loadQueue.io.lqFull 189 io.sqFull := storeQueue.io.sqFull 190 191 val ldq_perf = loadQueue.perfEvents.map(_._1).zip(loadQueue.perfinfo.perfEvents.perf_events) 192 val stq_perf = storeQueue.perfEvents.map(_._1).zip(storeQueue.perfinfo.perfEvents.perf_events) 193 val perfEvents = ldq_perf ++ stq_perf 194 val perf_list = storeQueue.perfinfo.perfEvents.perf_events ++ loadQueue.perfinfo.perfEvents.perf_events 195 val perfinfo = IO(new Bundle(){ 196 val perfEvents = Output(new PerfEventsBundle(perf_list.length)) 197 }) 198 perfinfo.perfEvents.perf_events := perf_list 199} 200