1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8import xiangshan.cache.{DCacheWordIO, DCacheLineIO, TlbRequestIO, MemoryOpConstants} 9import xiangshan.backend.LSUOpType 10import xiangshan.mem._ 11import xiangshan.backend.roq.RoqLsqIO 12 13class ExceptionAddrIO extends XSBundle { 14 val lsIdx = Input(new LSIdx) 15 val isStore = Input(Bool()) 16 val vaddr = Output(UInt(VAddrBits.W)) 17} 18 19class FwdEntry extends XSBundle { 20 val valid = Bool() 21 val data = UInt(8.W) 22} 23 24// inflight miss block reqs 25class InflightBlockInfo extends XSBundle { 26 val block_addr = UInt(PAddrBits.W) 27 val valid = Bool() 28} 29 30class LsqEnqIO extends XSBundle { 31 val canAccept = Output(Bool()) 32 val needAlloc = Vec(RenameWidth, Input(Bool())) 33 val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp))) 34 val resp = Vec(RenameWidth, Output(new LSIdx)) 35} 36 37// Load / Store Queue Wrapper for XiangShan Out of Order LSU 38class LsqWrappper extends XSModule with HasDCacheParameters { 39 val io = IO(new Bundle() { 40 val enq = new LsqEnqIO 41 val brqRedirect = Flipped(ValidIO(new Redirect)) 42 val flush = Input(Bool()) 43 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 44 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) 45 val loadDataForwarded = Vec(LoadPipelineWidth, Input(Bool())) 46 val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReq)) 47 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback int load 48 val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store 49 val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO)) 50 val roq = Flipped(new RoqLsqIO) 51 val rollback = Output(Valid(new Redirect)) 52 val dcache = Flipped(ValidIO(new Refill)) 53 val uncache = new DCacheWordIO 54 val exceptionAddr = new ExceptionAddrIO 55 val sqempty = Output(Bool()) 56 }) 57 val difftestIO = IO(new Bundle() { 58 val fromSQ = new Bundle() { 59 val storeCommit = Output(UInt(2.W)) 60 val storeAddr = Output(Vec(2, UInt(64.W))) 61 val storeData = Output(Vec(2, UInt(64.W))) 62 val storeMask = Output(Vec(2, UInt(8.W))) 63 } 64 }) 65 difftestIO <> DontCare 66 67 val loadQueue = Module(new LoadQueue) 68 val storeQueue = Module(new StoreQueue) 69 70 // io.enq logic 71 // LSQ: send out canAccept when both load queue and store queue are ready 72 // Dispatch: send instructions to LSQ only when they are ready 73 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 74 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 75 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 76 for (i <- 0 until RenameWidth) { 77 val isStore = CommitType.lsInstIsStore(io.enq.req(i).bits.ctrl.commitType) 78 79 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i) && !isStore 80 loadQueue.io.enq.req(i).valid := !isStore && io.enq.req(i).valid 81 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 82 83 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i) && isStore 84 storeQueue.io.enq.req(i).valid := isStore && io.enq.req(i).valid 85 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 86 87 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 88 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 89 } 90 91 // load queue wiring 92 loadQueue.io.brqRedirect <> io.brqRedirect 93 loadQueue.io.flush <> io.flush 94 loadQueue.io.loadIn <> io.loadIn 95 loadQueue.io.storeIn <> io.storeIn 96 loadQueue.io.loadDataForwarded <> io.loadDataForwarded 97 loadQueue.io.ldout <> io.ldout 98 loadQueue.io.roq <> io.roq 99 loadQueue.io.rollback <> io.rollback 100 loadQueue.io.dcache <> io.dcache 101 loadQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 102 loadQueue.io.exceptionAddr.isStore := DontCare 103 104 // store queue wiring 105 // storeQueue.io <> DontCare 106 storeQueue.io.brqRedirect <> io.brqRedirect 107 storeQueue.io.flush <> io.flush 108 storeQueue.io.storeIn <> io.storeIn 109 storeQueue.io.sbuffer <> io.sbuffer 110 storeQueue.io.mmioStout <> io.mmioStout 111 storeQueue.io.roq <> io.roq 112 storeQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 113 storeQueue.io.exceptionAddr.isStore := DontCare 114 115 loadQueue.io.load_s1 <> io.forward 116 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 117 118 storeQueue.io.sqempty <> io.sqempty 119 120 if (env.DualCoreDifftest) { 121 difftestIO.fromSQ <> storeQueue.difftestIO 122 } 123 124 io.exceptionAddr.vaddr := Mux(io.exceptionAddr.isStore, storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 125 126 // naive uncache arbiter 127 val s_idle :: s_load :: s_store :: Nil = Enum(3) 128 val pendingstate = RegInit(s_idle) 129 130 switch(pendingstate){ 131 is(s_idle){ 132 when(io.uncache.req.fire()){ 133 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, s_store) 134 } 135 } 136 is(s_load){ 137 when(io.uncache.resp.fire()){ 138 pendingstate := s_idle 139 } 140 } 141 is(s_store){ 142 when(io.uncache.resp.fire()){ 143 pendingstate := s_idle 144 } 145 } 146 } 147 148 loadQueue.io.uncache := DontCare 149 storeQueue.io.uncache := DontCare 150 loadQueue.io.uncache.resp.valid := false.B 151 storeQueue.io.uncache.resp.valid := false.B 152 when(loadQueue.io.uncache.req.valid){ 153 io.uncache.req <> loadQueue.io.uncache.req 154 }.otherwise{ 155 io.uncache.req <> storeQueue.io.uncache.req 156 } 157 when(pendingstate === s_load){ 158 io.uncache.resp <> loadQueue.io.uncache.resp 159 }.otherwise{ 160 io.uncache.resp <> storeQueue.io.uncache.resp 161 } 162 163 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 164 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 165 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 166 167} 168