1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8import xiangshan.cache.{DCacheWordIO, DCacheLineIO, TlbRequestIO, MemoryOpConstants} 9import xiangshan.backend.LSUOpType 10import xiangshan.mem._ 11import xiangshan.backend.roq.RoqLsqIO 12 13class ExceptionAddrIO extends XSBundle { 14 val lsIdx = Input(new LSIdx) 15 val isStore = Input(Bool()) 16 val vaddr = Output(UInt(VAddrBits.W)) 17} 18 19class FwdEntry extends XSBundle { 20 val mask = Vec(8, Bool()) 21 val data = Vec(8, UInt(8.W)) 22} 23 24// inflight miss block reqs 25class InflightBlockInfo extends XSBundle { 26 val block_addr = UInt(PAddrBits.W) 27 val valid = Bool() 28} 29 30class LsqEnqIO extends XSBundle { 31 val canAccept = Output(Bool()) 32 val needAlloc = Vec(RenameWidth, Input(Bool())) 33 val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp))) 34 val resp = Vec(RenameWidth, Output(new LSIdx)) 35} 36 37// Load / Store Queue Wrapper for XiangShan Out of Order LSU 38class LsqWrappper extends XSModule with HasDCacheParameters { 39 val io = IO(new Bundle() { 40 val enq = new LsqEnqIO 41 val brqRedirect = Input(Valid(new Redirect)) 42 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 43 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) 44 val loadDataForwarded = Vec(LoadPipelineWidth, Input(Bool())) 45 val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReq)) 46 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback int load 47 val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store 48 val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO)) 49 val roq = Flipped(new RoqLsqIO) 50 val rollback = Output(Valid(new Redirect)) 51 val dcache = Flipped(ValidIO(new Refill)) 52 val uncache = new DCacheWordIO 53 val exceptionAddr = new ExceptionAddrIO 54 val sqempty = Output(Bool()) 55 }) 56 val difftestIO = IO(new Bundle() { 57 val fromSQ = new Bundle() { 58 val storeCommit = Output(UInt(2.W)) 59 val storeAddr = Output(Vec(2, UInt(64.W))) 60 val storeData = Output(Vec(2, UInt(64.W))) 61 val storeMask = Output(Vec(2, UInt(8.W))) 62 } 63 }) 64 difftestIO <> DontCare 65 66 val loadQueue = Module(new LoadQueue) 67 val storeQueue = Module(new StoreQueue) 68 69 // io.enq logic 70 // LSQ: send out canAccept when both load queue and store queue are ready 71 // Dispatch: send instructions to LSQ only when they are ready 72 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 73 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 74 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 75 for (i <- 0 until RenameWidth) { 76 val isStore = CommitType.lsInstIsStore(io.enq.req(i).bits.ctrl.commitType) 77 78 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i) && !isStore 79 loadQueue.io.enq.req(i).valid := !isStore && io.enq.req(i).valid 80 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 81 82 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i) && isStore 83 storeQueue.io.enq.req(i).valid := isStore && io.enq.req(i).valid 84 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 85 86 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 87 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 88 } 89 90 // load queue wiring 91 loadQueue.io.brqRedirect <> io.brqRedirect 92 loadQueue.io.loadIn <> io.loadIn 93 loadQueue.io.storeIn <> io.storeIn 94 loadQueue.io.loadDataForwarded <> io.loadDataForwarded 95 loadQueue.io.ldout <> io.ldout 96 loadQueue.io.roq <> io.roq 97 loadQueue.io.rollback <> io.rollback 98 loadQueue.io.dcache <> io.dcache 99 loadQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 100 loadQueue.io.exceptionAddr.isStore := DontCare 101 102 // store queue wiring 103 // storeQueue.io <> DontCare 104 storeQueue.io.brqRedirect <> io.brqRedirect 105 storeQueue.io.storeIn <> io.storeIn 106 storeQueue.io.sbuffer <> io.sbuffer 107 storeQueue.io.mmioStout <> io.mmioStout 108 storeQueue.io.roq <> io.roq 109 storeQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 110 storeQueue.io.exceptionAddr.isStore := DontCare 111 112 loadQueue.io.load_s1 <> io.forward 113 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 114 115 storeQueue.io.sqempty <> io.sqempty 116 117 if (env.DualCoreDifftest) { 118 difftestIO.fromSQ <> storeQueue.difftestIO 119 } 120 121 io.exceptionAddr.vaddr := Mux(io.exceptionAddr.isStore, storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 122 123 // naive uncache arbiter 124 val s_idle :: s_load :: s_store :: Nil = Enum(3) 125 val pendingstate = RegInit(s_idle) 126 127 switch(pendingstate){ 128 is(s_idle){ 129 when(io.uncache.req.fire()){ 130 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, s_store) 131 } 132 } 133 is(s_load){ 134 when(io.uncache.resp.fire()){ 135 pendingstate := s_idle 136 } 137 } 138 is(s_store){ 139 when(io.uncache.resp.fire()){ 140 pendingstate := s_idle 141 } 142 } 143 } 144 145 loadQueue.io.uncache := DontCare 146 storeQueue.io.uncache := DontCare 147 loadQueue.io.uncache.resp.valid := false.B 148 storeQueue.io.uncache.resp.valid := false.B 149 when(loadQueue.io.uncache.req.valid){ 150 io.uncache.req <> loadQueue.io.uncache.req 151 }.otherwise{ 152 io.uncache.req <> storeQueue.io.uncache.req 153 } 154 when(pendingstate === s_load){ 155 io.uncache.resp <> loadQueue.io.uncache.resp 156 }.otherwise{ 157 io.uncache.resp <> storeQueue.io.uncache.resp 158 } 159 160 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 161 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 162 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 163 164} 165